Resistance value detection circuit suitable for line parasitic resistor

Abstract

The utility model provides a resistance value detection circuit suitable for a line parasitic resistor, which relates to the resistance value detection circuit field, and comprises a three-wire system resistance measurement sub-circuit, a first signal processing sub-circuit and a second signal processing sub-circuit, the three-wire system resistance measurement sub-circuit is electrically connected with a resistor to be measured, one end of the three-wire system resistance measurement sub-circuit is grounded, and the other end of the three-wire system resistance measurement sub-circuit is grounded. The first voltage sampling end of the three-wire system resistance measurement sub-circuit is electrically connected with the first signal processing sub-circuit, the second voltage sampling end of the three-wire system resistance measurement sub-circuit is electrically connected with the second signal processing sub-circuit, and the resistance measurement efficiency is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of resistance detection circuit, especially suitable for the resistance detection circuit of line parasitic resistance. BACKGROUND

[0002] When the resistance value of the measured resistance is small, the resistance of the test lead and the contact resistance of the probe and the test point cannot be ignored compared with the measured resistance, and if the two-wire test method is still used, it will inevitably lead to an increase in test error. Figure 1 At this time, the Kelvin connection method (or four-wire test method) shown in the figure can be used for testing. Kelvin connection has two requirements: for each test point, there is an excitation line F (for example, HF, LF) and a detection line S (for example, HS, LS), which are strictly separated and form independent loops respectively; at the same time, the detection line S must be connected to a test circuit with extremely high input impedance, so that the current flowing through the detection line S is extremely small, approximately zero.

[0003] However, the Kelvin test method requires two additional wires to measure voltage, while the traditional two-wire test method only requires two wires to transmit current and measure voltage. This additional wire increases the complexity of the system, especially in the case of multi-point measurement or large-scale system, wiring and management will become complex. Because the Kelvin four-wire system requires additional wires, these wires may act as antennas in long measurement lines and receive external electromagnetic interference, affecting the measurement results.

[0004] Therefore, it is necessary to provide a resistance detection circuit suitable for line parasitic resistance to improve the efficiency of resistance measurement. UTILITY MODEL CONTENT

[0005] The utility model provides a resistance detection circuit suitable for line parasitic resistance, including three -wire system resistance measurement subcircuit, first signal processing subcircuit, second signal processing subcircuit, wherein, three -wire system resistance measurement subcircuit is connected with the resistance to be measured, one end of three -wire system resistance measurement subcircuit is grounded, the first voltage sampling end of three -wire system resistance measurement subcircuit is connected with first signal processing subcircuit, the second voltage sampling end of three -wire system resistance measurement subcircuit is connected with second signal processing subcircuit.

[0006] Further, the three-wire resistance measurement sub-circuit comprises a first wire, a second wire, a third wire and a voltage dividing resistor, one end of the first wire is electrically connected with one end of the voltage dividing resistor, the other end of the voltage dividing resistor is electrically connected with a reference voltage source, the other end of the first wire and one end of the second wire are electrically connected with one end of the resistance to be measured, the other end of the second wire is electrically connected with the second signal processing sub-circuit as a second voltage sampling end, one end of the third wire is electrically connected with the other end of the resistance to be measured, and the other end of the third wire is grounded; a connection node of the voltage dividing resistor and the first wire is electrically connected with the first signal processing sub-circuit as a first voltage sampling end.

[0007] Further, the first signal processing sub-circuit comprises a first amplifier and a first filter, the other end of the first voltage sampling end is electrically connected with a non-inverting terminal of the first amplifier, and an output terminal of the first amplifier is electrically connected with the first filter.

[0008] Further, the first amplifier comprises a first voltage amplifier, a first resistor and a first reference resistor, the first voltage sampling end is electrically connected with a non-inverting terminal of the first voltage amplifier, one end of the first resistor is electrically connected with an inverting terminal of the first voltage amplifier, the other end of the first resistor is grounded, one end of the first reference resistor is electrically connected with an output terminal of the first voltage amplifier, and the other end of the first reference resistor is electrically connected with a connection node of the first resistor and the non-inverting terminal of the first voltage amplifier.

[0009] Further, the first filter comprises a second resistor and a first capacitor, one end of the second resistor is electrically connected with the output terminal of the first voltage amplifier, the other end of the second resistor is an output terminal of the first filter, and one end of the first capacitor is electrically connected with the second resistor.

[0010] Further, the second signal processing sub-circuit comprises a second amplifier and a second filter, the second voltage sampling end is electrically connected with a non-inverting terminal of the second amplifier, and an output terminal of the second amplifier is electrically connected with the second filter.

[0011] Further, the second amplifier comprises a second voltage amplifier, a third resistor and a second reference resistor, the second voltage sampling end is electrically connected with a non-inverting terminal of the second voltage amplifier, one end of the third resistor is electrically connected with an inverting terminal of the second voltage amplifier, the other end of the third resistor is grounded, one end of the second reference resistor is electrically connected with an output terminal of the second voltage amplifier, and the other end of the second reference resistor is electrically connected with a connection node of the third resistor and the non-inverting terminal of the second voltage amplifier.

[0012] Further, the second filter comprises a fourth resistor and a second capacitor, one end of the fourth resistor is electrically connected with the output end of the second voltage amplifier, the other end of the fourth resistor is the output end of the second filter, one end of the second capacitor is electrically connected with the fourth resistor.

[0013] Further, based on the output voltage of the first signal processing sub-circuit, the output voltage of the second signal processing sub-circuit, the output voltage of the reference voltage source and the resistance value of the voltage dividing resistor, the resistance value of the to-be-measured resistor is determined.

[0014] Further, it further comprises a digital-to-analog converter and a processor, one input end of the digital-to-analog converter is electrically connected with the output end of the first signal processing sub-circuit, the other input end of the digital-to-analog converter is electrically connected with the output end of the second signal processing sub-circuit, the output end of the digital-to-analog converter is electrically connected with the input end of the processor.

[0015] Compared with the prior art, the resistance value detection circuit suitable for line parasitic resistance provided by the utility model has at least the following beneficial effects:

[0016] The circuit can effectively eliminate the influence of the parasitic resistance in the line on the measurement result by adopting the three-wire resistance measurement sub-circuit, thereby improving the accuracy of the measurement. The first signal processing sub-circuit and the second signal processing sub-circuit further reduce noise and interference through amplification and filtering processing, thereby ensuring high-precision resistance value measurement. The circuit structure is stable, and reasonable circuit design and component selection can ensure stable operation under various environmental conditions. The selection and configuration of the voltage dividing resistor, the amplifier and the filter and other components are carefully considered to improve the reliability and stability of the circuit. The circuit can be suitable for parasitic resistance measurement of different resistance values, and only the resistance value of the voltage dividing resistor needs to be adjusted. The circuit can be further expanded, for example, multiple measurement channels can be added to simultaneously measure the resistance values of multiple parasitic resistances. The circuit structure is simple and easy to implement and debug. The types and number of components used are relatively small, which reduces the cost and maintenance difficulty. BRIEF DESCRIPTION OF DRAWINGS

[0017] The present specification will be further illustrated in the form of exemplary embodiments, which will be described in detail with reference to the drawings. These embodiments are not limiting, and in these embodiments, the same numbers represent the same structures, wherein:

[0018] Figure 1 is a circuit schematic diagram of the existing Kelvin connection method;

[0019] Figure 2 is a circuit schematic diagram of the resistance value detection circuit suitable for line parasitic resistance according to some embodiments of the present specification. DETAILED DESCRIPTION

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present specification, the drawings required to be used in the embodiment description will be briefly introduced as follows. Obviously, the drawings in the following description are only some examples or embodiments of the present specification, and for those skilled in the art, the present specification can also be applied to other similar scenarios without creative labor on the basis of these drawings. Unless it is obvious from the language environment or otherwise stated, the same reference numerals in the drawings represent the same structure or operation.

[0021] Figure 2 is a circuit schematic diagram of a resistance detection circuit suitable for line parasitic resistance according to some embodiments of the present specification, as Figure 2 shown, the resistance detection circuit suitable for line parasitic resistance can include a three-wire resistance measurement sub-circuit, a first signal processing sub-circuit, and a second signal processing sub-circuit, wherein the three-wire resistance measurement sub-circuit is electrically connected with the resistance to be measured Rt, one end C of the three-wire resistance measurement sub-circuit is grounded, the first voltage sampling end A of the three-wire resistance measurement sub-circuit is electrically connected with the first signal processing sub-circuit, and the second voltage sampling end B of the three-wire resistance measurement sub-circuit is electrically connected with the second signal processing sub-circuit.

[0022] As Figure 2 shown, in some embodiments, the three-wire resistance measurement sub-circuit includes a first wire, a second wire, a third wire, and a voltage dividing resistor RS, one end of the first wire is electrically connected with one end of the voltage dividing resistor RS, the other end of the voltage dividing resistor RS is electrically connected with a reference voltage source REF, the other end of the first wire and one end of the second wire are both electrically connected with one end of the resistance to be measured Rt, the other end of the second wire is electrically connected with the second signal processing sub-circuit as the second voltage sampling end B, one end of the third wire is electrically connected with the other end of the resistance to be measured Rt, and the other end of the third wire is grounded. The connection node of the voltage dividing resistor RS and the first wire is electrically connected with the first signal processing sub-circuit as the first voltage sampling end A. Wherein, r1, r2, r3 are the line inherent resistances of the first wire, the second wire, and the third wire, i.e. parasitic resistances. The first wire, the second wire, and the third wire adopt wires with equal length and same wire diameter, so the line resistances are approximately equal.

[0023] Specifically, a reference voltage source with high power voltage rejection ratio and low noise is selected to provide a basis for high-precision measurement. A stable reference voltage source can reduce fluctuations and errors during measurement, thereby improving signal quality and accuracy. Selecting a high-precision resistor can avoid average error, improve sampling consistency, and provide high-precision results.

[0024] As Figure 2As shown in the figure, in some embodiments, the first signal processing sub-circuit comprises a first amplifier and a first filter, the other end of the first voltage sampling end is electrically connected with the non-inverting terminal of the first amplifier, and the output end of the first amplifier is electrically connected with the first filter. The first amplifier comprises a first voltage amplifier U1, a first resistor R1 and a first reference resistor Rf1, the non-inverting terminal of the first voltage amplifier U1 is electrically connected with the first voltage sampling end A, one end of the first resistor R1 is electrically connected with the inverting terminal of the first voltage amplifier U1, the other end of the first resistor R1 is grounded, one end of the first reference resistor Rf1 is electrically connected with the output end of the first voltage amplifier U1, and the other end of the first reference resistor Rf1 is electrically connected with the node electrically connected with the non-inverting terminal of the first voltage amplifier U1 and the first resistor R1. The first filter comprises a second resistor R2 and a first capacitor C1, one end of the second resistor R2 is electrically connected with the output end of the first voltage amplifier U1, and the other end of the second resistor R2 is the output end of the first filter, and one end of the first capacitor C1 is electrically connected with the second resistor R2.

[0025] As shown in the figure, Figure 2 As shown in the figure, in some embodiments, the second signal processing sub-circuit comprises a second amplifier and a second filter, the second voltage sampling end is electrically connected with the non-inverting terminal of the second amplifier, and the output end of the second amplifier is electrically connected with the second filter. The second amplifier comprises a second voltage amplifier U2, a third resistor R3 and a second reference resistor Rf2, the non-inverting terminal of the second voltage amplifier U2 is electrically connected with the second voltage sampling end B, one end of the third resistor R3 is electrically connected with the inverting terminal of the second voltage amplifier U2, the other end of the third resistor R3 is grounded, one end of the second reference resistor Rf2 is electrically connected with the output end of the second voltage amplifier U2, and the other end of the second reference resistor Rf2 is electrically connected with the node electrically connected with the non-inverting terminal of the second voltage amplifier U2 and the third resistor R3. The second filter comprises a fourth resistor R4 and a second capacitor C2, one end of the fourth resistor R4 is electrically connected with the output end of the second voltage amplifier U2, the other end of the fourth resistor R4 is the output end of the second filter, and one end of the second capacitor C2 is electrically connected with the fourth resistor R4.

[0026] Specifically, using a low-bias current operational amplifier as the first voltage amplifier and the second voltage amplifier can obtain a higher input impedance, and the input virtual break model of the ideal operational amplifier is approximated. Using a low-offset voltage operational amplifier can improve the sensitivity and accuracy.

[0027] It can be understood that the difference between the output voltage of the first signal processing sub-circuit and the output voltage of the second signal processing sub-circuit is different for different resistance values of the to-be-measured resistance Rt, and therefore the resistance value of the to-be-measured resistance Rt can be calculated according to the output voltage of the first signal processing sub-circuit and the output voltage of the second signal processing sub-circuit.

[0028] In some embodiments, the operator can determine the resistance value of the resistance Rt to be measured based on the output voltage of the first signal processing sub-circuit, the output voltage of the second signal processing sub-circuit, the output voltage of the reference voltage source, and the resistance value of the voltage dividing resistor.

[0029] Specifically, using the bias current operational amplifier can realize input high impedance isolation, and the current cannot flow in or out of the A terminal and the B terminal. That is, the current flows from the reference voltage source REF, through the voltage dividing resistor RS, r1, the resistance Rt to be measured, and r3, and flows into the negative electrode of the power supply.

[0030] Thus, we can get:

[0031] ,

[0032] Among them, I is the current, U REF is the output voltage of the reference voltage source REF, U A is the output voltage of the first voltage sampling terminal A, and RS is the resistance value of the voltage dividing resistor.

[0033] Since the B measurement branch has high impedance isolation, the current flowing through r2 is approximately 0, and we can get:

[0034] ,

[0035] Among them, V r1 is the voltage of the first wire, U B is the output voltage of the second voltage sampling terminal B.

[0036] From the three-wire process, the line impedance is equal, and we can get:

[0037] ,

[0038] Among them, V r3 is the voltage of the third wire.

[0039] According to the above formula, we can get:

[0040] ,

[0041] After sorting, we can get:

[0042] ,

[0043] Among them, R t is the resistance value of the resistance Rt to be measured.

[0044] In some embodiments, the resistance detection circuit suitable for the line parasitic resistance can further include a digital-to-analog converter and a processor, an output end of the first signal processing sub-circuit is electrically connected with one input end of the digital-to-analog converter, an output end of the second signal processing sub-circuit is electrically connected with another input end of the digital-to-analog converter, and an output end of the digital-to-analog converter is electrically connected with an input end of the processor. The processor can output the resistance value of the resistance to be measured Rt.

[0045] Finally, it should be understood that the embodiments described herein are only to illustrate the principles of the embodiments described herein. Other variations can also belong to the scope of the embodiments described herein. Therefore, as an example but not limitation, alternative configurations of the embodiments described herein can be considered to be consistent with the teachings of the embodiments described herein. Accordingly, the embodiments described herein are not limited to the embodiments explicitly introduced and described in the embodiments described herein.

Claims

1. A resistance detection circuit for line parasitic resistance, characterized by, The three-wire resistance measurement sub-circuit, the first signal processing sub-circuit and the second signal processing sub-circuit are electrically connected.

2. The resistance detection circuit for line parasitic resistance according to claim 1, wherein The three-wire resistance measurement sub-circuit comprises a first wire, a second wire, a third wire and a voltage dividing resistor. The first wire is electrically connected to one end of the voltage dividing resistor.

3. The resistance detection circuit adapted for line parasitic resistance according to claim 2, characterized in that, The other end of the voltage dividing resistor is electrically connected to a reference voltage source.

4. The resistance detection circuit adapted for line parasitic resistance according to claim 3, characterized in that, The other end of the first wire and one end of the second wire are electrically connected to one end of the resistance to be measured.

5. The resistance detection circuit adapted for line parasitic resistance according to claim 4, characterized in that, The other end of the second wire is electrically connected to the second signal processing sub-circuit as a second voltage sampling end.

6. The resistance detection circuit for line parasitic resistance according to claim 3, wherein The other end of the third wire is electrically connected to the other end of the resistance to be measured.

7. The resistance detection circuit adapted for line parasitic resistance according to claim 6, characterized in that, The connection node of the voltage dividing resistor and the first wire is electrically connected to the first signal processing sub-circuit as a first voltage sampling end. The first signal processing sub-circuit comprises a first amplifier and a first filter. The other end of the first voltage sampling end is electrically connected to the non-inverting terminal of the first voltage amplifier. The other end of the first resistance is electrically connected to the ground. The other end of the first reference resistance is electrically connected to the connection node of the first resistance and the non-inverting terminal of the first voltage amplifier. The first filter comprises a second resistance and a first capacitance. The other end of the second resistance is the output end of the first filter. The second signal processing sub-circuit comprises a second amplifier and a second filter. The second voltage sampling end is electrically connected to the non-inverting terminal of the second voltage amplifier. The other end of the third resistance is electrically connected to the ground. The other end of the second reference resistance is electrically connected to the connection node of the third resistance and the non-inverting terminal of the second voltage amplifier.

8. The resistance detection circuit adapted for line parasitic resistance according to claim 7, characterized in that, The second filter comprises a fourth resistor and a second capacitor, one end of the fourth resistor is electrically connected with the output end of the second voltage amplifier, the other end of the fourth resistor is the output end of the second filter, and one end of the second capacitor is electrically connected with the fourth resistor.

9. The resistance value detection circuit for line parasitic resistance according to claim 2, wherein The resistance value of the to-be-measured resistor is determined based on an output voltage of the first signal processing sub-circuit, an output voltage of the second signal processing sub-circuit, an output voltage of the reference voltage source and a resistance value of the voltage dividing resistor.

10. The resistance detection circuit adapted for line parasitic resistance according to any one of claims 6-9, characterized in that, The application further comprises a digital-to-analog converter and a processor, an output end of the first signal processing sub-circuit is electrically connected with one input end of the digital-to-analog converter, an output end of the second signal processing sub-circuit is electrically connected with the other input end of the digital-to-analog converter, and an output end of the digital-to-analog converter is electrically connected with an input end of the processor.

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