DPU hardware board card

Abstract

The utility model relates to a DPU (Data Processing Unit) hardware board card. The DPU hardware board card comprises an ASIC (Application Specific Integrated Circuit) chip, a storage module and a golden finger, the ASIC chip is connected with an external device in an inserted mode through a golden finger. The ASIC chip is electrically connected with the storage module; the storage module is used for storing information of the DPU hardware board card; and the external equipment is used for supplying power to the storage module through the golden finger in a software shutdown state and acquiring the information of the DPU hardware board card stored in the storage module. Through the technical scheme disclosed by the invention, good adaptability is achieved, and diversified requirements of customers can be met.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of communication technology, in particular to a DPU hardware board. BACKGROUND

[0002] Network latency is the core indicator of the ultra-fast trading system, and low latency is the common pursuit of the global financial industry. Latency means economic value, and the current financial industry's pursuit of latency has gone from milliseconds to microseconds.

[0003] In the related art, some ultra-low latency board cards developed by some manufacturers only support standard protocols and cannot be customized and developed according to customer requirements, which has the disadvantages of insufficient adaptability and compatibility, long procurement cycle, unstable supply, etc. CONTENT OF THE UTILITY MODEL

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a DPU hardware board card with good adaptability to meet the diverse needs of customers.

[0005] In a first aspect, the present disclosure provides a DPU hardware board card, comprising:

[0006] an ASIC chip, a storage module and a golden finger;

[0007] The ASIC chip is connected with an external device through the golden finger, and the ASIC chip and the storage module are electrically connected;

[0008] The storage module is used for storing information of the DPU hardware board card, and the external device supplies power to the storage module through the golden finger when in a software shutdown state and acquires the information of the DPU hardware board card stored in the storage module.

[0009] Optionally, the DPU hardware board card further comprises:

[0010] a control module connected with the ASIC chip;

[0011] The control module is used for initializing and configuring the ASIC chip and acquiring state information of the ASIC chip.

[0012] Optionally, the DPU hardware board card further comprises:

[0013] a network control module connected with the control module, and the control module is connected with a network controller of the external device through the network control module.

[0014] Optionally, the DPU hardware board card further comprises:

[0015] a firmware upgrade module, the firmware upgrade module being connected with the control module;

[0016] The firmware upgrade module is used for upgrading the control module and / or the ASIC chip.

[0017] Optionally, the DPU hardware board card further comprises:

[0018] a first voltage conversion module, the ASIC chip being connected with the golden finger through the first voltage conversion module;

[0019] The first voltage conversion module is used for converting the power supply voltage provided by the external device into the working voltage of the ASIC chip.

[0020] Optionally, the DPU hardware board card further comprises:

[0021] an optoelectronic conversion module, the optoelectronic conversion module being electrically connected with the ASIC chip; the optoelectronic conversion module is used for converting the electrical signal acquired from the ASIC chip into an optical signal for external transmission, and converting the acquired optical signal into an electrical signal for transmission to the ASIC chip.

[0022] Optionally, the DPU hardware board card further comprises:

[0023] an isolation module, the isolation module being connected with the ASIC chip through the golden finger;

[0024] The isolation module is used for isolating the connection between the ASIC chip and the external device before the ASIC chip is powered on.

[0025] Optionally, the DPU hardware board card further comprises:

[0026] a JTAG module, the JTAG module being electrically connected with the ASIC chip, the JTAG module being used for programming and debugging the ASIC chip;

[0027] a UART module, the UART module being connected with the ASIC chip;

[0028] The external device acquires debugging information from the ASIC chip through the UART module.

[0029] Optionally, the DPU hardware board card further comprises a first clock module and a second clock module, the first clock module and the second clock module both being connected with the ASIC chip;

[0030] The first clock module is used for providing a global reference clock to the ASIC chip, and the second clock module is used for providing a network differential clock to the ASIC chip.

[0031] Optionally, the ASIC chip comprises an ASIC K2S1-2200N chip.

[0032] The DPU hardware board provided by the present disclosure comprises an ASIC chip, a storage module and a golden finger; the ASIC chip is connected with an external device through the golden finger; the ASIC chip and the storage module are electrically connected; the storage module is used for storing information of the DPU hardware board; and the external device supplies power to the storage module through the golden finger when in a software shutdown state and acquires the information of the DPU hardware board stored in the storage module. Thus, the present disclosure sets the storage module in the DPU hardware board, so that the server can read the information of the DPU hardware board through the golden finger when in a software shutdown state, which facilitates subsequent external device configuration of related drivers, improves the adaptability of the DPU hardware board to external devices, avoids insufficient adaptability and compatibility and the problem of being unable to be customized and developed according to customer requirements. The DPU hardware board provided by the present disclosure has good adaptability and can meet the needs of customer diversity. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure, together with the description.

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, for those skilled in the art, other drawings can also be obtained based on these drawings without creative labor.

[0035] Figure 1 A structural schematic diagram of a DPU hardware board provided by the present disclosure is shown in the figure.

[0036] Figure 2 A structural schematic diagram of another DPU hardware board provided by the present disclosure is shown in the figure.

[0037] Figure 3 A connection relationship schematic diagram of a first voltage conversion module in a DPU hardware board provided by the present disclosure is shown in the figure.

[0038] Figure 4 A structural schematic diagram of another DPU hardware board provided by the present disclosure is shown in the figure. DETAILED DESCRIPTION

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, for those skilled in the art, other drawings can also be obtained based on these drawings without creative labor.

[0040] Many specific details are set forth in the following description in order to provide a thorough understanding of the present disclosure. However, the present disclosure can be practiced according to other embodiments that do not require some of the specific details described in this description. It is understood that the examples described in this specification are merely examples and are not intended to limit the present disclosure in any manner.

[0041] Figure 1 A structural schematic diagram of a DPU hardware board provided by an embodiment of the present disclosure is shown in the following figure, Figure 2 A structural schematic diagram of another DPU hardware board provided by an embodiment of the present disclosure is shown in the following figure. In combination with Figure 1 and Figure 2 The DPU hardware board includes an ASIC chip 1, a storage module 2 and a connecting finger 3; the ASIC chip 1 is connected with an external device through the connecting finger 3; the ASIC chip 1 and the storage module 2 are electrically connected; the storage module 2 is used for storing information of the DPU hardware board; the external device supplies power to the storage module 2 through the connecting finger 3 when in a software shutdown state, and obtains the information of the DPU hardware board stored in the storage module 2.

[0042] The DPU hardware board provided by the embodiment of the present disclosure is a hardware board dedicated to DPU. DPU (Data Processing Unit) is a new generation of processor for data-centric computing, which can integrate complete data center functions into a single chip. The performance of DPU has been greatly improved compared with the existing CPU. The data processing capability of DPU is stronger, so the embodiment of the present disclosure is improved based on the hardware board dedicated to DPU.

[0043] Specifically, the connecting finger is the connection between the computer hardware such as the memory bar and the memory slot, the graphics card and the graphics card slot, and all signals are transmitted through the connecting finger. The connecting finger is composed of many golden conductive contacts. Because its surface is plated with gold and the conductive contacts are arranged like fingers, it is called "connecting finger".

[0044] The ASIC (Application Specific Integrated Circuit) chip is an integrated circuit for a specific application. Several, dozens or even hundreds of general-purpose small-scale integrated circuits that perform some functions can be integrated on a chip to realize the needs of the system.

[0045] The related external device, such as a server, needs to set a related module of the DPU hardware board to enable the server to read the information of the DPU hardware board, such as address information, identity information and other key information, through the golden finger 3 in the S5 state, that is, the software shutdown state, and the server configures a related driver based on the obtained information of the DPU hardware board, and the related DPU hardware board does not have a corresponding module, and the adaptability to the external device, such as the server, is poor.

[0046] In combination Figure 1 And Figure 2 In order to improve the adaptability to the related external device, the storage module 2 is provided in the embodiment of the disclosure, the storage module 2 is electrically connected with the ASIC chip 1, and the ASIC chip 1 is plugged with the external device through the golden finger 3. Exemplarily, the interface of the golden finger 3 is PCIE (peripheral component interconnect express, high-speed serial computer expansion bus), and the DPU hardware board is inserted into the PCIE slot of the external device through the golden finger 3 to establish communication with the external device, such as a host or a server. The power supply provided by the external device, such as 12V or 3.3V, is supplied to the DPU hardware board through the golden finger 3.

[0047] When the external device is in the software shutdown state, that is, the S5 state, the golden finger 3 cannot provide 12V voltage to the DPU hardware board, and can provide 3.3V voltage to the DPU hardware board to power on the storage module 2, the external device powers on the storage module 2 through the golden finger 3, and reads the DPU hardware board information stored in the storage module 2 through the SMBUS (System Management Bus, system management bus) of the golden finger 3.

[0048] Exemplarily, the storage module 2 is, for example, an EEPROM (Electrically Erasable Programmable Read-Only Memory, electrically erasable programmable read-only memory) chip. The EEPROM chip adopts an FRU (Fault, Repair and Unavailable, fault, repair and unavailability) scheme, and each FRU scheme has a unique identifier for identifying the type and model of the device. This identifier is usually a unique serial number, which can be obtained by reading the EEPROM chip on the device. The information of the FRU scheme usually includes the model number, manufacturer, production date, serial number and other important information of the device. These information are recorded in the EEPROM chip of the device, so that when the device needs to be replaced, the appropriate FRU can be accurately identified and matched.

[0049] The length and offset of the FRU data vary with the content, which is combined by the six areas in Table 1. Except the Common Header, the other areas can be omitted.

[0050] Table 1

[0051]

[0052] The FRU management system can identify the device type and model by reading the EEPROM chip on the device. Once the device is identified, the system can determine the device status according to the FRU information of the device. If repair is needed, the repair steps and replacement parts can be confirmed. At the same time, when the FRU in the device is replaced, the FRU record of the device needs to be updated in time.

[0053] The DPU hardware board provided by the embodiment of the present disclosure is a half-height and half-length PCIE card, the gold finger interface is PCIE, PCIE3.0x8, without locking piece, and there are 8 pairs of differential signals, lan0-lan7. The size of the PCIE card conforms to the standard PCIE, and the PCIE card can be directly used in the PCIE slot of the host.

[0054] The embodiment of the present disclosure sets the storage module 2 in the DPU hardware board, so that the server can read the information of the DPU hardware board through the gold finger 3 in the S5 state, i.e. the software shutdown state, which facilitates the subsequent configuration of the related drivers of the external device, improves the adaptability of the DPU hardware board to the external device, realizes the compatible design of the DPU hardware board, has good adaptability, and can meet the diverse needs of customers.

[0055] Optionally, the DPU hardware board further comprises a control module 4, which is connected with the ASIC chip 1; the control module 4 is configured to initialize and configure the ASIC chip 1 and obtain the state information of the ASIC chip 1.

[0056] Specifically, the control module 4 is, for example, an MCU (Microcontroller Unit, microcontroller unit), Figure 2 The MCU is exemplarily shown in the middle of the figure, and the model of the MCU is MCUGD32F407VET6. The control module 4 can be connected with the CONFIG interface of the ASIC chip 1 through an SPI (Serial Peripheral Interface, serial peripheral interface) bus. After the DPU hardware board is powered on, the control module 4 initializes and sets the ASIC chip 1. During the use of the ASIC chip 1, the control module 4 obtains the state information of the ASIC chip 1 to monitor the voltage state, current state or temperature state of the ASIC chip 1.

[0057] Figure 2 The I2C Devices are connected to and controlled by the control module 4. The I2C Devices can include, for example, a power monitor for real-time monitoring of power consumption or real-time monitoring of voltage of the control module 4 and / or the ASIC chip 1, and a temperature sensor. After the power monitor and the temperature sensor obtain relevant information, the information is written into the storage module 2. The I2C Devices can also include other devices, which are set according to the use requirements of the DPU hardware board card, and the embodiments of the present disclosure do not limit this.

[0058] Optionally, in combination with Figure 1 and Figure 2 , the DPU hardware board card further includes a network control module 5, the network control module 5 being connected with the control module 4; the control module 4 being connected with a network controller of an external device through the network control module 5.

[0059] Specifically, the network control module 5 is, for example, an NCSI (Network Controller Side Information) interface, which is a network interface technology proposed by Intel and aims to improve the communication efficiency between a network adapter and a host operating system. The NCSI is usually implemented in a high-speed interface.

[0060] More and more existing external devices, such as hosts or servers, are provided with a management controller (MC) and a network controller (NC). The management controller and the network controller are connected, and the network controller can obtain chip information through PCIE or NCSI. However, some servers, such as remote servers, only have software drivers matching the NCSI, and cannot match the corresponding PCIE software drivers. If the DPU hardware board card does not have an NCSI interface, it cannot be adapted to this type of server. Therefore, the embodiments of the present disclosure set the NCSI interface as the network control module 5, the control module 4 is connected with the network controller of the external device through the network control module 5, and the control module 4 is connected with the network control module 5 externally, for managing and monitoring the network controller, so that the DPU hardware board card provided by the embodiments of the present disclosure can be adapted to more manufacturers and more types of servers.

[0061] Exemplarily, Figure 2The network control module 5 and the control module 4 can be connected through, for example, an RMII (Reduced Media Independent Interface), a UART (Universal Asynchronous Receiver Transmitter), or other signal lines, as shown in the figure.

[0062] Optionally, the DPU hardware board card further comprises a firmware upgrade module 6 connected with the control module 4; the firmware upgrade module 6 is used for upgrading the control module 4 and / or the ASIC chip 1.

[0063] Specifically, the DPU hardware board card further comprises a firmware upgrade module 6, for example, an ISP (In System Programing) upgrade module, which allows programming and firmware upgrade without taking the control module 4 and / or the ASIC chip 1 off the circuit board. The firmware upgrade module 6 can upgrade the control module 4 online, can upgrade the ASIC chip 1 online through the control module 4, or can upgrade the control module 4 and the ASIC chip 1, which is not limited in the embodiments of the present disclosure.

[0064] Figure 3 A first voltage conversion module provided in the embodiments of the present disclosure in the connection relationship in the DPU hardware board card is shown in the figure. Optionally, as shown in the figure, Figure 3 the DPU hardware board card further comprises a first voltage conversion module 7, the ASIC chip 1 is connected with the gold finger 3 through the first voltage conversion module 7; the storage module 2 is connected with the gold finger 3 through a second voltage conversion module; the first voltage conversion module 7 is used for converting the power supply voltage provided by an external device into the working voltage of the ASIC chip 1.

[0065] Table 2

[0066]

[0067] Table 2 is a voltage parameter table of an ASIC chip provided in the embodiments of the present disclosure. As can be known from Table 2, since the power supply voltage provided by an external device such as a host or a server is different from the working voltage of the ASIC chip 1, the DPU hardware board card provided in the embodiments of the present disclosure can further comprise a first voltage conversion module 7, which converts the power supply voltage provided by the external device into the working voltage of the ASIC chip 1.

[0068] Exemplarily, as shown in the figure, Figure 3As shown, the ASIC chip 1 is connected with the gold finger 3 through a first voltage conversion module 7, which may include, for example, a fuse unit, a voltage reduction unit and a voltage stabilizing unit. The gold finger 3 is electrically connected with the fuse unit, the voltage reduction unit and the voltage stabilizing unit. The voltage stabilizing unit supplies power to each component of the DPU hardware board card that needs power supply, such as each interface of the ASIC chip 1.

[0069] The fuse unit may include, for example, an Efuse or other types of fuses. The voltage reduction unit may include, for example, a Buck voltage reduction circuit and an LDO (Low Dropout Regulator) voltage stabilizing circuit. The Buck voltage reduction circuit and the LDO voltage stabilizing circuit can make the output voltage less than the input voltage. The specific circuit structure of the Buck voltage reduction circuit and the LDO voltage stabilizing circuit is well known to those skilled in the art, and will not be described here.

[0070] Referring to Figure 3 , the 12V voltage accessed by the gold finger 3 is converted into 0.9V@2.0A by the first Buck voltage reduction circuit after passing through the Efuse, and supplies power to SW_VDD. The model of the Buck voltage reduction circuit is BuckE55340. The 12V voltage accessed by the gold finger 3 is converted into 1.4V@6A by the second Buck voltage reduction circuit after passing through the Efuse, and is divided into two paths. The model of the Buck voltage reduction circuit is BuckSQ29066B. One path is converted into 0.95V 1.9A by the LDO voltage stabilizing circuit, and supplies power to Serdes. The model of the LDO voltage stabilizing circuit is LDOSGM2050. The other path is converted into 0.95V 1.9A by the LDO voltage stabilizing circuit, and supplies power to PCIE. The model of the LDO voltage stabilizing circuit is LDOSGM2050. The 12V voltage accessed by the gold finger 3 is converted into 1.8V@6A by the third Buck voltage reduction circuit after passing through the Efuse, and is divided into two paths. One path supplies power to SW_VDDIO and the peripheral circuit of the DPU hardware board card. The other path is supplied to Serdes and PCIE after passing through two-stage LC filtering. The model of the Buck voltage reduction circuit is BuckSQ29066B.

[0071] The DPU hardware board card further includes a second voltage conversion module 12, which includes a Buck voltage reduction circuit. The 12V voltage accessed by the gold finger 3 is converted into 3.3V@2.5A by the fourth Buck voltage reduction circuit after passing through the Efuse, and supplies power to the photoelectric conversion module 8 and the like.

[0072] The 12V voltage accessed by the gold finger 3 supplies power to the MCU and the MCU peripheral circuit and the storage module 2 and the like after passing through the PTC (Positive Temperature Coefficient) fuse.

[0073] Optionally, in combination with Figure 1 and Figure 2 , the DPU hardware board card further comprises: an optoelectronic conversion module 8, which is electrically connected with the ASIC chip 1; the optoelectronic conversion module 8 is used to convert the electrical signal obtained from the ASIC chip 1 into an optical signal for external transmission, and is used to convert the obtained optical signal into an electrical signal for transmission to the ASIC chip 1.

[0074] Specifically, in combination with Figure 1 and Figure 2 , the DPU hardware board card further comprises, for example, an optoelectronic conversion module 8, which is connected with the ASIC chip 1 through an SFP (Small Form Pluggable) interface; for example, the PCIE3.0x8 differential signal on the gold finger 3 is connected to the PCIE module of the ASIC chip 1, and is converted into 2 groups of 25G SFP28 signals by using a software program, and is connected to the seat of the SFP28 module through the SERDES interface of the ASIC chip 1; the optoelectronic conversion module 8 is inserted into the SFP28 seat to realize the communication between the DPU hardware board card and the external device. In addition, the control module 4 can also be connected with the optoelectronic conversion module 8 to realize the control of the optoelectronic conversion module 8.

[0075] Figure 4 Another structure schematic diagram of a DPU hardware board card provided by the embodiment of the present disclosure is shown. Optionally, in combination with Figure 1 , Figure 2 and Figure 4 , the DPU hardware board card further comprises: an isolation module 9, which is connected with the ASIC chip 1; the isolation module 9 is used to isolate the connection between the ASIC chip 1 and the external device before the ASIC chip 1 is powered on. The isolation module 9 is, for example, an isolation buffer TPT29617A.

[0076] Specifically, in combination with Figure 1 , Figure 2 and Figure 4 , before the ASIC chip 1 is powered on, in order to prevent the external device from pulling information to the ASIC chip 1 and causing the external device such as a server to crash, the embodiment of the present disclosure sets the isolation module 9, which can be connected with the ASIC chip 1 through the gold finger 3, to isolate the connection between the ASIC chip 1 and the external device before the external device provides a 12V power voltage to the ASIC chip 1, thereby preventing the external device from crashing.

[0077] Figure 4 The single-chip microcomputer is connected with the storage module 2 through an analog switch, as shown in the example in Figure 4The DPU hardware board further includes a soldered FRU EEPROM BL24C512A and a non-soldered FRU EEPROM BL24C512A, so as to reduce the difficulty of software development. The DPU hardware board further includes a temperature measurement chip CT7432A MMR and a nuclear power chip ES5340, which are electrically connected to the control module 4 through I2C. It can be understood that when the DPU hardware board does not include the control module 4, the isolation module 9, the storage module 2, the temperature measurement chip, and the nuclear power chip are electrically connected to the ASIC chip 1, and the specific connection mode is well known to those skilled in the art and will not be described here.

[0078] The DPU hardware board has two SFP28 interfaces, and the rate is configured through an external active differential clock 156.25M, which can reach 25G. The PCIE3.0 X8 differential signals on the golden finger 3 are connected to the corresponding special pins of the ASIC chip 1, which can be converted into 4 groups of 25G SFP28 network signals, and the 25G optical-electric conversion module 8 is inserted to communicate with external devices. The FP28 complies with the SFF-8431 protocol, which includes the signals Tx_Fault, Tx_Disable, RS0 / RS1, Mod_ABS, Rx_LOS, and SCL / SDA. These related control signals are connected to the I / O pin of the ASIC chip 1 and are controlled by the ASIC chip 1.

[0079] Figure 4 The DPU hardware board further includes a third voltage conversion module 13 and a fourth voltage conversion module 14, and the ASIC chip 1 is electrically connected to the SFP28 through the third voltage conversion module 13. The third voltage conversion module 13 is used to convert the voltage provided by the ASIC chip 1 into the working voltage of the SFP28. The fourth voltage conversion module 14 is electrically connected to the control module 4 and the ASIC chip 1 respectively, and the fourth voltage conversion module 14 is used to convert the voltage provided by the control module 4 into the working voltage of the ASIC chip 1.

[0080] Optionally, in combination with Figure 1 and Figure 2 , the DPU hardware board further includes: a JTAG module 10, which is electrically connected to the ASIC chip 1, and is used for programming and debugging the ASIC chip 1; a UART module 11, which is connected to the ASIC chip 1; and an external device obtains debugging information from the ASIC chip 1 through the UART module 11.

[0081] Specifically, the JTAG (Joint Test Action Group) module is, for example, a JTAG interface, which is a debugging interface of the ASIC chip 1, and is used for connecting the ASIC chip 1 to a JTAG socket and programming and debugging the ASIC chip 1.

[0082] A UART module is a universal serial data bus used for asynchronous communication. This bus enables bidirectional communication, allowing for full-duplex transmission and reception. External devices can obtain debugging information from the ASIC chip 1 through the UART module 11. For example, the ASIC chip 1 can be connected to an external computer via the UART module 11 to print the information output by the ASIC chip 1.

[0083] Optionally, the DPU hardware board also includes: a first clock module and a second clock module, both of which are connected to the ASIC chip; the first clock module is used to provide a global reference clock to the ASIC chip 1, and the second clock module is used to provide a network differential clock to the ASIC chip.

[0084] Specifically, the first clock module provides a 50MHz global reference clock (GCLK) to the ASIC chip, and the second clock module provides a 156.25MHz network differential clock to the ASIC chip. Additionally, it may include a passive crystal oscillator module to provide an 8MHz passive crystal oscillator to the control module. The clock modules utilize higher-performance crystal oscillators to reduce clock signal frequency offset and jitter, ensuring clock signal quality.

[0085] In addition, such as Figure 2 As shown, the DPU hardware board also includes a reserved 12V fan mount for redundant heat dissipation. The DPU hardware board also includes indicator lights (LEDs) connected to ASIC chip 1 to indicate the operating status of corresponding devices within the DPU hardware board. For example, the indicator lights include a power indicator; a lit power indicator means the power chip's output voltage is normal, while a dim indicator means the voltage is abnormal. Some important signals can also have their operating status indicated by the on / off state of the indicator lights; a lit indicator means the signal is normal (high level output), while a dim indicator means the signal is abnormal (low level output). The DPU hardware board also includes GPIO (General-purpose input / output) ports.

[0086] Optionally, ASIC chip 1 includes an ASIC K2S1-2200N chip.

[0087] Specifically, for the securities and private equity industry, network latency is a core indicator of ultra-fast trading systems. Low latency is a common pursuit in the global financial industry, representing an arms race-level competition. Latency translates into economic value, and the financial industry's pursuit of latency has now progressed from milliseconds to microseconds. Currently, low-latency networks are primarily dominated by foreign manufacturers, with virtually no domestic presence.

[0088] Ultra-low latency network card is customized and optimized for low latency scenarios, based on the DPU chip and HADOS software platform of the company's independent intellectual property KPU architecture, with the company's self-developed commercial chip-level data offload engine DOE, network offload engine NOE, using programmable architecture and other technologies, which can be used as a technical base for financial ultra-fast trading, artificial intelligence, industrial internet, video streaming and other fields.

[0089] Specific to the financial field, the ultra-low latency network card can provide a simple and easy-to-use low-latency hardware platform for customers such as securities companies and asset management institutions that pursue extreme latency. On the hardware side, NOE, Lightning DMA, and other IPs are packaged with standard AXIStream interfaces, making hardware secondary development integration more convenient; on the software side, users can develop heterogeneous acceleration services more conveniently based on the HADOS software development kit.

[0090] In the securities and financial industry, speed means value, and the core ultra-fast trading system has an endless pursuit of low-latency network performance, with high technical threshold and product development difficulty. In addition, security, reliability, and self-control have become an endogenous demand in the financial field, and low-latency network urgently needs a domestic solution to fill the gap in the domestic market.

[0091] The ultra-low latency network card in the related art is basically provided by foreign manufacturers. For the financial field, ultra-low latency is crucial.

[0092] To solve the above problems, the disclosed embodiment adopts an ultra-low latency DPU hardware board card including an ASIC K2S1-2200N chip, which is an ultra-low latency board card hardware design scheme developed based on the ASIC K2S1-2200N chip. The chip has the highest cost performance, and the software side code migration is easy. The DPU hardware board card has the advantages of being able to be customized and developed according to customer requirements, strong adaptability and compatibility, and completing product compatibility adaptation with domestic CPU core manufacturers such as Haiguang, Kunpeng, and Feipeng, as well as operating system core manufacturers such as Kirin, Euler, and United, and completing order delivery within 6-8 weeks.

[0093] The disclosed embodiment sets a storage module in the DPU hardware board card, so that the server can read the information of the DPU hardware board card through the golden finger in the software shutdown state, facilitating subsequent external device configuration of related drivers, improving the adaptability of the DPU hardware board card to external devices, and avoiding the problems of insufficient adaptability and compatibility and being unable to be customized and developed according to customer requirements. The DPU hardware board card provided by the present disclosure has good adaptability and can meet the diverse needs of customers.

[0094] It has to be noted that, in the present document, relational terms are intended to encompass the various possible relationships between alternatives, such as those individuals or entities that have been in contact with one another as well as those individuals or entities that merely have information regarding each other — a many-to-many relationship. The terms "first" and "second", etc. are used herein solely to distinguish one alternative entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0095] The foregoing is merely illustrative of the principles of this disclosure and various modifications can be made by those skilled in the art without departing from the spirit and scope of the disclosure. The disclosure is not intended to be limited to the embodiments described herein but is to be accorded the full scope of the claims, wherein reference to an element in the singular is not intended to mean "one and only one" unless specifically so stated, but instead means that there is at least one and there can be more than one.

Claims

1. A DPU hardware board, characterized in that, include: ASIC chips, memory modules, and gold fingers; The ASIC chip is connected to an external device via the gold fingers; the ASIC chip and the storage module are electrically connected. The storage module is used to store information about the DPU hardware board; when the external device is in a software-powered-off state, it supplies power to the storage module through the gold fingers and obtains the information about the DPU hardware board stored in the storage module.

2. The DPU hardware board according to claim 1, characterized in that, Also includes: A control module, which is connected to the ASIC chip; The control module is used to initialize and configure the ASIC chip and obtain the status information of the ASIC chip.

3. The DPU hardware board according to claim 2, characterized in that, Also includes: A network control module is connected to the control module; the control module is connected to the network controller of the external device through the network control module.

4. The DPU hardware board according to claim 2, characterized in that, Also includes: A firmware upgrade module, which is connected to the control module; The firmware upgrade module is used to upgrade the control module and / or the ASIC chip.

5. The DPU hardware board according to claim 1, characterized in that, Also includes: A first voltage conversion module is used, through which the ASIC chip is connected to the gold finger; The first voltage conversion module is used to convert the power supply voltage provided by the external device into the operating voltage of the ASIC chip.

6. The DPU hardware board according to claim 1, characterized in that, Also includes: A photoelectric conversion module, wherein the photoelectric conversion module is electrically connected to the ASIC chip; The photoelectric conversion module is used to convert electrical signals obtained from the ASIC chip into optical signals for external transmission, and to convert the obtained optical signals into electrical signals for transmission to the ASIC chip.

7. The DPU hardware board according to claim 1, characterized in that, Also includes: An isolation module, which is connected to the ASIC chip; The isolation module is used to isolate the connection between the ASIC chip and the external device before the ASIC chip is powered on.

8. The DPU hardware board according to claim 1, characterized in that, Also includes: A JTAG module, which is electrically connected to the ASIC chip, is used for programming and debugging the ASIC chip; A UART module, which is connected to the ASIC chip; External devices obtain debugging information from the ASIC chip through the UART module.

9. The DPU hardware board according to claim 1, characterized in that, Also includes: A first clock module and a second clock module, both of which are connected to the ASIC chip; The first clock module is used to provide a global reference clock to the ASIC chip, and the second clock module is used to provide a network differential clock to the ASIC chip.

10. The DPU hardware board according to claim 1, characterized in that, The ASIC chip includes the ASIC K2S1-2200N chip.

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