Small-size visual development board based on Quartus platform

Abstract

The utility model discloses a small-size visual development board based on a Quartus platform, which comprises an FPGA (Field Programmable Gate Array) main chip U6, a key control circuit, a memory circuit, a storage circuit, a clock circuit, a JTAG (Joint Test Action Group) interface circuit, a USB (Universal Serial Bus) to serial port circuit, an image acquisition circuit, an image output circuit, an expansion IO (Input / Output) circuit, an Ethernet interface circuit and a power supply circuit, the power supply circuit comprises a DC power supply circuit, a power supply switching circuit, a 12V-5V conversion circuit, a 5V-3.3 V conversion circuit, a 5V-2.5 V conversion circuit and a 5V-1.2 V conversion circuit, the input end of the 12V-5V conversion circuit is electrically connected with the output end of the DC power supply circuit and the output end of the power supply switching circuit, and the power supply switching circuit is electrically connected with the DC power supply circuit and the USB to serial port circuit. An image acquired by the image acquisition circuit is calculated through the FPGA main chip U6, and the image is output through the image output circuit, so that development of a visual system is realized, the size of a visual development board is reduced, the structure is simplified, the cost is reduced, and power consumption is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to core board technical field especially is based on quartus platform's small size visual development board. BACKGROUND

[0002] With the rapid development of embedded system and artificial intelligence technology, the application in the visual field is more and more extensive, especially in intelligent monitoring, automatic driving, robot vision and industrial automation etc. field, the traditional visual system is mostly dependent on CPU or GPU and carries out computation, however along with the increasing processing demand, the requirement of low power consumption, high parallelism, real time is gradually improved. FPGA (field programmable gate array) can realize high speed parallel operation on the hardware level, can be designed and developed through quartus platform, reduces the design threshold of FPGA development board, thus becomes the preferred platform of more and more visual processing application. However, at present, based on FPGA development board still has the problems such as big volume and high power consumption, so that beginners face higher technical threshold and cost threshold when developing in the visual field, thus it is necessary to improve. SUMMARY

[0003] In view of the defects in the prior art, the utility model aims at providing a small size visual development board based on quartus platform, which reduces the volume of the visual development board, reduces the power consumption and facilitates the development and design of beginners.

[0004] In order to achieve the above purpose, the utility model adopts the technical scheme of a small size visual development board based on quartus platform, which comprises an FPGA main chip U6, a key control circuit, a memory circuit, a storage circuit, a clock circuit, a JTAG interface circuit, a USB-to-serial port circuit, an image acquisition circuit, an image output circuit, an extension IO circuit, an Ethernet interface circuit and a power supply circuit,

[0005] The key control circuit, the memory circuit, the storage circuit, the clock circuit, the JTAG interface circuit, the USB-to-serial port circuit, the image acquisition circuit, the image output circuit, the extension IO circuit, the Ethernet interface circuit and the power supply circuit are electrically connected with the FPGA main chip U6,

[0006] The power supply circuit is electrically connected with the FPGA main chip U6, the key control circuit, the memory circuit, the storage circuit, the clock circuit, the JTAG interface circuit, the USB-to-serial port circuit, the image acquisition circuit, the image output circuit, the Ethernet interface circuit and the extension IO circuit.

[0007] The power supply circuit includes a DC power supply circuit, a power supply switching circuit, a 12V-5V conversion circuit, a 5V-3.3V conversion circuit, a 5V-2.5V conversion circuit and a 5V-1.2V conversion circuit, the input end of the 12V-5V conversion circuit is electrically connected with the output end of the DC power supply circuit and the power supply switching circuit respectively, the power supply switching circuit is electrically connected with the DC power supply circuit and the USB-to-serial circuit respectively, the input end of the 5V-3.3V conversion circuit, the 5V-2.5V conversion circuit and the 5V-1.2V conversion circuit is electrically connected with the output end of the 12V-5V conversion circuit respectively;

[0008] The power supply switching circuit includes a MOS tube Q1, a diode D1, a resistor R1 and a resistor R2, the source of the MOS tube Q1 is electrically connected with the 5V_IN power supply end, the drain of the MOS tube Q1 is electrically connected with the 5V_USB power supply end, the gate of the MOS tube Q1 is electrically connected with the first end of the resistor R2, the negative electrode of the diode D1 and the second end of the resistor R1 respectively, the first end of the resistor R1 is electrically connected with the 12V_IN power supply end, the positive electrode of the diode D1 and the second end of the resistor R2 are grounded respectively;

[0009] The DC power supply circuit includes a DC socket JACK1, a fuse F1, a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4, the P pin of the DC socket JACK1 is electrically connected with the 12V_IN power supply end and the first end of the fuse F1 respectively, the second end of the fuse F1 is electrically connected with the first end of the capacitor C1, the first end of the capacitor C2, the first end of the capacitor C3, the first end of the capacitor C4 and the input end of the 12V-5V conversion circuit respectively, the G2 pin, the G3 pin of the DC socket JACK1, the second end of the capacitor C1, the second end of the capacitor C2, the second end of the capacitor C3 and the second end of the capacitor C4 are grounded respectively.

[0010] In the further technical scheme, the 12V-5V conversion circuit includes a power conversion chip U1, a switch SW6, an inductor L1, a diode D3, a diode D2, a resistor R3, a resistor R4, a resistor R5, a capacitor C8, a capacitor C5, a capacitor C6, a capacitor C7,

[0011] The IN pin of the power conversion chip U1 is electrically connected with the first end of the resistor R3 and the output end of the DC power supply circuit respectively, the VCC pin of the power conversion chip U1 is electrically connected with the first end of the capacitor C8, the EN pin of the power conversion chip U1 is electrically connected with the second end of the resistor R3, the BST pin of the power conversion chip U1 is electrically connected with the first end of the capacitor C5, the SW pin of the power conversion chip U1 is electrically connected with the second end of the capacitor C5, the first end of the inductor L1 and the negative electrode of the diode D3 respectively, the FB pin of the power conversion chip U1 is electrically connected with the first end of the resistor R5 and the first end of the resistor R4 respectively, the second end of the inductor L1 is electrically connected with the second end of the resistor R4, the first end of the capacitor C6, the first end of the capacitor C7, the negative electrode of the diode D2, the sixth pin of the switch SW6, the third pin of the switch SW6 and the 5V_IN power supply end respectively, the fifth pin of the switch SW6 and the second pin of the switch SW6 are electrically connected with the 5V power supply end respectively, the second end of the capacitor C8, the positive electrode of the diode D3, the second end of the resistor R5, the second end of the capacitor C6, the second end of the capacitor C7, the positive electrode of the diode D2, the GND pin of the power conversion chip U1 and the E pin of the power conversion chip U1 are grounded respectively.

[0012] In a further technical solution, the 5V-3.3V conversion circuit comprises a power conversion chip U4, an inductor L3, a resistor R12, a resistor R11, a resistor R10, a resistor R9, a capacitor C13, a capacitor C12, a capacitor C14,

[0013] The VIN pin of the power conversion chip U4 is electrically connected with the EN pin of the power conversion chip U4, the first end of the capacitor C13 and the 5V power supply end respectively, the LX pin of the power conversion chip U4 is electrically connected with the first end of the inductor L3, the FB pin of the power conversion chip U4 is electrically connected with the first end of the resistor R11, the first end of the capacitor C12 and the first end of the resistor R12 respectively, the second end of the inductor L3 is electrically connected with the second end of the resistor R11, the second end of the capacitor C12, the first end of the capacitor C14 and the first end of the resistor R9 respectively, the second end of the resistor R9 is electrically connected with the first end of the resistor R10 and the 3V3 power supply end respectively, the second end of the resistor R10 is electrically connected with the positive electrode of the light emitting diode D4, the second end of the capacitor C13, the GND pin of the power conversion chip U4, the second end of the capacitor C14, the second end of the resistor R12 and the negative electrode of the light emitting diode D4 are grounded respectively.

[0014] In a further technical solution, the 5V-2.5V conversion circuit comprises a power conversion chip U5, an inductor L4, a resistor R14, a resistor R15, a resistor R13, a capacitor C16, a capacitor C15, a capacitor C17,

[0015] The VIN pin of the power conversion chip U5 is electrically connected with the EN pin of the power conversion chip U5, the first end of the capacitor C16 and the 5V power supply end respectively, the LX pin of the power conversion chip U5 is electrically connected with the first end of the inductor L4, the FB pin of the power conversion chip U5 is electrically connected with the first end of the resistor R14, the first end of the capacitor C15 and the first end of the resistor R15 respectively, the second end of the inductor L4 is electrically connected with the second end of the resistor R14, the second end of the capacitor C15, the first end of the capacitor C17 and the first end of the resistor R13 respectively, the second end of the resistor R13 is electrically connected with the 2.5V power supply end, and the second end of the capacitor C16, the GND pin of the power conversion chip U5, the second end of the resistor R15 and the second end of the capacitor C17 are grounded respectively.

[0016] In a further technical solution, the 5V-1.2V conversion circuit includes a power conversion chip U3, an inductor L2, a resistor R7, a resistor R8, a resistor R6, a capacitor C9, a capacitor C10, a capacitor C11,

[0017] The VIN pin of the power conversion chip U3 is electrically connected with the EN pin of the power conversion chip U3, the first end of the capacitor C9 and the 5V power supply end respectively, the LX pin of the power conversion chip U3 is electrically connected with the first end of the inductor L2, the FB pin of the power conversion chip U3 is electrically connected with the first end of the resistor R7, the first end of the capacitor C10 and the first end of the resistor R8 respectively, the second end of the inductor L2 is electrically connected with the second end of the resistor R7, the second end of the capacitor C10, the first end of the capacitor C11 and the first end of the resistor R6 respectively, the second end of the resistor R6 is electrically connected with the 1.2V power supply end, and the second end of the capacitor C9, the GND pin of the power conversion chip U3, the second end of the resistor R8 and the second end of the capacitor C11 are grounded respectively.

[0018] In a further technical solution, the USB-to-serial circuit includes a USB conversion chip U8, a TYPE-C socket J1, a crystal oscillator Y1, a crystal oscillator Y2, an inductor L5, a resistor R305, a resistor R306, a capacitor C27, a capacitor C34, a capacitor C35 and a capacitor C28,

[0019] The VCC pin of the USB conversion chip U8 is electrically connected with the 5V_USB power supply end and the first end of the capacitor C28 respectively, the TXD pin and the RXD pin of the USB conversion chip U8 are electrically connected with the FPGA main chip U6 respectively, the V3 pin of the USB conversion chip U8 is electrically connected with the first end of the capacitor C27, the GND pin of the USB conversion chip U8 and the second end of the capacitor C27 are grounded respectively, the UD+ pin of the USB conversion chip U8 is electrically connected with the DP1 pin and the DP2 pin of the TYPE-C socket J1 respectively, the UD- pin of the USB conversion chip U8 is electrically connected with the DN1 pin and the DN2 pin of the TYPE-C socket J1 respectively, the XI pin of the USB conversion chip U8 is electrically connected with the first end of the crystal oscillator Y1, the first end of the crystal oscillator Y2 and the first end of the capacitor C34 respectively, the XO pin of the USB conversion chip U8 is electrically connected with the second end of the crystal oscillator Y1, the second end of the crystal oscillator Y2 and the first end of the capacitor C35 respectively, the second end of the capacitor C34, the second end of the capacitor C35 and the second end of the capacitor C28 are grounded respectively, the resistor R305 is connected in series between the CC2 pin of the TYPE-C socket J1 and the ground end, the resistor R306 is connected in series between the CC1 pin of the TYPE-C socket J1 and the ground end, the first end of the inductor L5 and each GND pin of the TYPE-C socket J1 are grounded respectively, the second end of the inductor L5 is electrically connected with each SH pin of the TYPE-C socket J1 respectively, and each VBUS pin of the TYPE-C socket J1 is electrically connected with the 5V_USB power supply end.

[0020] In a further technical solution, the image acquisition circuit comprises a camera socket J11 and a plurality of voltage stabilizing resistors,

[0021] The VDD pin of the camera socket J11 is electrically connected with the output end of the 12V-5V conversion circuit, the SCL pin of the camera socket J11 is electrically connected with the I2C1_SCL pin of the FPGA main chip U6, the SDA pin of the camera socket J11 is electrically connected with the I2C1_SDA pin of the FPGA main chip U6, the GND pin of the camera socket J11 is grounded, and each voltage stabilizing resistor is connected in series between the camera socket J11 and the FPGA main chip U6.

[0022] In a further technical solution, the image output circuit comprises a VGA interface circuit, an HDMI interface circuit and an LCD interface circuit, and the VGA interface circuit, the HDMI interface circuit and the LCD interface circuit are electrically connected with the FPGA main chip U6 and the power supply circuit respectively.

[0023] In a further technical solution, the key control circuit comprises a reset key circuit and at least one user key circuit,

[0024] The reset button circuit comprises a button SW1, a capacitor C58, a resistor R47, a resistor R48 and a bidirectional diode Z1. The first end of the button SW1 is electrically connected with the second end of the resistor R48, the second end of the resistor R47, the second end of the bidirectional diode Z1 and the first end of the capacitor C58 respectively. The second end of the button SW1 is electrically connected with the second end of the capacitor C58 and the ground respectively. The first end of the resistor R48 is electrically connected with the output end of the 5V-3.3V conversion circuit. The first end of the resistor R47 is electrically connected with the RESET pin of the FPGA main chip U6. The first end of the bidirectional diode Z1 is grounded.

[0025] The user button circuit comprises a button SW2, a capacitor C60, a resistor R51, a resistor R52 and a bidirectional diode Z2. The first end of the button SW2 is electrically connected with the second end of the resistor R52, the second end of the resistor R51, the second end of the bidirectional diode Z2 and the first end of the capacitor C60 respectively. The second end of the button SW2 is electrically connected with the second end of the capacitor C60 and the ground respectively. The first end of the resistor R52 is electrically connected with the output end of the 5V-3.3V conversion circuit. The first end of the resistor R51 is electrically connected with the KEY1 pin of the FPGA main chip U6. The first end of the bidirectional diode Z2 is grounded.

[0026] In a further technical solution, the visual development board is further provided with an LED indication circuit. The LED indication circuit comprises a light-emitting diode D6, a light-emitting diode D7, a light-emitting diode D8, a light-emitting diode D9, a resistor R63, a resistor R161, a resistor R162 and a resistor R163.

[0027] The first end of the light-emitting diode D6, the first end of the light-emitting diode D7, the first end of the light-emitting diode D8 and the first end of the light-emitting diode D9 are electrically connected with the output end of the 5V-3.3V conversion circuit respectively. The resistor R63 is connected in series between the second end of the light-emitting diode D6 and the LED0 pin of the FPGA main chip U6. The resistor R161 is connected in series between the second end of the light-emitting diode D7 and the LED1 pin of the FPGA main chip U6. The resistor R162 is connected in series between the second end of the light-emitting diode D8 and the LED2 pin of the FPGA main chip U6. The resistor R163 is connected in series between the second end of the light-emitting diode D9 and the LED3 pin of the FPGA main chip U6.

[0028] Compared with the prior art, the utility model has the advantages that: the FPGA main chip U6 calculates the image collected by the image collection circuit, and outputs the image through the image output circuit, so that the development of the vision system is realized, the size of the vision development board is reduced, the structure is simplified, the cost is reduced, and the power consumption is reduced; the FPGA main chip U6 is provided with hardware acceleration and a high-level design tool, so that the Quartus platform is used for design and development, the development threshold is reduced, the development efficiency is improved, low power consumption and high compatibility are achieved; the 12V-5V conversion circuit, 5V-3.3V conversion circuit, 5V-2.5V conversion circuit and 5V-1.2V conversion circuit output 5V, 3.3V, 2.5V and 1.2V power supply respectively, so that the power supply of various voltage types of different components is met, the peripheral device support range is expanded, and the adaptability is improved; the power supply switching circuit switches the power supply of the DC power supply circuit and the USB-to-serial port circuit, cuts off the 5V power supply of the USB-to-serial port circuit when the DC power supply circuit has 12V power supply, and connects the 5V power supply of the USB-to-serial port circuit when the DC power supply circuit has no 12V power supply, so that the power input type of the power supply circuit is expanded, and the mobility is improved. BRIEF DESCRIPTION OF DRAWINGS

[0029] The utility model is further explained in connection with the drawings and examples.

[0030] Figure 1 It is the circuit block diagram of the utility model;

[0031] Figure 2 It is the circuit block diagram of the power supply circuit of the utility model;

[0032] Figure 3 It is the circuit diagram of the DC power supply circuit of the utility model;

[0033] Figure 4 It is the circuit diagram of the power supply switching circuit of the utility model;

[0034] Figure 5 It is the circuit diagram of the 12V-5V conversion circuit of the utility model;

[0035] Figure 6 It is the circuit diagram of the 5V-3.3V conversion circuit of the utility model;

[0036] Figure 7 It is the circuit diagram of the 5V-2.5V conversion circuit of the utility model;

[0037] Figure 8 It is the circuit diagram of the 5V-1.2V conversion circuit of the utility model;

[0038] Figure 9 It is the circuit diagram of the USB-to-serial port circuit of the utility model;

[0039] Figure 10 is a circuit diagram of the control button circuit of the utility model;

[0040] Figure 11 is a circuit diagram of the LED indication circuit of the utility model;

[0041] Figure 12 is a circuit diagram of the memory circuit of the utility model;

[0042] Figure 13 is a circuit diagram of the storage circuit of the utility model;

[0043] Figure 14 is a circuit diagram of the clock circuit of the utility model;

[0044] Figure 15 is a circuit diagram of the VGA interface circuit of the utility model;

[0045] Figure 16 is a circuit diagram of the LCD interface circuit of the utility model;

[0046] Figure 17 is a circuit diagram of the HDMI interface circuit of the utility model;

[0047] Figure 18 is a circuit diagram of the image acquisition circuit of the utility model;

[0048] Figure 19 is a circuit diagram of the extension IO circuit of the utility model;

[0049] Figure 20 is a circuit diagram of the Ethernet interface circuit of the utility model;

[0050] Figure 21 is one of the circuit diagrams of the FPGA main chip U6 of the utility model;

[0051] Figure 22 is the second of the circuit diagrams of the FPGA main chip U6 of the utility model;

[0052] Figure 23 is the third of the circuit diagrams of the FPGA main chip U6 of the utility model;

[0053] Figure 24 is a flow chart of the development process of the utility model;

[0054] Figure 25 is a flow chart during image processing of the utility model. DETAILED DESCRIPTION

[0055] The following is only the preferred embodiment of the utility model, and does not limit the protection scope of the utility model.

[0056] A small visual development board based on Quartus platform, as shown in Figures 1 to 25 Fig. 1, comprising an FPGA main chip U6, a key control circuit, a memory circuit, a storage circuit, a clock circuit, a JTAG interface circuit, a USB-to-serial circuit, an image acquisition circuit, an image output circuit, an expansion IO circuit, an Ethernet interface circuit and a power supply circuit, the key control circuit, the memory circuit, the storage circuit, the clock circuit, the JTAG interface circuit, the USB-to-serial circuit, the image acquisition circuit, the image output circuit, the expansion IO circuit, the Ethernet interface circuit and the power supply circuit are electrically connected with the FPGA main chip U6, the power supply circuit is electrically connected with the FPGA main chip U6, the key control circuit, the memory circuit, the storage circuit, the clock circuit, the JTAG interface circuit, the USB-to-serial circuit, the image acquisition circuit, the image output circuit, the Ethernet interface circuit and the expansion IO circuit; the power supply circuit comprises a DC power supply circuit, a power supply switching circuit, a 12V-5V conversion circuit, a 5V-3.3V conversion circuit, a 5V-2.5V conversion circuit and a 5V-1.2V conversion circuit, the input end of the 12V-5V conversion circuit is electrically connected with the output end of the DC power supply circuit and the power supply switching circuit, the power supply switching circuit is electrically connected with the DC power supply circuit and the USB-to-serial circuit, the input end of the 5V-3.3V conversion circuit, the 5V-2.5V conversion circuit and the 5V-1.2V conversion circuit is electrically connected with the output end of the 12V-5V conversion circuit; the power supply switching circuit comprises a MOS tube Q1, a diode D1, a resistor R1 and a resistor R2, the source of the MOS tube Q1 is electrically connected with a 5V_IN power supply end, the drain of the MOS tube Q1 is electrically connected with a 5V_USB power supply end, the gate of the MOS tube Q1 is electrically connected with the first end of the resistor R2, the negative electrode of the diode D1 and the second end of the resistor R1, the first end of the resistor R1 is electrically connected with a 12V_IN power supply end, the positive electrode of the diode D1 and the second end of the resistor R2 are grounded; the DC power supply circuit comprises a DC socket JACK1, a fuse F1, a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4, the P pin of the DC socket JACK1 is electrically connected with a 12V_IN power supply end and the first end of the fuse F1, the second end of the fuse F1 is electrically connected with the first end of the capacitor C1, the first end of the capacitor C2, the first end of the capacitor C3, the first end of the capacitor C4 and the input end of the 12V-5V conversion circuit, the G2 pin, the G3 pin of the DC socket JACK1, the second end of the capacitor C1, the second end of the capacitor C2, the second end of the capacitor C3 and the second end of the capacitor C4 are grounded.

[0057] The traditional FPGA development board is provided with rich expandability, more interfaces, and large size, which causes interface waste and high power consumption when used for development in the visual field, and is not suitable for development in the visual field, and the utility model discloses a FPGA main chip U6 is calculated to the image that image acquisition circuit gathers, and the image is output through the image output circuit, to realize the development of visual system, reduce the size of visual development board, simplify the structure, reduce the cost, reduce the power consumption generation, through the hardware acceleration of FPGA main chip U6 and high-level design tool, it is convenient to design and develop through Quartus platform, reduce the development threshold, improve the development efficiency, have low power consumption and high compatibility, 5V, 3.3V, 2.5V and 1.2V power supply are output respectively through 12V-5V conversion circuit, 5V-3.3V conversion circuit, 5V-2.5V conversion circuit and 5V-1.2V conversion circuit, to meet the power supply of various voltage types of different components, expand the peripheral support range, improve the adaptability, the power of DC power supply circuit and USB-serial conversion circuit is switched through the power switching circuit, when DC power supply circuit has 12V power supply, diode D1 is clamped at 5V, MOS tube Q1 is off, thereby cutting off the 5V power supply of USB-serial conversion circuit, and using DC power supply circuit for power supply, when DC power supply circuit has no 12V power supply, MOS tube Q1 is turned on, and the 5V power supply of USB-serial conversion circuit is connected, prevents the current, protects the USB interface of computer, and can expand the power input type of power supply circuit, improves mobility.

[0058] The expansion IO circuit is powered through 12V-5V conversion circuit and 5V-3.3V conversion circuit, which is convenient for connecting modules and sensors with different power requirements, and the general IO pin voltage is uniformly configured as 3.3V, and developers can freely expand functions according to requirements, and the expansion IO output pin is connected to B1, B2 and B7 of the FPGA main chip U6. By connecting other modules and sensors through the expansion IO circuit, diversified functions can be realized, and common image sensor interfaces (LVDS interface, MIPI interface), temperature and humidity sensors, I2C protocol interface devices, SPI protocol interface devices and the like are supported, and the general IO supports programmability.

[0059] The FPGA acceleration module built-in FPGA main chip U6 can accelerate common computer vision algorithms such as edge detection, target detection, filtering and image segmentation to hardware through Open CL or HLS (high-level language synthesis) tools, describe image processing algorithms with high-level language, and realize hardware acceleration by using FPGA. By utilizing the parallel computing capability of FPGA, the visual development board can efficiently process real-time video stream data and realize image processing task acceleration. Especially in target detection, image segmentation and edge detection, hardware acceleration can greatly improve the processing speed and meet the real-time requirements.

[0060] Specifically, as shown in Figure 5 the 12V-5V conversion circuit includes a power conversion chip U1, a switch SW6, an inductor L1, a diode D3, a diode D2, a resistor R3, a resistor R4, a resistor R5, a capacitor C8, a capacitor C5, a capacitor C6, a capacitor C7, the IN pin of the power conversion chip U1 is electrically connected with the first end of the resistor R3 and the output end of the DC power supply circuit respectively, the VCC pin of the power conversion chip U1 is electrically connected with the first end of the capacitor C8, the EN pin of the power conversion chip U1 is electrically connected with the second end of the resistor R3, the BST pin of the power conversion chip U1 is electrically connected with the first end of the capacitor C5, the SW pin of the power conversion chip U1 is electrically connected with the second end of the capacitor C5, the first end of the inductor L1 and the negative electrode of the diode D3 respectively, the FB pin of the power conversion chip U1 is electrically connected with the first end of the resistor R5 and the first end of the resistor R4 respectively, the second end of the inductor L1 is electrically connected with the second end of the resistor R4, the first end of the capacitor C6, the first end of the capacitor C7, the negative electrode of the diode D2, the sixth pin of the switch SW6, the third pin of the switch SW6 and the 5V IN power supply end respectively, the fifth pin of the switch SW6 and the second pin of the switch SW6 are electrically connected with the 5V power supply end respectively, the second end of the capacitor C8, the positive electrode of the diode D3, the second end of the resistor R5, the second end of the capacitor C6, the second end of the capacitor C7, the positive electrode of the diode D2, the GND pin of the power conversion chip U1 and the E pin of the power conversion chip U1 are grounded respectively.

[0061] When the DC power supply circuit is connected to a 12V power supply, the DC-DC voltage reduction is performed by the power conversion chip U1. The model of the power conversion chip U1 is MP2482. Since the power conversion chip U1 has a 5mΩ MOSFET tube integrated inside, the output current of the diode D3 as a freewheeling diode is large, the higher switching frequency makes the inductance value of the energy storage inductor smaller, the saturation current is larger, the volume is smaller, and the overall circuit occupies a smaller area on the board. The capacitor C3 and the capacitor C4 of the DC power supply circuit are used as input capacitors for filtering, and also as high-frequency backflow paths. The resistor R3 provides a voltage for the EN pin of the power conversion chip U1 to enter the working state, and the capacitor C5 is used as a bootstrap capacitor for the upper tube of the DC power supply circuit, providing a working current for the opening of the upper tube, so that it can be reliably opened. The inductor L1 is used as an energy storage filter inductor. When the switch tube is closed, part of the energy is stored in the inductor L1, and part of the energy is supplied to the output. When the MOSFET tube of the power conversion chip U1 is disconnected, the inductor L1 releases energy through the capacitor C6 and the diode D3 to provide current output. The resistors R4 and R5 are used as feedback resistors for the output voltage, and together with the internal reference voltage 0.81V, they are sent to the internal error amplifier for difference amplification, and then the signal is used to control the duty cycle of the PWM output signal, so as to realize the control of the output voltage. The capacitor C6 is used as an output capacitor to store energy for the inductor L1 output, smooth the output voltage, and multiple capacitors in parallel can reduce the equivalent resistance ESR, reduce the influence of ESR, and improve the response speed of the capacitor.

[0062] Specifically, as shown in Figure 6 The 5V-3.3V conversion circuit includes a power conversion chip U4, an inductor L3, a resistor R12, a resistor R11, a resistor R10, a resistor R9, a capacitor C13, a capacitor C12, and a capacitor C14. The VIN pin of the power conversion chip U4 is electrically connected to the EN pin of the power conversion chip U4, the first end of the capacitor C13, and the 5V power supply end, respectively. The LX pin of the power conversion chip U4 is electrically connected to the first end of the inductor L3. The FB pin of the power conversion chip U4 is electrically connected to the first end of the resistor R11, the first end of the capacitor C12, and the first end of the resistor R12, respectively. The second end of the inductor L3 is electrically connected to the second end of the resistor R11, the second end of the capacitor C12, the first end of the capacitor C14, and the first end of the resistor R9, respectively. The second end of the resistor R9 is electrically connected to the first end of the resistor R10 and the 3V3 power supply end. The second end of the resistor R10 is electrically connected to the positive electrode of the light-emitting diode D4. The second end of the capacitor C13, the GND pin of the power conversion chip U4, the second end of the capacitor C14, the second end of the resistor R12, and the negative electrode of the light-emitting diode D4 are grounded.

[0063] 12V-5V conversion circuit output 5V power supply through power conversion chip U4 step-down output 3.3V power supply, power conversion chip U4 model is RT8096C, capacitor C13 as input capacitor, inductor L3 as energy storage inductor, capacitor C14 as output capacitor, through resistor R11 and resistor R12 voltage division and power conversion chip U4 internal reference voltage 0.6V comparison output control signal, and then use the signal to control the duty cycle of PWM output signal, realize the control of output voltage. Capacitor C12 is the key feedforward capacitor, which can optimize the loop bandwidth and improve the loop response performance. Light emitting diode D4 is a power indicator, etc. When the power conversion chip U4 outputs 3.3V power supply, light emitting diode D4 is lit to prompt the user visual development board power-on successfully.

[0064] Specifically, as shown in Figure 7 5V-2.5V conversion circuit includes power conversion chip U5, inductor L4, resistor R14, resistor R15, resistor R13, capacitor C16, capacitor C15, capacitor C17, the VIN pin of power conversion chip U5 is electrically connected with the EN pin of power conversion chip U5, the first end of capacitor C16 and 5V power supply end respectively, the LX pin of power conversion chip U5 is electrically connected with the first end of inductor L4, the FB pin of power conversion chip U5 is electrically connected with the first end of resistor R14, the first end of capacitor C15 and the first end of resistor R15 respectively, the second end of inductor L4 is electrically connected with the second end of resistor R14, the second end of capacitor C15, the first end of capacitor C17 and the first end of resistor R13 respectively, the second end of resistor R13 is electrically connected with 2.5V power supply end, the second end of capacitor C16, the GND pin of power conversion chip U5, the second end of resistor R15 and the second end of capacitor C17 are grounded respectively.

[0065] 12V-5V conversion circuit output 5V power supply through power conversion chip U5 step-down output 2.5V power supply, power conversion chip U5 model is RT8096C, capacitor C16 as input capacitor, inductor L4 as energy storage inductor, capacitor C17 as output capacitor, through resistor R14 and resistor R15 voltage division and chip internal reference voltage 0.6V comparison output control signal, and then use the signal to control the duty cycle of PWM output signal, realize the control of output voltage. Capacitor C15 as feedforward capacitor.

[0066] Specifically, as shown in Figure 8As shown, the 5V-1.2V conversion circuit includes a power conversion chip U3, an inductor L2, a resistor R7, a resistor R8, a resistor R6, a capacitor C9, a capacitor C10, and a capacitor C11. The VIN pin of the power conversion chip U3 is electrically connected to the EN pin of the power conversion chip U3, the first end of the capacitor C9, and a 5V power supply, respectively. The LX pin of the power conversion chip U3 is electrically connected to the first end of the inductor L2. The FB pin of the power conversion chip U3 is electrically connected to the first end of the resistor R7, the first end of the capacitor C10, and the first end of the resistor R8, respectively. The second end of the inductor L2 is electrically connected to the second end of the resistor R7, the second end of the capacitor C10, the first end of the capacitor C11, and the first end of the resistor R6, respectively. The second end of the resistor R6 is electrically connected to a 1.2V power supply. The second end of the capacitor C9, the GND pin of the power conversion chip U3, the second end of the resistor R8, and the second end of the capacitor C11 are grounded, respectively.

[0067] The 5V power supply output by the 12V-5V conversion circuit is reduced by the power conversion chip U3 for the second time, and a 1.2V power supply is output. The model of the power conversion chip U3 is RT8096C. The internal upper and lower MOS tube resistances of the power conversion chip U3 are as low as 160mΩHS / 110mΩLS. The output current is as high as 1A, and the peak efficiency can be as high as 95%. The switching frequency of up to 1.5MHz can greatly reduce the required inductance to 2.2uH. The capacitor C9 is an input capacitor, the inductor L2 is an energy storage inductor, and the capacitor C11 is an output capacitor. The resistor R7 and the resistor R8 are used for voltage division and comparison with the internal reference voltage 0.6V of the power conversion chip U3 to output a control signal, which is then used to control the duty cycle of the PWM output signal to achieve output voltage control. The capacitor C10 is a key feedforward capacitor that can optimize the loop bandwidth and improve the loop response performance.

[0068] The FPGA main chip U6 is powered by the 5V-3.3V conversion circuit, the 5V-2.5V conversion circuit, and the 5V-1.2V conversion circuit. The JTAG interface circuit is powered by the 5V-3.3V conversion circuit. The storage circuit is powered by the 5V-3.3V conversion circuit. The memory circuit is powered by the 5V-3.3V conversion circuit. The clock circuit is powered by the 5V-3.3V conversion circuit.

[0069] Specifically, as Figure 9As shown, the USB-to-serial circuit includes a USB conversion chip U8, a TYPE-C socket J1, a crystal oscillator Y1, a crystal oscillator Y2, an inductor L5, a resistor R305, a resistor R306, a capacitor C27, a capacitor C34, a capacitor C35, and a capacitor C28, the VCC pin of the USB conversion chip U8 is electrically connected to the 5V_USB power supply end and the first end of the capacitor C28, the TXD pin and the RXD pin of the USB conversion chip U8 are electrically connected to the FPGA main chip U6, the V3 pin of the USB conversion chip U8 is electrically connected to the first end of the capacitor C27, the GND pin of the USB conversion chip U8 and the second end of the capacitor C27 are grounded, the UD+ pin of the USB conversion chip U8 is electrically connected to the DP1 and DP2 pins of the TYPE-C socket J1, the UD- pin of the USB conversion chip U8 is electrically connected to the DN1 and DN2 pins of the TYPE-C socket J1, the XI pin of the USB conversion chip U8 is electrically connected to the first end of the crystal oscillator Y1, the first end of the crystal oscillator Y2, and the first end of the capacitor C34, the XO pin of the USB conversion chip U8 is electrically connected to the second end of the crystal oscillator Y1, the second end of the crystal oscillator Y2, and the first end of the capacitor C35, the second end of the capacitor C34, the second end of the capacitor C35, and the second end of the capacitor C28 are grounded, the resistor R305 is connected in series between the CC2 pin of the TYPE-C socket J1 and the ground end, the resistor R306 is connected in series between the CC1 pin of the TYPE-C socket J1 and the ground end, the first end of the inductor L5 and each GND pin of the TYPE-C socket J1 are grounded, the second end of the inductor L5 is electrically connected to each SH pin of the TYPE-C socket J1, and each VBUS pin of the TYPE-C socket J1 is electrically connected to the 5V_USB power supply end.

[0070] The TYPE-C socket J1 is connected to external equipment, which can be connected to a power supply for power supply or connected to an external device for communication, the CC1 and CC2 pins are used to detect the type of connected equipment, and the corresponding VBUS voltage is configured according to different equipment. The inductor L5 is a 330Ω resistor, which cooperates with a 100MHz crystal oscillator Y1 to provide a clock signal for the circuit. The capacitor C34 and the capacitor C35 are used for filtering and stabilizing the clock signal, the USB conversion chip U8 is a CH340G, which converts the USB signal into a TTL level UART signal, simplifies the USB-to-UART conversion process, reduces the complexity of circuit design, and ensures the communication between the USB device and the FPGA main chip U6. The resistors R305 and R306 are 5.1kΩ resistors used for current limiting and protection circuit, and the capacitors C27 and C28 are 0.1μF capacitors used for decoupling and filtering. The TYPE-C interface is connected to the external equipment, which not only can be powered, but also can be used for high-speed data transmission, which is convenient for serial port debugging, compatible with multiple devices, and improves the expansibility.

[0071] Specifically, as shown in Figure 18 the image acquisition circuit includes a camera socket J11 and a plurality of voltage stabilizing resistors, the VDD pin of the camera socket J11 is electrically connected with the output end of the 12V-5V conversion circuit, the SCL pin of the camera socket J11 is electrically connected with the I2C1_SCL pin of the FPGA main chip U6, the SDA pin of the camera socket J11 is electrically connected with the I2C1_SDA pin of the FPGA main chip U6, the GND pin of the camera socket J11 is grounded, and each voltage stabilizing resistor is connected in series between the camera socket J11 and the FPGA main chip U6. The camera module is connected through the camera socket J11, the 5V power supply is input through the VDD pin of the camera socket J11 to supply power, the CAM_PDN, CAM_RST, CAM_XCLK, CAM_PCLK, CAM_VS and CAM_HS signals of the FPGA main chip U6 are connected to the pins of the camera socket J11 through the resistors R293, R294, R295 and R296 respectively, these signals are mainly used to control the working state of the camera module, including reset (CAM_RST), clock signals (CAM_XCLK, CAM_PCLK), synchronization signals (CAM_VS, CAM_HS), and the data signals CAM_D0 to CAM_D7 are connected to the D4 to D11 pins of J11 through the resistors R297 to R304, these data signals are used to transmit image data; the FPGA main chip U6 communicates with the camera module through the I2C_SDA and I2C_SCL signals to configure the camera parameters; each resistor is used for signal current limiting or impedance matching to ensure stable signal transmission; the power supply, control signal, data signal and communication signal are used to realize the normal working and data transmission of the camera module, and the camera module transmits the collected image to the FPGA main chip U6 for image acquisition.

[0072] Specifically, as shown in Figures 15 to 17 the image output circuit includes a VGA interface circuit, an HDMI interface circuit and an LCD interface circuit, and the VGA interface circuit, the HDMI interface circuit and the LCD interface circuit are electrically connected with the FPGA main chip U6 and the power supply circuit. The display connected through the VGA interface circuit transmits the RGB565 image format, the display connected through the HDMI interface circuit transmits the HDMI interface circuit, and the LCD screen connected through the LCD interface circuit transmits the LCD interface circuit, so as to enrich the connection richness of image display output and facilitate the connection with different interface types of display screen. The VGA interface circuit is powered through the 5V-3.3V conversion circuit, and the HDMI interface circuit and the LCD interface circuit are powered through the 12V-5V conversion circuit and the 5V-3.3V conversion circuit.

[0073] Specifically, asFigure 10 As shown, the key control circuit includes a reset key circuit and at least one user key circuit, the reset key circuit includes a key SW1, a capacitor C58, a resistor R47, a resistor R48 and a bidirectional diode Z1, the first end of the key SW1 is electrically connected with the second end of the resistor R48, the second end of the resistor R47, the second end of the bidirectional diode Z1 and the first end of the capacitor C58 respectively, the second end of the key SW1 is electrically connected with the second end of the capacitor C58 and the ground terminal respectively, the first end of the resistor R48 is electrically connected with the output terminal of the 5V-3.3V conversion circuit, the first end of the resistor R47 is electrically connected with the RESET pin of the FPGA main chip U6, and the first end of the bidirectional diode Z1 is grounded; the user key circuit includes a key SW2, a capacitor C60, a resistor R51, a resistor R52 and a bidirectional diode Z2, the first end of the key SW2 is electrically connected with the second end of the resistor R52, the second end of the resistor R51, the second end of the bidirectional diode Z2 and the first end of the capacitor C60 respectively, the second end of the key SW2 is electrically connected with the second end of the capacitor C60 and the ground terminal respectively, the first end of the resistor R52 is electrically connected with the output terminal of the 5V-3.3V conversion circuit, the first end of the resistor R51 is electrically connected with the KEY1 pin of the FPGA main chip U6, and the first end of the bidirectional diode Z2 is grounded. Through the reset key circuit, the visual development board is reset after the key SW1 is pressed, the key control circuit is provided with four user key circuits, and the functions of the corresponding user key circuits are defined to realize different control functions by pressing the keys and improve the degree of customization.

[0074] Specifically, as shown in the figure, Figure 11 The visual development board is also provided with an LED indication circuit, the LED indication circuit includes a light-emitting diode D6, a light-emitting diode D7, a light-emitting diode D8, a light-emitting diode D9, a resistor R63, a resistor R161, a resistor R162 and a resistor R163, the first end of the light-emitting diode D6, the first end of the light-emitting diode D7, the first end of the light-emitting diode D8 and the first end of the light-emitting diode D9 are electrically connected with the output terminal of the 5V-3.3V conversion circuit respectively, the resistor R63 is connected in series between the second end of the light-emitting diode D6 and the LED0 pin of the FPGA main chip U6, the resistor R161 is connected in series between the second end of the light-emitting diode D7 and the LED1 pin of the FPGA main chip U6, the resistor R162 is connected in series between the second end of the light-emitting diode D8 and the LED2 pin of the FPGA main chip U6, and the resistor R163 is connected in series between the second end of the light-emitting diode D9 and the LED3 pin of the FPGA main chip U6. By lighting or extinguishing the light-emitting diodes D6, D7, D8 and D9, the status indicator lamp of the program is used to display the status, so that the user can understand the running condition of the visual development board.

[0075] The above merely describes preferred embodiments of the present application, and for those skilled in the art, according to the idea of the present application, changes can be made in the specific implementation manner and application range, and the content of the specification should not be understood as a limitation of the present application.

Claims

1. A small size visual development board based on Quartus platform, characterized in that: The FPGA main chip U6, the key control circuit, the memory circuit, the storage circuit, the clock circuit, the JTAG interface circuit, the USB-to-serial circuit, the image acquisition circuit, the image output circuit, the expansion IO circuit, the Ethernet interface circuit and the power supply circuit are electrically connected with each other, The key control circuit, the memory circuit, the storage circuit, the clock circuit, the JTAG interface circuit, the USB-to-serial circuit, the image acquisition circuit, the image output circuit, the expansion IO circuit, the Ethernet interface circuit and the power supply circuit are electrically connected with the FPGA main chip U6, The power supply circuit is electrically connected with the FPGA main chip U6, the key control circuit, the memory circuit, the storage circuit, the clock circuit, the JTAG interface circuit, the USB-to-serial circuit, the image acquisition circuit, the image output circuit, the Ethernet interface circuit and the expansion IO circuit; The power supply circuit includes a DC power supply circuit, a power supply switching circuit, a 12V-5V conversion circuit, a 5V-3.3V conversion circuit, a 5V-2.5V conversion circuit and a 5V-1.2V conversion circuit, the input end of the 12V-5V conversion circuit is electrically connected with the output end of the DC power supply circuit and the power supply switching circuit, the power supply switching circuit is electrically connected with the DC power supply circuit and the USB-to-serial circuit, the input end of the 5V-3.3V conversion circuit, the 5V-2.5V conversion circuit and the 5V-1.2V conversion circuit is electrically connected with the output end of the 12V-5V conversion circuit; The power supply switching circuit includes a MOS tube Q1, a diode D1, a resistor R1 and a resistor R2, the source of the MOS tube Q1 is electrically connected with the 5V_IN power supply end, the drain of the MOS tube Q1 is electrically connected with the 5V_USB power supply end, the gate of the MOS tube Q1 is electrically connected with the first end of the resistor R2, the negative electrode of the diode D1 and the second end of the resistor R1, the first end of the resistor R1 is electrically connected with the 12V_IN power supply end, the positive electrode of the diode D1 and the second end of the resistor R2 are grounded; The DC power supply circuit includes a DC socket JACK1, a fuse F1, a capacitor C1, a capacitor C2, a capacitor C3 and a capacitor C4, the P pin of the DC socket JACK1 is electrically connected with the 12V_IN power supply end and the first end of the fuse F1, the second end of the fuse F1 is electrically connected with the first end of the capacitor C1, the first end of the capacitor C2, the first end of the capacitor C3, the first end of the capacitor C4 and the input end of the 12V-5V conversion circuit, the G2 pin, the G3 pin, the second end of the capacitor C1, the second end of the capacitor C2, the second end of the capacitor C3 and the second end of the capacitor C4 of the DC socket JACK1 are grounded.

2. The small volume visual development board based on Quartus platform according to claim 1, characterized in that: The 12V-5V conversion circuit includes a power conversion chip U1, a switch SW6, an inductor L1, a diode D3, a diode D2, a resistor R3, a resistor R4, a resistor R5, a capacitor C8, a capacitor C5, a capacitor C6 and a capacitor C7, The IN pin of the power conversion chip U1 is electrically connected with the first end of the resistor R3 and the output end of the DC power supply circuit respectively, the VCC pin of the power conversion chip U1 is electrically connected with the first end of the capacitor C8, the EN pin of the power conversion chip U1 is electrically connected with the second end of the resistor R3, the BST pin of the power conversion chip U1 is electrically connected with the first end of the capacitor C5, the SW pin of the power conversion chip U1 is electrically connected with the second end of the capacitor C5, the first end of the inductor L1 and the negative electrode of the diode D3 respectively, the FB pin of the power conversion chip U1 is electrically connected with the first end of the resistor R5 and the first end of the resistor R4 respectively, the second end of the inductor L1 is electrically connected with the second end of the resistor R4, the first end of the capacitor C6, the first end of the capacitor C7, the negative electrode of the diode D2, the sixth pin of the switch SW6, the third pin of the switch SW6 and the 5V_IN power supply end respectively, the fifth pin of the switch SW6 and the second pin of the switch SW6 are electrically connected with the 5V power supply end respectively, the second end of the capacitor C8, the positive electrode of the diode D3, the second end of the resistor R5, the second end of the capacitor C6, the second end of the capacitor C7, the positive electrode of the diode D2, the GND pin of the power conversion chip U1 and the E pin of the power conversion chip U1 are grounded respectively. 3.The small-size visual development board based on Quartus platform according to claim 2, characterized in that: The 5V-3.3V conversion circuit comprises a power conversion chip U4, an inductor L3, a resistor R12, a resistor R11, a resistor R10, a resistor R9, a capacitor C13, a capacitor C12, a capacitor C14, The VIN pin of the power conversion chip U4 is electrically connected with the EN pin of the power conversion chip U4, the first end of the capacitor C13 and the 5V power supply end respectively, the LX pin of the power conversion chip U4 is electrically connected with the first end of the inductor L3, the FB pin of the power conversion chip U4 is electrically connected with the first end of the resistor R11, the first end of the capacitor C12 and the first end of the resistor R12 respectively, the second end of the inductor L3 is electrically connected with the second end of the resistor R11, the second end of the capacitor C12, the first end of the capacitor C14 and the first end of the resistor R9 respectively, the second end of the resistor R9 is electrically connected with the first end of the resistor R10 and the 3V3 power supply end respectively, the second end of the resistor R10 is electrically connected with the positive electrode of the light emitting diode D4, the second end of the capacitor C13, the GND pin of the power conversion chip U4, the second end of the capacitor C14, the second end of the resistor R12 and the negative electrode of the light emitting diode D4 are grounded respectively.

4. The small volume visual development board based on Quartus platform according to claim 2, characterized in that: The 5V-2.5V conversion circuit comprises a power conversion chip U5, an inductor L4, a resistor R14, a resistor R15, a resistor R13, a capacitor C16, a capacitor C15, a capacitor C17, The VIN pin of the power conversion chip U5 is electrically connected with the EN pin of the power conversion chip U5, the first end of the capacitor C16 and the 5V power supply end respectively, the LX pin of the power conversion chip U5 is electrically connected with the first end of the inductor L4, the FB pin of the power conversion chip U5 is electrically connected with the first end of the resistor R14, the first end of the capacitor C15 and the first end of the resistor R15 respectively, the second end of the inductor L4 is electrically connected with the second end of the resistor R14, the second end of the capacitor C15, the first end of the capacitor C17 and the first end of the resistor R13 respectively, the second end of the resistor R13 is electrically connected with the 2.5V power supply end, and the second end of the capacitor C16, the GND pin of the power conversion chip U5, the second end of the resistor R15 and the second end of the capacitor C17 are grounded respectively.

5. The small volume visual development board based on Quartus platform according to claim 2, characterized in that: The 5V-1.2V conversion circuit comprises a power conversion chip U3, an inductor L2, a resistor R7, a resistor R8, a resistor R6, a capacitor C9, a capacitor C10, a capacitor C11, The VIN pin of the power conversion chip U3 is electrically connected with the EN pin of the power conversion chip U3, the first end of the capacitor C9 and the 5V power supply end respectively, the LX pin of the power conversion chip U3 is electrically connected with the first end of the inductor L2, the FB pin of the power conversion chip U3 is electrically connected with the first end of the resistor R7, the first end of the capacitor C10 and the first end of the resistor R8 respectively, the second end of the inductor L2 is electrically connected with the second end of the resistor R7, the second end of the capacitor C10, the first end of the capacitor C11 and the first end of the resistor R6 respectively, the second end of the resistor R6 is electrically connected with the 1.2V power supply end, and the second end of the capacitor C9, the GND pin of the power conversion chip U3, the second end of the resistor R8 and the second end of the capacitor C11 are grounded respectively.

6. The small visual development board based on Quartus platform according to claim 2, characterized in that: The USB conversion chip U8, the TYPE-C socket J1, the crystal oscillator Y1, the crystal oscillator Y2, the inductor L5, the resistor R305, the resistor R306, the capacitor C27, the capacitor C34, the capacitor C35 and the capacitor C28, The VCC pin of the USB conversion chip U8 is electrically connected with the 5V_USB power supply end and the first end of the capacitor C28 respectively, the TXD pin and the RXD pin of the USB conversion chip U8 are electrically connected with the FPGA main chip U6 respectively, the V3 pin of the USB conversion chip U8 is electrically connected with the first end of the capacitor C27, the GND pin of the USB conversion chip U8 and the second end of the capacitor C27 are grounded respectively, the UD+ pin of the USB conversion chip U8 is electrically connected with the DP1 pin and the DP2 pin of the TYPE-C socket J1 respectively, the UD- pin of the USB conversion chip U8 is electrically connected with the DN1 pin and the DN2 pin of the TYPE-C socket J1 respectively, the XI pin of the USB conversion chip U8 is electrically connected with the first end of the crystal oscillator Y1, the first end of the crystal oscillator Y2 and the first end of the capacitor C34 respectively, the XO pin of the USB conversion chip U8 is electrically connected with the second end of the crystal oscillator Y1, the second end of the crystal oscillator Y2 and the first end of the capacitor C35 respectively, the second end of the capacitor C34, the second end of the capacitor C35 and the second end of the capacitor C28 are grounded respectively, the resistor R305 is connected in series between the CC2 pin of the TYPE-C socket J1 and the ground end, the resistor R306 is connected in series between the CC1 pin of the TYPE-C socket J1 and the ground end, the first end of the inductor L5 and each GND pin of the TYPE-C socket J1 are grounded respectively, the second end of the inductor L5 is electrically connected with each SH pin of the TYPE-C socket J1 respectively, each VBUS pin of the TYPE-C socket J1 is electrically connected with the 5V_USB power supply end.

7. The small visual development board based on Quartus platform according to claim 1, characterized in that: The image acquisition circuit comprises a camera socket J11 and a plurality of voltage stabilizing resistors, the VDD pin of the camera socket J11 is electrically connected with the output end of the 12V-5V conversion circuit, the SCL pin of the camera socket J11 is electrically connected with the I2C1_SCL pin of the FPGA main chip U6, the SDA pin of the camera socket J11 is electrically connected with the I2C1_SDA pin of the FPGA main chip U6, the GND pin of the camera socket J11 is grounded, and each voltage stabilizing resistor is connected in series between the camera socket J11 and the FPGA main chip U6.

8. The small visual development board based on Quartus platform according to claim 1, characterized in that: The image output circuit comprises a VGA interface circuit, an HDMI interface circuit and an LCD interface circuit, and the VGA interface circuit, the HDMI interface circuit and the LCD interface circuit are electrically connected with the FPGA main chip U6 and the power supply circuit respectively.

9. The small volume visual development board based on Quartus platform according to claim 1, characterized in that: The key control circuit comprises a reset key circuit and at least one user key circuit, The reset button circuit comprises a button SW1, a capacitor C58, a resistor R47, a resistor R48 and a bidirectional diode Z1. The first end of the button SW1 is electrically connected with the second end of the resistor R48, the second end of the resistor R47, the second end of the bidirectional diode Z1 and the first end of the capacitor C58 respectively. The second end of the button SW1 is electrically connected with the second end of the capacitor C58 and the ground terminal respectively. The first end of the resistor R48 is electrically connected with the output terminal of the 5V-3.3V conversion circuit. The first end of the resistor R47 is electrically connected with the RESET pin of the FPGA main chip U6. The first end of the bidirectional diode Z1 is grounded. The user button circuit comprises a button SW2, a capacitor C60, a resistor R51, a resistor R52 and a bidirectional diode Z2. The first end of the button SW2 is electrically connected with the second end of the resistor R52, the second end of the resistor R51, the second end of the bidirectional diode Z2 and the first end of the capacitor C60 respectively. The second end of the button SW2 is electrically connected with the second end of the capacitor C60 and the ground terminal respectively. The first end of the resistor R52 is electrically connected with the output terminal of the 5V-3.3V conversion circuit. The first end of the resistor R51 is electrically connected with the KEY1 pin of the FPGA main chip U6. The first end of the bidirectional diode Z2 is grounded.

10. The small volume visual development board based on Quartus platform according to claim 9, characterized in that: The visual development board is also provided with an LED indication circuit, which comprises a light-emitting diode D6, a light-emitting diode D7, a light-emitting diode D8, a light-emitting diode D9, a resistor R63, a resistor R161, a resistor R162 and a resistor R163, The first end of the light-emitting diode D6, the first end of the light-emitting diode D7, the first end of the light-emitting diode D8 and the first end of the light-emitting diode D9 are electrically connected with the output terminal of the 5V-3.3V conversion circuit respectively. The resistor R63 is connected in series between the second end of the light-emitting diode D6 and the LED0 pin of the FPGA main chip U6. The resistor R161 is connected in series between the second end of the light-emitting diode D7 and the LED1 pin of the FPGA main chip U6. The resistor R162 is connected in series between the second end of the light-emitting diode D8 and the LED2 pin of the FPGA main chip U6. The resistor R163 is connected in series between the second end of the light-emitting diode D9 and the LED3 pin of the FPGA main chip U6.

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