Integrated circuit device

Abstract

An integrated circuit device includes a device layer, a metallization stack, a backside distribution network, at least one signal transmission conductor, and a plurality of copper via windows. The device layer includes a plurality of electronic devices. A metallization stack is disposed on a front side of the device layer and includes a plurality of patterned metal layers spaced apart by an inter-metal dielectric layer. A backside distribution network is disposed on a backside of the device layer. At least one signal transmission conductor is disposed on the backside of the device layer. A plurality of copper vias pass through the device layer, the plurality of copper vias being electrically connected to the at least one signal transmission conductor and the at least one patterned metal layer of the metallization stack.

Description

Technical Field

[0001] This disclosure relates to integrated circuit devices. Background Technology

[0002] The following content concerns semiconductor device technology, integrated circuit technology, and prior art. Utility Model Content

[0003] According to some embodiments disclosed herein, an integrated circuit device includes: a device layer including a plurality of electronic devices; a metallization stack disposed on a front side of the device layer and including a plurality of patterned metal layers spaced apart by inter-metal dielectric layers, the metallization stack being electrically connected to the plurality of electronic devices of the device layer; a back-side power distribution network disposed on a back side of the device layer, the back-side power distribution network being electrically connected to a power source to the plurality of electronic devices of the device layer; at least one signal transmission conductor disposed on the back side of the device layer; and a plurality of copper dielectric windows, through the device layer, the plurality of copper dielectric windows being electrically connected to the at least one signal transmission conductor and at least one of the patterned metal layers of the metallization stack.

[0004] According to some embodiments disclosed herein, an integrated circuit device includes: a device layer including a plurality of electronic devices; a metallization stack disposed on a front side of the device layer and including a plurality of patterned metal layers spaced apart by inter-metal dielectric layers; a back-side power distribution network disposed on a back side of the device layer, the back-side power distribution network being electrically connected to a power source to the plurality of electronic devices of the device layer; an etch stop layer disposed on the back side of the device layer; at least one signal transmission conductor disposed on the back side of the device layer; and a plurality of dielectric windows electrically connected to the at least one signal transmission conductor and at least one patterned metal layer of the metallization stack through the device layer and the etch stop layer.

[0005] According to some embodiments disclosed herein, an integrated circuit device includes: a device layer including a plurality of electronic devices; a metallization stack disposed on a front side of the device layer and including a plurality of patterned metal layers; a back-side power distribution network disposed on a back side of the device layer, the back-side power distribution network being electrically connected to a power source; a back-side dielectric layer disposed on the back side of the device layer; at least one signal transmission conductor disposed on the back side of the device layer; and a dielectric window passing through the device layer and the back-side dielectric layer and electrically connected to the at least one signal transmission conductor and the at least one patterned metal layer of the metallization stack. Attached Figure Description

[0006] The various features of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A schematic cross-sectional view of an IC is shown, the IC including at least one signal transmission conductor disposed on the back side of the device layer of the IC;

[0008] Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E A schematic cross-sectional view illustrating the continuous stages of IC manufacturing, the IC including at least one signal transmission conductor disposed on the back side of the device layer of the IC;

[0009] Figure 3 A schematic perspective view illustrating the isolation of signal transmission conductors disposed on the back side of the device layer of an IC;

[0010] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H and Figure 4I A cross-sectional view schematically illustrating a series of stages in fabricating a copper dielectric window for connection to a signal transmission conductor disposed on the back side of a device layer of an IC using a mosaic process according to an embodiment.

[0011] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E , Figure 5F , Figure 5G , Figure 5H and Figure 5I A cross-sectional view schematically illustrating a series of stages in fabricating a copper dielectric window for connection to a signal transmission conductor disposed on the back side of a device layer of an IC using a dual damascene process according to an embodiment.

[0012] [Symbol Explanation]

[0013] 10: Device Layer

[0014] 12: Metallization Stacking

[0015] 14: Front side

[0016] 16: Metal layer

[0017] 18: IMD layer

[0018] 20: Backside power distribution network

[0019] 24: Dorsal side

[0020] 26: Backside dielectric material

[0021] 26-1: Lower part

[0022] 26-2: Upper part

[0023] 28: Transmission conductor

[0024] 28-1, 28-2: Metallic layer

[0025] 30: Mesoscopic window

[0026] 30C: Conductor

[0027] 30EX: Copper

[0028] 32:Substrate

[0029] 34: Carrier wafer

[0030] 36: Adhesive

[0031] 40: Epitaxial Growth Materials

[0032] 42: STI oxide

[0033] 43: Etching stop layer

[0034] 44: SiN layer

[0035] 46, 76, 86: Bottom layer

[0036] 48, 78, 88: Intermediate layer

[0037] 50, 80: Patterned photoresist

[0038] 52, 82, 82C, 92, 94C: Open

[0039] 54, 94: Partial mesoscopic window opening

[0040] 56, 96: Interlayer window opening

[0041] 58: Residue

[0042] 60: Thin layer

[0043] 62: Exposed end

[0044] 70:TEOS

[0045] 72: Hard Mask

[0046] 74:TEOS

[0047] 90: Photoresist layer

[0048] 96C: Groove

[0049] D1, D2: Semiconductor devices Detailed Implementation

[0050] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0051] In addition, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms are used herein to describe the relationship between one element or feature and another illustrated in the figures. Besides the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0052] A typical integrated circuit (IC) comprises a device layer formed during front-end-of-line (FEOL) processing and a metallization stack formed during back-end-of-line (BEOL) processing. The device layer typically comprises various semiconductor devices, such as field-effect transistors (FETs), diodes, photodiodes, etc., fabricated on or within the front surface of a semiconductor substrate made of silicon (e.g., silicon wafers) or another semiconductor material. The device layer is formed using various semiconductor processing operations such as dopant diffusion and / or implantation, etching, and material deposition. Subsequently, a metallization stack is formed on the front side of the substrate, and more specifically, on the device layer. In a typical BEOL process, each layer of the metallization stack is formed by the following steps: depositing an intermetallic dielectric (IMD) layer; opening and filling the dielectric window openings in the IMD layer to form a dielectric window (i.e., feedthrough) through the IMD layer; depositing a metal layer on the IMD layer and patterning the metal layer to form a patterned metal layer. The device terminal of the device layer is contacted through the interlayer window of the first IMD layer.

[0053] Therefore, typical signal transmission is achieved by inputting power into a device in the device layer, and then transmitting the signal to another device in the device layer via BEOL wiring of a metallized stack disposed on the front side of the substrate. Signals can pass through numerous patterned metal layers of the metallized stack and through interfaces between different materials. For example, the interposer window can be made of tungsten (W), while the patterned metal layers can be copper, and other types of materials, such as aluminum, can also be incorporated. Therefore, using electricity for signal transmission via the front-side metallized stack is inefficient and impractical, resulting in slower signal transmission speeds, resistive power losses in long front-side transmission paths, and current losses at interfaces between different materials.

[0054] As ICs become increasingly miniaturized and more complex device circuit systems are implemented, these signal processing issues become increasingly problematic. Miniaturization reduces signal path length, but with higher device counts and densities, the amount of wiring in the metallization stack increases, which may require additional patterned metal layers to extend path lengths. In some modern ICs, the metallization stack can contain more than a dozen patterned metal layers, where signal loss occurs each time a signal travels between layers. Larger IC circuit system areas can also specify longer path lengths. If the IC occupies an area of ​​N... 2In a square region, the maximum possible distance between a pair of devices increases with the increase of N. Layout design can mitigate this by avoiding connections between devices near the opposite edges of the IC region, but this may prevent the implementation of long signal connections.

[0055] Another challenge is power delivery to the IC. This is typically accomplished via front-side metallization stacking, further increasing the density and complexity of wiring implemented within the stack. This challenge can be mitigated by using a back-side power distribution network (BS-PDN). A BS-PDN comprises conductors formed on the back side of the substrate, sometimes referred to as power delivery rails. Advantageously, BS-PDN separates power delivery at the back side of the substrate from signal transmission via the front-side metallization stack. However, BS-PDN does not address other signal transmission challenges arising from IC miniaturization, namely, long signal paths across multiple materials (e.g., copper / tungsten interfaces).

[0056] In the method disclosed herein, signal transmission paths are disposed on the back side of the substrate. These back-side signal transmission paths can be an extension of BS-PDN and complement conventional front-side signal transmission via front-side metallization stacking. The back-side signal transmission paths are designed for signals particularly susceptible to the transmission challenges of long signal paths traversing multiple materials. For example, high-current signals can experience higher resistive (IR) power losses P = I. 2 R, where I is the current magnitude, R is the resistance of the signal path, and P is the resistive power loss. Therefore, the signal power loss increases with the square of the current. Similarly, high-frequency signals can experience higher power loss due to the skin effect, where at higher frequencies, current is primarily carried at the surface of the conductor. Signal paths between more distant device pairs will also experience higher power loss. For example, a signal carried from a device near one edge of the IC region to a device near the opposite edge of the IC region will have a longer total signal path and a higher I. 2 R loss.

[0057] The back-side signal transmission path disclosed in this paper is suitable for transmitting signals that are expected to have higher power loss for such reasons, while conventional front-side metallization stacks are used for transmitting other signals.

[0058] Furthermore, the back-side signal transmission path disclosed herein is designed to minimize resistive signal loss when manufactured using processes highly compatible with existing IC manufacturing workflows. For example, the disclosed back-side signal transmission path uses an all-copper dielectric window (i.e., an all-copper feedthrough) formed by a damascene process to connect to a patterned metal layer of a front-side metallized stack. This damascene process requires as few as a single additional masking step and wet and / or dry etching to form the dielectric window opening filled by electroplating and chemical mechanical polishing (CMP). In some embodiments, a dual damascene process is employed, which also advantageously forms the patterned metal layer of the back-side power distribution network and / or the back-side signal transmission conductor. This approach advantageously eliminates the interface between different materials because the back-side signal transmission path is all copper.

[0059] refer to Figure 1 The integrated circuit includes a device layer 10, which includes multiple electronic devices. Figure 1 (Not shown separately). Device layer 10 is typically formed during FEOL processing. A metallization stack 12 is disposed on the front side 14 of device layer 10. The metallization stack 12 includes a plurality of patterned metal layers 16 spaced apart by an inter-metal dielectric material layer 18 (or inter-metal dielectric layer). The metallization stack 12 is typically formed during BEOL processing and electrically interconnects the electronic devices of device layer 10. A back-side power distribution network 20 is disposed on the back side 24 of device layer 10 and connected to deliver power to a plurality of semiconductor devices of device layer 10. The back-side power distribution network 20 is embedded in or disposed in a back-side dielectric material 26. The illustrative back-side power distribution network 20 includes a lower portion 26-1 electrically connected to the semiconductor devices of device layer 10 and an upper portion 26-2 forming a power distribution rail or the like. In a non-limiting illustrative example, the lower portion 26-1 includes tungsten and the upper portion 26-2 includes copper, but other materials are also contemplated. In some non-limiting embodiments, the back-side dielectric material 26 may be a low-k dielectric material, having a dielectric constant κ less than that of silicon dioxide (SiO2, κ = 3.9). For example, in some non-limiting embodiments, the back-side dielectric material 26 may be a low-k dielectric material, such as fluorinated silicon dioxide, organosilicate glass (OSG), or various combinations thereof.

[0060] At least one signal transmission conductor 28 is also disposed on the back side 24 of the device layer 10 and embedded or disposed in the dielectric material 26. The at least one signal transmission conductor 28 is used to transmit electrical signals between devices in the device layer 10. A copper dielectric window (i.e., a copper feedthrough) 30 passes through the device layer 10. The copper dielectric window 30 electrically connects the at least one signal transmission conductor 28 to at least one patterned metal layer 16 of the metallization stack 12.

[0061] For reference Figures 2A to 2E It describes the manufacturing process. Figure 1 The appropriate method for IC. Figures 2A to 2E A schematic cross-sectional view illustrating the continuous stages of IC manufacturing. Figure 2A The substrate 32 is described below. As some non-limiting illustrative examples, the substrate 32 may include a silicon wafer, a silicon-on-insulator (SOI) wafer, a silicon-germanium wafer, a gallium arsenide wafer, or another semiconductor substrate. Front-end-of-line (FEOL) processing is performed to form semiconductor devices, such as field-effect transistors (FETs), diodes, photodiodes, resistors, capacitors, and various combinations thereof, on or within the semiconductor wafer 32. These semiconductor devices constitute device layer 10. It should be noted that in some IC designs, device layer 10 may contain multiple layers of semiconductor devices. Various semiconductor processing operations, such as dopant diffusion and / or implantation, etching, and material deposition, are used to form the devices of device layer 10 on or within the substrate 32. After the FEOL processing, a back-end-of-line (BEOL) processing is performed on the front side 14 of device layer 10 (e.g., the front side 14 of device layer 10 away from substrate 32) to form a metallization stack 12. Each layer of the metallization stack 12 is formed by the following steps: depositing a portion of an intermetallic dielectric (IMD) layer 18; opening and filling a dielectric window opening in the IMD layer (of that portion) to form a dielectric window through the IMD layer; depositing a metal layer on the IMD layer and patterning the metal layer to form a patterned metal layer 16; and repeating this process sequentially to form each metal layer 16. A terminal of the device in the device layer 10 is contacted through the dielectric window of the first IMD layer. The resulting structure is schematically shown in [illustration missing]. Figure 2B In the cross-sectional view.

[0062] To form the back-side component, substrate 32 is removed. For this purpose, refer to... Figure 2C The carrier wafer 34 is bonded to the exposed upper surface of the metallization stack 12 by a suitable adhesive 36. As some non-limiting illustrative examples, the carrier wafer 34 may include a silicon wafer, a sapphire wafer, etc. The adhesive 36 is a material that provides sufficient strength for bonding between the carrier wafer 34 and the IMD layer 18. Reference Figure 2DThe components are shown in a flipped orientation with substrate 32 removed. Substrate removal can be performed using any suitable method. In a non-limiting illustrative example, substrate 32 is an SOI wafer, and substrate removal requires the removal of an insulating layer (e.g., silicon dioxide in some SOI wafer designs), leaving an upper silicon layer of the SOI wafer on which semiconductor devices are formed. In this example, device layer 10 includes the devices and the remaining silicon layer of the SOI wafer. (For some SOI wafers, the silicon layer may have a submicron thickness). In other considered methods, substrate 32 can be removed by a back-side applied mechanical or chemical-mechanical thinning process. Figure 2D The resulting structure shown includes a carrier wafer 34, an IMD layer 18 bonded to the carrier wafer 34 by adhesive 36, and a device layer 10, the back side 24 of which is now exposed by removing the substrate 32. (Note again, compared with the previous...) Figures 2A to 2C compared to, Figure 2D The structure is shown in a flipped orientation.

[0063] With the backside 24 of the device layer 10 now exposed, backside components can be fabricated. Forming the backside power distribution network 20 depends on the chosen architecture but typically requires a process similar to BEOL, such as (repeatedly) depositing dielectric material, forming and filling dielectric window openings to form the dielectric window, and depositing and patterning a metal layer. A similar process is used to form at least one transmission conductor 28. A damascene process (described in further detail later herein) can be used to form dielectric windows 30 connected to at least one transmission conductor 28. In some embodiments disclosed later herein, a dual damascene process can be used to form dielectric windows 30 connected to at least one transmission conductor 28 and also to form at least one transmission conductor 28 and / or the bottommost metal layer of the backside power distribution network 20.

[0064] To further illustrate the characteristics of the transmission conductor 28 and the dielectric window 30 Figure 3 A schematic perspective view illustrating the isolation of the signal transmission conductor 28 disposed on the back side of the device layer 10 of the IC. Figure 3 In this illustrative example, two schematically illustrated semiconductor devices D1 and D2 are connected by a transmission conductor 28. More specifically, in this non-limiting illustrative example, devices D1 and D2 are connected to the two bottommost metal layers 16 of the metallization stack 12, and as shown, an interlayer window 30 is connected at one end to one of these metal layers 16, through the device layer 10, and at the opposite end to the transmission conductor 28. Figure 3In this example, the transmission conductor 28 itself is made of two metal layers 28-1 and 28-2. Clearly, the total transmission length is short because it passes only through the bottom two metal layers 16 of the front metallization stack 12 (in some more complex IC designs, it may have twelve or more total metal layers), through the copper dielectric window 30, and through the transmission conductor 28, which in this instance comprises only two layers 28-1 and 28-2. This is much shorter than the typical transmission length when only the metallization stack 12 is used for signal transmission, because in that case, the signal may need to be routed through many metal layers of the stack 12, especially when the signal needs to be transmitted over long distances (e.g., from a device near one edge of the IC region to a second device near the opposite edge of the IC region).

[0065] The following describes some non-limiting illustrative examples of the inlay process used to manufacture the copper interlayer window 30.

[0066] refer to Figures 4A to 4I The diagram shows a cross-sectional view of the continuous stages of manufacturing a copper dielectric window using the inlay process according to the first embodiment. Figure 4A Explain the IC and Figure 2D This corresponds to (i.e., after removing substrate 32) and is a portion after the deposition of the first layer of back-side dielectric material 26 and the formation of the first layer of back-side power distribution network 20. As previously mentioned, the back-side dielectric material 26 may be, for example, a low-k dielectric material. Device layer 10 is schematically indicated by a portion of epitaxial growth material 40 and surrounding shallow trench isolation (STI) oxide 42 (or shallow trench isolation structure). Interlayer windows are destined to be formed through device layer 10, and more specifically, through STI oxide 42. It should also be noted that although epitaxial material 40 is shown schematically to represent a semiconductor device of device layer 10, this is only a non-limiting illustrative example, and more generally, semiconductor devices of device layer 10 can be manufactured in various ways, such as by doped regions created by dopant implantation or dopant diffusion, by deposition of polysilicon regions, etc. It should be noted that Figures 4A to 4I The IC portion shown only shows the metal layer 16 of the metallized stack 12. Figures 4A to 4I Illustrative examples also illustrate silicon dioxide (SiO2). x The dielectric layer and such as (depending on the etchant) SiN, AlO x ZrO xVarious etch stop layers (ESLs) such as AlOx, ZrOx, and AlN are used. Depending on the IC manufacturing workflow, different types of ESLs can be used to provide etch termination at different depths using appropriate material-selective etchants. As an example, the back side 24 of device layer 10 has etch stop layers (ESLs) 43 such as AlOx, ZrOx, and AlN, as some non-limiting illustrative examples.

[0067] Figure 4B This describes the IC portion following the deposition of SiN layer 44 on ESL 43. Figure 4C This describes the IC portion after deposition of a hard mask comprising a bottom layer (BL) 46 and an intermediate layer 48. In one non-limiting illustrative embodiment, the bottom layer 46 is SiCO, but other materials are also considered. In one non-limiting illustrative embodiment, the intermediate layer 48 is SiCHO or amorphous carbon, but other materials are also considered. A photoresist layer is applied to the intermediate layer 48 and the photoresist layer is photolithographically patterned (e.g., by exposure via a photomask to form a latent image in the photoresist, followed by development of the photoresist) to form a patterned photoresist 50 with an opening 52, through which an etched interlayer window opening is formed.

[0068] Figure 4D The description describes the IC portion after further processing to form a partial dielectric window opening 54, where the partial dielectric window opening 54 is a continuation of opening 52 through these layers and terminates at an ESL layer 43 disposed on the back side 24 of device layer 10. This can be achieved, for example, by etching the materials of ML 48, BL 46, SiN 44, and back side dielectric material 26, but without etching the ESL layer 43 disposed on the back side 24 of device layer 10 (e.g., as some non-limiting examples, AlO). x ZrO x This is accomplished by dry etching of the AlN layer. The process also includes stripping the photoresist 50 and removing the intermediate layer 48, so that the bottom layer 46 is used as a mask for subsequent etching steps. Figure 4E This describes the IC portion after further wet etching to remove the portion of ESL layer 43 located at the bottom of opening 54.

[0069] Figure 4F This describes the IC portion following the formation of a complete via window 56 landing on the patterned metal layer 16 of the metallization stack 12, after further etching to extend the via window 54 through the device layer 10. Again, the bottom layer 46 serves as a mask for this etching (e.g., ...). Figure 4FAs schematically shown, the etching can erode the underlying layer 46, and the erosion is sufficient to thin it. Dry etching can be used, for example, to etch through the dielectric layer of STI oxide 42 and the metallization stack 12, up to the patterned metal layer 16. However, this etching can leave residue 58 at the bottom of the dielectric window opening 56. This residue 58, if left in situ, will undesirably increase the copper dielectric window 30 (in... Figure 4F The resistance at the interface between the unformed (not yet formed) and the patterned metal layer 16. Therefore, in the liner removal step (e.g., suitable wet etching or similar), this residue 58 is removed or stripped, thereby producing a resistance such as Figure 4G The portion of the IC depicted in the diagram shows a section of the patterned metal layer 16 exposed by a mesop window opening 56. In some workflows, an after-stripping inspection (ASI) may be performed to verify the removal of residue 58. Therefore, in Figure 4G The structure in this stage has a fully formed mesoscopic window opening 56. According to the tiling process, the mesoscopic window opening 56 is then filled with copper by a copper plating process.

[0070] Figure 4H The structure after copper plating is described. To protect the walls of the dielectric window opening 56 during the copper plating process, optionally, a thin layer 60 of a protective material such as tantalum (Ta), tantalum nitride (TaN), silicon nitride (SiN), or silicon carbide (SiC) may be applied to the walls of the dielectric window opening 56 before copper plating. For copper plating, a thin copper seed layer is applied, for example by physical vapor deposition (PVD), chemical vapor deposition (CVD), or another suitable technique, followed by copper plating itself on the seed layer. The copper plated in the copper dielectric window opening 56 forms a copper dielectric window (i.e., a copper feedthrough) 30. However, the plating is not limited to the dielectric window opening 56, but also includes plating copper 30EX on the SiN layer 44, thereby plating an excess of copper 30EX on the surface of the SiN layer 44, such as... Figure 4H As seen in the image. Therefore, after copper electroplating, chemical mechanical polishing (CMP) is performed to remove excess copper 30EX, thereby obtaining the desired result. Figure 4I The final copper dielectric window 30 is shown.

[0071] Continue to refer to Figure 4IThe fabricated copper dielectric window 30 electrically contacts the patterned metal layer 16 of the metallized stack 12. The specific patterned metal layer used for contact can vary; however, to obtain extremely low resistance, it is generally preferred to contact a patterned metal layer (e.g., metal layer M0 or M1) located near the device layer 10. Although Figure 4I Not shown in the diagram, but the exposed end 62 of the copper dielectric window 30 will contact the signal transmission conductor 28 (in...). Figure 4I The steps shown have not yet been formed, but see [link / reference]. Figure 2E and Figure 3 (and related discussions). As previously discussed, the signal transmission conductor 28 is disposed on the back side 24 of the device layer 10 and is embedded in or disposed in the back side dielectric material 26. Figure 2E (As seen in the diagram). If the signal transmission conductor 28 is a copper transmission conductor, then a full copper path is provided from the patterned metal layer 16 of the front metallization stack 12 through the device layer 10 to the copper transmission conductor 28. (As shown in the diagram). Figure 2E As further seen, copper dielectric windows 30 are present at both ends of the copper transmission conductor 28, thereby providing a low-resistance signal transmission path. This path is entirely copper, except for a thin layer 60 of protective material (e.g., Ta, TaN, SiN, SiC, etc.)—however, this thin layer 60 is typically only a few angstroms thick and may contain a conductive material (e.g., Ta), and therefore does not introduce significant additional resistance.

[0072] Figures 4A to 4I The manufacturing process is a damascene process, in which a mesoscopic window opening 56 is formed, copper is electroplated in the mesoscopic window opening 56 to form a copper mesoscopic window 30, and excess copper 30EX is removed by chemical mechanical polishing. It should be noted that the detailed etching sequence in the damascene process used to manufacture the copper mesoscopic window 30 can vary depending on factors such as the number, depth, and material of the etch-stop layers in the structure. Figures 4A to 4I The etching sequence differs from that described in the non-limiting illustrative examples. Generally, the damascene process enables the formation of copper via windows 30 with relatively small diameters (e.g., 50 nm to 100 nm in some non-limiting illustrative embodiments), thereby facilitating miniaturization and compatibility with IC manufacturing workflows with small critical size. It should also be understood that, although... Figures 4A to 4I This describes the formation of a single copper dielectric window 30, but the process can utilize appropriate patterning of the photoresist 50, for example, by using openings 52 located at the positions where each copper dielectric window 30 will be formed, to appropriately form any number of copper dielectric windows 30.

[0073] More specifically, Figures 4A to 4I The manufacturing process is a single damascene process for forming the interlayer window 30. Backside electrical conductors, such as signal transmission conductors 28 and / or conductors of the backside power distribution network 20, are formed by another process, such as the deposition of a blanket copper layer and photolithography patterning.

[0074] refer to Figures 5A to 5I In some embodiments, the copper dielectric window 30 is formed using a dual damascene process, which also forms the electrical conductor layer 30C (see [link]). Figure 5H and Figure 5I Conductor 30C can be used as a (partial) back-side conductor, such as forming signal transmission conductor 28 and / or back-side power distribution network 20. Except where ESL 43 is absent and in Figure 5A In the stage shown, except for any portion of the back-side dielectric material 26 that has not yet been deposited, Figure 5A Explain the IC and Figure 4A It is a part similar to an IC. Figure 5A The description includes a device layer 10 containing an illustrative semiconductor device 40 and an STI oxide 42, and a front metallization stack 12 located on the front side 14 of the device layer 10.

[0075] Figure 5B The description covers the IC portion following the formation of the back-side dielectric layer or dielectric material 26 (in this embodiment, it is an extremely low-k dielectric material, i.e., an ELK dielectric), the tetraethyl orthosilicate (TEOS) 70 layer, the hard mask 72, the second TEOS layer 74, the mask including the bottom layer 76, the intermediate layer 78, and the patterned photoresist 80 with openings 82 and 82C formed therein. It should be noted that... Figures 4A to 4I The (single) inlay technique is different, in Figures 5A to 5I In the dual damascene process, the opening 82 for forming the copper dielectric window 30 and the opening 82C for forming the copper conductor 30C are both patterned in the photoresist. The bottom layer 76, the intermediate layer 78, and the patterned photoresist 80 can be similar to... Figure 4C The single-staple embodiment is formed by corresponding bottom layer 46, intermediate layer 48, and patterned photoresist 50. Etching through photoresist openings 82 and 82C transfers these openings to the TEOS 70 / hard mask 72 / TEOS 74 stack, and strips mask layers 76, 78, and photoresist 80, thereby creating Figure 5C The structure is shown in the figure. It should be noted that while the photoresist opening 82 corresponding to the designated copper dielectric window 30 will generally be circular and / or have a low aspect ratio, the photoresist opening 82C corresponding to the designated conductor 30C may generally include a high aspect ratio opening, such as a trench, which may or may not be linear (e.g., the photoresist opening 82C may be curved or otherwise shaped to correspond to the conductor 30C to be formed in the dual damascene process).

[0076] Next, as Figure 5DAs shown, a new mask is formed, comprising a bottom layer 86, an intermediate layer 88, and a patterned photoresist layer 90. Here, the patterned photoresist layer 90 only has an opening 92 corresponding to the designated copper dielectric window 30, but does not have an opening corresponding to the designated copper conductor 30C.

[0077] The etching process involves a portion of the interlayer window opening 94, marked by the photoresist opening 92. This portion of the interlayer window opening 94 penetrates the device layer 10 and a portion of the metallized stack 12, but does not reach the metal layer 16 of the front metallized stack 12. Figure 5E As seen in the image. This step also includes removing or peeling off the photoresist layer 90 and the intermediate layer 88, leaving only the bottom layer 86, as shown. Figure 5E Further observations can be made.

[0078] like Figure 5F As shown, the bottom layer 86 is then removed. This is done through etching, which also exposes the opening 94C in the TEOS 70 / Hard Mask 72 / TEOS 74 stack. The opening 94C corresponds to the designated copper conductor 30C, as shown. Figure 5F As seen in the image. Further etching is performed to deepen the opening 94, thereby forming a complete interlayer window opening 96 landing on the metal layer 16 of the front metallization stack 12, as shown. Figure 5G As seen in the text. Figure 5G As further seen, the etching deepens the opening 94C, thereby forming an opening 96C in the form of a trench 96C, which will be filled with copper during the subsequent copper plating step to form the copper conductor 30C.

[0079] As previously described, copper plating then occurs, i.e., a thin layer 60 (or diffusion barrier layer) of a protective material (e.g., Ta, TaN, SiN, SiC, etc.) is optionally deposited, and a thin copper seed layer is deposited by PVD, CVD, or another suitable technique, followed by copper electroplating itself on the seed layer. Copper plated in the copper dielectric window opening 96 forms a copper dielectric window (i.e., a copper feedthrough) 30, while copper plated in the trench 96C forms a copper conductor 30C. Additionally, excess copper 30EX is formed on the upper surface, such as... Figure 5H As seen in the image. Following copper electroplating, chemical mechanical polishing (CMP) is performed to remove excess copper 30EX, resulting in the desired product. Figure 5I The final copper dielectric window 30 and copper conductor 30C are shown.

[0080] As previously mentioned, in some embodiments, the copper conductor 30C may be used as at least one signal transmission conductor 28. In such cases, refer again... Figure 5GThe trench 96C may intersect with the dielectric window opening 96, and this combined structure is electroplated to form each signal transmission conductor 28 and its terminating copper dielectric window 30 as a single copper structure. This can advantageously improve the mechanical strength of the conductive structure and reduce resistance.

[0081] In the illustrative embodiment, a back-side signal transmission path comprising a copper dielectric window 30 and at least one signal transmission conductor 28 is used in conjunction with a back-side power distribution network 20, both disposed on the back side 24 of the device layer 10. This is advantageous because the process steps for forming the back-side power distribution network 20 can be used, for example, by modifying the mask used to manufacture the back-side power distribution network 20 to simultaneously form the copper dielectric window 30 and / or at least one signal transmission conductor 28. However, it is also contemplated to use a back-side signal transmission path comprising a copper dielectric window 30 and at least one signal transmission conductor 28 without using the back-side power distribution network 20.

[0082] Several other embodiments are described below.

[0083] In a non-limiting illustrative embodiment, a method of manufacturing an integrated circuit is disclosed. The method includes: forming a device layer comprising a plurality of electronic devices; forming a metallization stack on the front side of the device layer, the metallization stack comprising a plurality of patterned metal layers spaced apart by an intermetallic dielectric material, the plurality of patterned metal layers electrically interconnecting the electronic devices of the device layer; forming a back-side power distribution network on the back side of the device layer, the back-side power distribution network comprising at least one back-side patterned metal layer connected to power terminals of the plurality of semiconductor devices of the device layer; and forming copper dielectric windows through the device layer and contacting at least one patterned metal layer of the metallization stack, the plurality of copper dielectric windows being formed by a damascene process. In some embodiments, the method further includes: forming at least one signal transmission conductor disposed on the back side of the device layer and electrically connected to the copper dielectric windows. According to some embodiments of this disclosure, the step of forming the device layer includes forming the plurality of electronic devices on and / or in a front side of a semiconductor substrate, and the method further includes bonding the metallization stack to a carrier substrate; and removing the semiconductor substrate to expose the back side of the device layer. According to some embodiments of this disclosure, the damascene process for forming the plurality of copper dielectric windows includes the following steps: disposing at least one back-side dielectric layer on the back side of the device layer; etching a plurality of dielectric window openings from the back side of the device layer and through the at least one back-side dielectric layer and the device layer, wherein the etching of the plurality of dielectric window openings terminates on the at least one patterned metal layer of the metallized stack; electroplating copper on the back side of the device layer and filling the plurality of dielectric window openings to form the plurality of copper dielectric windows that pass through the device layer and contact the at least one patterned metal layer of the metallized stack; and performing chemical mechanical polishing to remove the copper electroplated on the back side of the device layer. According to some embodiments of this disclosure, the damascene process is a dual damascene process, which further includes: etching a plurality of trenches in the at least one back-side dielectric layer prior to the electroplating, wherein the electroplating also fills the plurality of trenches to form a patterned metal layer of the back-side power distribution network. According to some embodiments of this disclosure, the steps of etching the plurality of dielectric window openings and etching the plurality of trenches include: performing a first etching that forms the plurality of trenches and the plurality of partial dielectric window openings; and performing a second etching that extends the plurality of partial dielectric window openings to terminate on the at least one patterned metal layer of the metallized stack. According to some embodiments of this disclosure, the method further includes: forming at least one signal transmission conductor disposed on the back side of the device layer and electrically connected to the plurality of copper dielectric windows by etching at least one trench in the at least one back-side dielectric layer prior to the electroplating, wherein the electroplating also fills the at least one trench to form the at least one signal transmission conductor.According to some embodiments of this disclosure, the method further includes, before setting the at least one back-side dielectric layer, setting a back-side etch stop layer on the back side of the device layer, wherein the step of etching the plurality of dielectric window openings includes: performing a first etching to form a plurality of partial dielectric window openings, the plurality of partial dielectric window openings passing through the at least one back-side dielectric layer and terminating at the back-side etch stop layer; removing a plurality of portions of the back-side etch stop layer disposed at a plurality of bottoms of the plurality of partial dielectric windows; and performing a second etching to extend the plurality of partial dielectric window openings through the device layer and terminating on the at least one patterned metal layer of the metallized stack. According to some embodiments of this disclosure, the method further includes: forming at least one signal transmission conductor disposed on the back side of the device layer and electrically connected to the plurality of copper dielectric windows; wherein the plurality of patterned metal layers of the metallized stack include a plurality of patterned copper layers, and the at least one signal transmission conductor includes at least one copper signal transmission conductor.

[0084] In a non-limiting illustrative embodiment, an integrated circuit includes: a device layer including a plurality of electronic devices; a metallization stack disposed on the front side of the device layer and including a plurality of patterned metal layers spaced apart by an intermetallic dielectric material, the metallization stack electrically interconnecting the electronic devices of the device layer; a back-side power distribution network disposed on the back side of the device layer and connected to deliver power to the plurality of semiconductor devices of the device layer; at least one signal transmission conductor disposed on the back side of the device layer; and copper dielectric windows, through the device layer, the plurality of copper dielectric windows electrically connecting the at least one signal transmission conductor to the at least one patterned metal layer of the metallization stack. According to some embodiments of this disclosure, the at least one signal transmission conductor comprises copper. According to some embodiments of this disclosure, the at least one patterned metal layer of the metallization stack comprises copper. According to some embodiments of this disclosure, the metallization stack, the plurality of copper dielectric windows, and the at least one signal transmission conductor form at least one all-copper signal transmission path between the plurality of devices of the device layer. According to some embodiments of this disclosure, the plurality of copper dielectric windows are coated with a copper diffusion barrier layer. According to some embodiments of this disclosure, the copper diffusion barrier layer comprises cobalt or tantalum nitride. According to some embodiments of this disclosure, the integrated circuit further includes a back-side dielectric layer disposed between the back side of the device layer and the at least one signal transmission conductor, and the plurality of copper dielectric windows also pass through the back-side dielectric layer. According to some embodiments of this disclosure, an integrated circuit device includes: a device layer including a plurality of electronic devices; a metallization stack disposed on a front side of the device layer and including a plurality of patterned metal layers spaced apart by inter-metal dielectric layers, the metallization stack being electrically connected to the plurality of electronic devices of the device layer; a back-side power distribution network disposed on a back side of the device layer, the back-side power distribution network being electrically connected to a power source to the plurality of electronic devices of the device layer; at least one signal transmission conductor disposed on the back side of the device layer; and a plurality of copper dielectric windows passing through the device layer, the plurality of copper dielectric windows being electrically connected to the at least one signal transmission conductor and the at least one patterned metal layer of the metallization stack. According to some embodiments disclosed herein, an integrated circuit device includes: a device layer including a plurality of electronic devices; a metallization stack disposed on a front side of the device layer and including a plurality of patterned metal layers spaced apart by inter-metal dielectric layers; a back-side power distribution network disposed on a back side of the device layer, the back-side power distribution network being electrically connected to a power source to the plurality of electronic devices of the device layer; an etch stop layer disposed on the back side of the device layer; and a plurality of dielectric windows electrically connected to at least one signal transmission conductor and at least one patterned metal layer of the metallization stack through the device layer and the etch stop layer.According to some embodiments of this disclosure, an integrated circuit device includes: a device layer including a plurality of electronic devices; a metallization stack disposed on a front side of the device layer and including a plurality of patterned metal layers; a back-side power distribution network disposed on a back side of the device layer, the back-side power distribution network being electrically connected to a power source; a back-side dielectric layer disposed on the back side of the device layer; at least one signal transmission conductor disposed on the back side of the device layer; and a dielectric window passing through the device layer and the back-side dielectric layer and electrically connected to the at least one signal transmission conductor and the at least one patterned metal layer of the metallization stack. According to some embodiments of this disclosure, the device layer includes a shallow trench isolation structure surrounding the plurality of electronic devices. According to some embodiments of this disclosure, the plurality of electronic devices are semiconductor devices. According to some embodiments of this disclosure, the integrated circuit device further includes a signal transmission path between the plurality of electronic devices in the device layer, wherein the signal transmission path includes the metallization stack, the plurality of copper dielectric windows, and the at least one signal transmission conductor. According to some embodiments of this disclosure, the plurality of copper dielectric windows include a diffusion barrier layer. According to some embodiments of this disclosure, the metallization stack is electrically connected to the plurality of electronic devices of the device layer. According to some embodiments of this disclosure, the integrated circuit device further includes at least one signal transmission conductor disposed on the back side of the device layer.

[0085] In a non-limiting illustrative embodiment, a method for manufacturing an integrated circuit is disclosed. The method includes: forming a device layer including a plurality of electronic devices; disposing at least one dielectric layer on the device layer; etching a dielectric window opening through the at least one dielectric layer and the device layer; electroplating copper on the at least one dielectric layer and filling the dielectric window opening, wherein the copper electroplated in the dielectric window opening forms a copper dielectric window that passes through the at least one dielectric layer and the device layer and is electrically connected to the devices of the device layer; and performing chemical mechanical polishing to remove the copper electroplated on the at least one dielectric layer. In some embodiments, the method further includes: forming at least one signal transmission conductor disposed on the at least one dielectric layer and electrically connected to the copper dielectric window. According to some embodiments of this disclosure, the method further includes: forming a metallization stack on the device layer, wherein the device layer is inserted between the metallization stack and the at least one dielectric layer; wherein the device layer lands on at least one patterned metal layer of the metallization stack through the at least one dielectric layer and the plurality of dielectric window openings of the device layer. According to some embodiments of this disclosure, the method further includes: forming a power distribution network on the at least one dielectric layer. According to some embodiments of this disclosure, the method further includes: etching a plurality of trenches in the at least one dielectric layer prior to the electroplating, wherein the electroplating also fills the plurality of trenches to form a patterned metal layer of the power distribution network. According to some embodiments of this disclosure, the method further includes: forming at least one signal transmission conductor disposed on the at least one dielectric layer and electrically connected to the plurality of copper dielectric windows. According to some embodiments of this disclosure, the method further includes: disposing an etch stop layer on the device layer prior to disposing the at least one dielectric layer, wherein the step of etching the plurality of dielectric window openings includes the following steps: performing a first etching to form a plurality of partial dielectric window openings passing through the at least one dielectric layer and terminating at the etch stop layer; removing a plurality of portions of the etch stop layer disposed at a plurality of bottoms of the plurality of partial dielectric windows; and performing a second etching to extend the plurality of partial dielectric window openings through the device layer.

[0086] The foregoing summary outlines features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit device, characterized by comprising: a device layer comprising a plurality of electronic devices; a metallization stack disposed on a front side of the device layer and comprising a plurality of patterned metal layers separated by intermetal dielectric layers, the metallization stack electrically connected to the plurality of electronic devices of the device layer; a backside power distribution network disposed on a backside of the device layer, the backside power distribution network electrically connecting a power source to the plurality of electronic devices of the device layer; at least one signal transmission conductor disposed on the backside of the device layer; and a plurality of copper via windows through the device layer, the plurality of copper via windows electrically connected to the at least one signal transmission conductor and at least one of the patterned metal layers of the metallization stack. The device layer includes a shallow trench isolation structure surrounding the plurality of electronic devices.

2. The integrated circuit device of claim 1, wherein, The plurality of electronic devices are semiconductor devices.

3. The integrated circuit device of claim 1, wherein, Further comprising a signal transmission path between the plurality of electronic devices of the device layer, wherein the signal transmission path comprises the metallization stack, the plurality of copper via windows, and the at least one signal transmission conductor.

4. The integrated circuit device of claim 1, wherein, The plurality of copper via windows include a diffusion barrier layer.

5. The integrated circuit device of claim 1, wherein, Further comprising:

6. The integrated circuit device of claim 1, wherein, a backside dielectric layer between the backside of the device layer and the at least one signal transmission conductor, the plurality of copper via windows also passing through the backside dielectric layer. comprising:

7. An integrated circuit device, characterized by a device layer comprising a plurality of electronic devices; a metallization stack disposed on a front side of the device layer and comprising a plurality of patterned metal layers; a backside power distribution network disposed on a backside of the device layer, the backside power distribution network electrically connecting a power source to the plurality of electronic devices of the device layer; an etch stop layer disposed on the backside of the device layer; at least one signal transmission conductor disposed on the backside of the device layer; and a plurality of via windows through the device layer and the etch stop layer, the plurality of via windows electrically connected to the at least one signal transmission conductor and at least one of the patterned metal layers of the metallization stack. The metallization stack is electrically connected to the plurality of electronic devices of the device layer. The plurality of via windows include a diffusion barrier layer.

8. The integrated circuit device of claim 7, wherein, comprising:

9. The integrated circuit device of claim 7, wherein, a device layer comprising a plurality of electronic devices; 10. An integrated circuit device, characterized by a metallization stack disposed on a front side of the device layer and comprising a plurality of patterned metal layers; a backside power distribution network disposed on a backside of the device layer, the backside power distribution network electrically connected to a power source; a backside dielectric layer disposed on the backside of the device layer; at least one signal transmission conductor disposed on the backside of the device layer; and a via window through the device layer and the backside dielectric layer and electrically connected to the at least one signal transmission conductor and at least one of the patterned metal layers of the metallization stack. ​ ​ ​

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