Electroplating power supply communication module capable of preventing data loss

Abstract

The utility model discloses an electroplating power supply communication module capable of preventing data loss, which belongs to the technical field of electroplating power supplies and comprises an electroplating power supply module and a communication module. The communication module comprises a down-conversion circuit, a filter amplification circuit, an analog-to-digital conversion module, a filter power amplification circuit, an IF gain module, a digital-to-analog conversion module, a clock module, a power supply module, a serial peripheral equipment interface and an FPGA module, an external power supply AC220V input is rectified and then is subjected to soft start through a silicon controlled soft start circuit, and then filtering is performed; obtained direct current is converted into alternating current through half-bridge inversion, then rectification and filtering are carried out again to obtain needed direct current, and direct current or single pulse is output according to setting of a user; the current detection circuit and the output sampling circuit feed back detected and collected signals to the control center in real time, the control center compares the feedback signals with parameters set by a user and adjusts and outputs control signals, dynamic adjustment is conducted in this way, and it is guaranteed that the circuit outputs according to the parameters set by the user.

Description

TECHNICAL FIELD

[0001] The utility model relates to electroplating power supply communication technical field especially relates to a data loss prevention electroplating power supply communication module. BACKGROUND

[0002] Single-phase pulse rectifier has been widely applied in new energy generation, uninterrupted power supply and railway locomotive traction and other fields due to its high grid-side power factor, small current harmonic and bi-directional energy flow.

[0003] At present, there are many control methods for single-phase pulse rectifier, and these control methods are relatively mature. These control methods can be roughly divided into current control and power control. Among them, the current control takes the grid-side current as the control object, accurately tracks the given grid-side current, and thus realizes the control target of grid-side unit power factor and constant DC side voltage.

[0004] The amplitude and phase of the given grid-side current are closely related to the grid voltage. The power control takes the grid-side active and reactive power as the control object, and indirectly realizes the decoupling control of the grid-side current active and reactive components. The calculation of system power needs to extract the amplitude and phase of the grid voltage fundamental wave and other information.

[0005] Therefore, the implementation of pulse rectifier current control and power control depends on the extraction of grid voltage information.

[0006] Wireless transmission refers to a way of data transmission using wireless technology. Wireless transmission and wired transmission are corresponding. With the increasing development of wireless technology, wireless transmission technology application is more and more accepted by various industries. Wireless image transmission as a special use way is also gradually favored by the majority of users. Its convenient installation, strong flexibility, high cost performance and other characteristics make more industries' monitoring systems adopt wireless transmission mode to establish the connection between the monitored point and the monitoring center.

[0007] Wireless monitoring technology has been widely used in modern transportation, transportation, water conservancy, shipping, railway, public security, fire fighting, border inspection station, forest fire prevention, park, scenic spot, factory, community and other fields. The transmission module in the prior art has more spectrum signal noise and stray, and the signal cannot be concentrated. CONTENT OF THE UTILITY MODEL

[0008] The utility model solves the technical problem in the background art by providing a data loss prevention electroplating power supply communication module.

[0009] The utility model discloses a technical scheme adopted to solve the above technical problems:

[0010] The utility model provides an anti -data loss's electroplating power supply communication module contains electroplating power supply module and communication module, electroplating power supply module and communication module are connected,

[0011] The communication module comprises a frequency down conversion circuit, a filter amplification circuit, an analog-digital conversion module, a filter power amplification circuit, an IF gain module, a digital-analog conversion module, a clock module, a power module, a serial peripheral interface, an FPGA module, the analog-digital conversion module, the digital-analog conversion module, the clock module, the power module and the serial peripheral interface are connected with the FPGA module respectively, the frequency down conversion circuit, the filter amplification circuit and the analog-digital conversion module are connected in sequence, and the filter power amplification circuit, the IF gain module and the digital-analog conversion module are connected in sequence.

[0012] The electroplating power supply module comprises an external power supply AC220V, a rectifier module, a thyristor soft start module, a filter module, a half-bridge inverter module, a rectifier filter module, a pulse conversion module, an output end, a current detection module, a driving circuit module, a sampling amplification module, an isolation feedback module, a pulse width modulation circuit, a control center, a driving circuit, a liquid crystal screen display module and a button / knob input module, the output end of the external power supply AC220V is connected with the input end of the rectifier module, the output end of the rectifier module is connected with the input end of the thyristor soft start module, the output end of the thyristor soft start module is connected with the input end of the filter module, the output end of the filter module is connected with the input end of the half-bridge inverter module, the output end of the half-bridge inverter module is connected with the input end of the rectifier filter module, the output end of the rectifier filter module is connected with the input end of the pulse conversion module, and the output end of the pulse conversion module is connected with the output end; the output end of the filter module is also connected with the input end of the current detection module, the output end of the current detection module is connected with the input end of the pulse width modulation circuit, the output end of the pulse width modulation circuit is connected with the half-bridge inverter module through the driving circuit, the output end of the rectifier filter module is connected with the input end of the control center and the input end of the pulse width modulation circuit in sequence through the sampling amplification module and the isolation feedback module respectively, the output end of the button / knob input module is connected with the input end of the control center module, the output end of the control center is connected with the input end of the driving circuit, and the output end of the driving circuit is connected with the input end of the pulse conversion module.

[0013] As a further preferred scheme of the utility model discloses a kind of anti-data loss's electroplating power supply communication module, the FPGA module comprises acquisition control unit, data processing and RAM read-write module unit, port control unit, synchronous clock control unit, command frame resolving unit, FIFO data cache unit, Flash data storage control unit, data interpretation unit;The acquisition control unit, port control unit, synchronous clock control unit, command frame resolving unit, FIFO data cache unit, Flash data storage control unit, data interpretation unit are connected with data processing and RAM read-write module unit respectively.

[0014] As a further preferred scheme of the utility model a kind of electroplating power supply communication module of preventing data loss, the control center includes high-stability crystal oscillator module, FPGA master module, USB transmission module, serial module, data processing center, USB interface, gigabit network interface and HDMI interface, the high-stability crystal oscillator module is connected with FPGA master module, the FPGA master module is connected data processing center by SB transmission module, serial module respectively, the USB interface, gigabit network interface and HDMI interface are connected with data processing center respectively.

[0015] As a further preferred scheme of the utility model a kind of electroplating power supply communication module of preventing data loss, the chip model of the USB transmission module is XY7C68013.

[0016] As a further preferred scheme of the utility model a kind of electroplating power supply communication module of preventing data loss, the high-stability crystal oscillator module includes control chip 7N10.000MBP, capacitor C45, resistance R22, resistance R23, resistance R24, capacitor C69 and voltage VCC end, the 8 interface of control chip 7N10.000MBP is connected with one end of resistance R22, the other end of resistance R22 is connected with one end of capacitor C45, 9 interface of control chip 7N10.000MBP, one end of resistance R23 and voltage VCC end respectively, the other end of capacitor C45 is grounded, one end of resistance R23 is connected with one end of resistance R24, the other end of resistance R24 is grounded, the 10 interface of control chip 7N10.000MBP is connected with one end of capacitor C69, the other end of capacitor C69 is grounded.

[0017] As a further preferred scheme of the utility model a kind of electroplating power supply communication module of preventing data loss, the half-bridge inverter module includes resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R8, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor E1, capacitor E2, capacitor E3, capacitor E4, capacitor E5, capacitor E6, diode D3, diode D4, input end, OUT2 end, +48V voltage end, -48V voltage end, +12V voltage end, -12V voltage end, chip AD811, chip PB50;

[0018] The input end is connected with one end of the resistor R1, one end of the resistor R2, one end of the capacitor C6 and the pin 2 of the chip AD811, the pin 3 of the chip AD811 is grounded, the pin 4 of the chip AD811 is connected with a -12V voltage end and one end of the capacitor C1, the other end of the capacitor C1 is grounded, the pin 7 of the chip AD811 is connected with a +12V voltage end and one end of the capacitor C2, the other end of the capacitor C2 is grounded, the output end of the chip AD811 is connected with the pin 4 of the chip PB50, the pin 3 of the chip PB50 is connected with a +48V voltage end, one end of the capacitor C3, the positive pole of the capacitor E1, the positive pole of the capacitor E3 and the positive pole of the capacitor E4, the other end of the capacitor C3 is grounded, the negative pole of the capacitor E1 is connected with the negative pole of the capacitor E3 and the negative pole of the capacitor E4 and grounded, one end of the resistor R6 is connected with the pin 2 of the chip PB50, one end of the resistor R5 is connected with the pin 1 of the chip PB50, one end of the capacitor C5 is connected with the pin 8 of the chip PB50, one end of the resistor R4 is connected with the pin 7 of the chip PB50, the pin 5 of the chip PB50 is grounded, the pin 6 of the chip PB50 is connected with a -48V voltage end, the negative pole of the capacitor E4, one end of the capacitor C4, the negative pole of the capacitor E5 and the negative pole of the capacitor E6, the positive pole of the capacitor E4 is connected with the other end of the capacitor C4, the positive pole of the capacitor E5 and the positive pole of the capacitor E6, the other end of the resistor R6 is connected with the other end of the resistor R5, the other end of the resistor R4, the other end of the resistor R2 and one end of the resistor R3, the other end of the resistor R3 is connected with the other end of the capacitor C6, the other end of the capacitor C5 is connected with the positive pole of the diode D3, the negative pole of the diode D4 and the OUT2 end, the negative pole of the diode D3 is connected with a +48V voltage end, and the positive pole of the diode D4 is connected with a -48V voltage end.

[0019] As a further preferred scheme of the utility model discloses a kind of anti-data loss electroplating power supply communication module, the pulse width modulation circuit includes pulse signal generator, VCC, Vee, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R5, first potentiometer Rw1, second potentiometer Rw2, first capacitor C1, second capacitor C2, third capacitor C3, first diode VD1, second diode VD2, third diode VD3, first operational amplifier U1;

[0020] The positive terminal of the pulse signal generator is connected with the b terminal of the first potentiometer Rw1, one end of the first potentiometer Rw1 is connected with one end of the first resistor R1, the other end of the first resistor R1 is connected with the negative terminal of the pulse signal generator and grounded, the sliding terminal c of the first potentiometer Rw1 is connected with one end of the first capacitor C1, the other end of the first capacitor C1 is connected with the non-inverting input terminal of the first operational amplifier U1, one end of the third resistor R3 is connected with the non-inverting input terminal of the first operational amplifier U1, the other end of the third resistor R3 is connected with the negative voltage supply terminal VEE, the sliding terminal c and a terminal of the second potentiometer Rw2, the Vee terminal, one end of the third capacitor C3 and the negative power supply terminal of the first operational amplifier U1 respectively, the b terminal of the second potentiometer Rw2 is connected with one end of the second resistor R2 and the inverting input terminal of the first operational amplifier U1 respectively, the other end of the second resistor R2 is connected with the VCC terminal, one end of the second capacitor C2 and the positive power supply terminal of the first operational amplifier U1 respectively, the other end of the second capacitor C2 is grounded, the other end of the third capacitor C3 is connected with the anode terminal of the first diode VD1, one end of the fifth resistor R5 and grounded, the other end of the fourth resistor R4 is connected with the cathode terminal of the first diode VD1, the anode terminal of the second diode VD2 and the anode terminal of the third diode VD3 respectively, the cathode terminal of the second diode VD2 is connected with one end of the fifth resistor R5 and the uo1 terminal respectively, and the cathode terminal of the third diode VD3 is connected with one end of the fifth resistor R5 and the uo1 terminal respectively.

[0021] Compared with the prior art, the above technical scheme has the following technical effects:

[0022] The utility model discloses a kind of electroplating power supply communication modules of preventing data loss, including electroplating power module and communication module, the electroplating power module and communication module are connected;The communication module includes down-conversion circuit, filter amplification circuit, analog-digital conversion module, filter power amplification circuit, IF gain module, digital-analog conversion module, clock module, power module, serial peripheral interface, FPGA module, the electroplating power supply external power supply AC220V input, after rectification, soft start is carried out by thyristor soft start circuit, then filtering, the obtained direct current is converted into alternating current by half-bridge inverter, then rectification filtering is carried out again to obtain the required direct current, finally in pulse conversion part, according to the setting of user, output direct current or single pulse;After receiving the control signal generated by control center, drive circuit and pulse width modulation circuit drive corresponding switch tube to make main circuit start working, while, current detection circuit and output sampling circuit real-time feedback signal detected and collected to control center, control center compares feedback signal with user setting parameter, then adjusts output control signal, so dynamic adjustment is carried out, guaranteeing that circuit carries out output according to the parameter set by user. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings described in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0024] Figure 1 is a structure principle diagram of the electroplating power supply communication module of the present application;

[0025] Figure 2 is a structure principle diagram of the communication module of the present application;

[0026] Figure 3 is a structure principle diagram of the electroplating power supply module of the present application;

[0027] Figure 4 is a structure principle diagram of the FPGA module of the present application;

[0028] Figure 5 is a structure principle diagram of the control center of the present application;

[0029] Figure 6 is a circuit diagram of the high-stable crystal oscillator module of the present application;

[0030] Figure 7 is a circuit diagram of the half-bridge inverter module of the present application;

[0031] Figure 8 is a circuit diagram of the pulse width modulation circuit of the present application. DETAILED DESCRIPTION

[0032] The technical solutions of the present application will be further described in detail below in combination with the drawings:

[0033] The technical solutions of the embodiments of the present application will be clearly and completely described below in combination with the drawings of the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments of the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0034] An electroplating power supply communication module for preventing data loss, as shown in Figure 1 , comprises an electroplating power supply module and a communication module, and the electroplating power supply module and the communication module are connected.

[0035] As shown in Figure 2As shown, the communication module includes a down-conversion circuit, a filter amplification circuit, an analog-to-digital conversion module, a filter power amplification circuit, an IF gain module, a digital-to-analog conversion module, a clock module, a power module, a serial peripheral interface, an FPGA module, the analog-to-digital conversion module, the digital-to-analog conversion module, the clock module, the power module, and the serial peripheral interface are connected with the FPGA module respectively, the down-conversion circuit, the filter amplification circuit, and the analog-to-digital conversion module are connected in sequence, and the filter power amplification circuit, the IF gain module, and the digital-to-analog conversion module are connected in sequence.

[0036] As shown in the figure, Figure 3 As shown, the electroplating power supply module includes an external power supply AC220V, a rectifier module, a silicon-controlled soft start module, a filter module, a half-bridge inverter module, a rectifier filter module, a pulse conversion module, an output end, a current detection module, a drive circuit module, a sampling amplification module, an isolation feedback module, a pulse width modulation circuit, a control center, a drive circuit, a liquid crystal screen display module, and a button / knob input module; the output end of the external power supply AC220V is connected with the input end of the rectifier module, the output end of the rectifier module is connected with the input end of the silicon-controlled soft start module, the output end of the silicon-controlled soft start module is connected with the input end of the filter module, the output end of the filter module is connected with the input end of the half-bridge inverter module, the output end of the half-bridge inverter module is connected with the input end of the rectifier filter module, the output end of the rectifier filter module is connected with the input end of the pulse conversion module, and the output end of the pulse conversion module is connected with the output end; the output end of the filter module is also connected with the input end of the current detection module, the output end of the current detection module is connected with the input end of the pulse width modulation circuit, the output end of the pulse width modulation circuit is connected with the half-bridge inverter module through the drive circuit, the output end of the rectifier filter module is connected with the input end of the control center and the input end of the pulse width modulation circuit in sequence through the sampling amplification module and the isolation feedback module respectively, the output end of the button / knob input module is connected with the input end of the control center module, the output end of the control center is connected with the input end of the drive circuit, and the output end of the drive circuit is connected with the input end of the pulse conversion module.

[0037] As shown in the figure, Figure 4 As shown, the FPGA module includes a collection control unit, a data processing and RAM read-write module unit, a port control unit, a synchronous clock control unit, a command frame decoding unit, a FIFO data buffer unit, a Flash data storage control unit, and a data interpretation unit; the collection control unit, the port control unit, the synchronous clock control unit, the command frame decoding unit, the FIFO data buffer unit, the Flash data storage control unit, and the data interpretation unit are connected with the data processing and RAM read-write module unit respectively.

[0038] As shown in the figure, Figure 5As shown, the control center comprises a high-stable crystal oscillator module, an FPGA master control module, a USB transmission module, a serial port module, a data processing center, a USB interface, a gigabit network interface and an HDMI interface, the high-stable crystal oscillator module is connected with the FPGA master control module, the FPGA master control module is connected with the data processing center through the SB transmission module and the serial port module respectively, and the USB interface, the gigabit network interface and the HDMI interface are connected with the data processing center respectively.

[0039] The chip model of the USB transmission module is XY7C68013.

[0040] The utility model discloses a kind of electroplating power supply communication modules of preventing data loss, external power supply AC220V input, after rectification, soft start is carried out by thyristor soft start circuit, then filtering, the direct current obtained is converted into alternating current by half-bridge inverter, then rectification filtering is carried out again to obtain the required direct current, finally in pulse conversion part, according to the setting of user, output direct current or single pulse;After receiving the control signal generated by control center, drive circuit and pulse width modulation circuit drive corresponding switch tube to make main circuit start working, while, current detection circuit and output sampling circuit in real time feedback signal detected and collected to control center, control center compares feedback signal with user setting parameter, then adjusts output control signal, so dynamic adjustment is carried out, guarantee circuit according to the parameter set by user carries out output.

[0041] User observes liquid crystal screen, controls by knob, key, (with steady flow mode as example):

[0042] When using direct current mode, user sets corresponding current value as required, can output direct current waveform after starting.

[0043] When using pulse mode, user sets corresponding peak current, frequency, duty cycle as required, can output pulse waveform after starting.

[0044] In addition, user can also carry out programmable control to power supply in host computer through Modbus communication.

[0045] Preferably, the rectification module adopts half-wave rectification circuit.

[0046] The current detection module adopts Hall sensor.

[0047] As Figure 6As shown, the high-stable crystal oscillator module contains control chip 7N10.000MBP, capacitor C45, resistor R22, resistor R23, resistor R24, capacitor C69 and voltage VCC end, the 8 interface of control chip 7N10.000MBP is connected with one end of resistor R22, the other end of resistor R22 is connected with one end of capacitor C45, 9 interface of control chip 7N10.000MBP, one end of resistor R23 and voltage VCC end respectively, the other end of capacitor C45 is grounded, one end of resistor R23 is connected with one end of resistor R24, the other end of resistor R24 is grounded, one end of capacitor C69 is connected with 10 interface of control chip 7N10.000MBP, the other end of capacitor C69 is grounded.The high-stable crystal oscillator module of the utility model has good short-term stability of high-stable crystal oscillator, and establishes high-precision time reference.

[0048] As shown in the figure, Figure 7 As shown, the half-bridge inverter module contains resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, resistor R8, capacitor C1, capacitor C2, capacitor C3, capacitor C4, capacitor C5, capacitor C6, capacitor E1, capacitor E2, capacitor E3, capacitor E4, capacitor E5, capacitor E6, diode D3, diode D4, input end, OUT2 end, +48V voltage end, -48V voltage end, +12V voltage end, -12V voltage end, chip AD811, chip PB50;

[0049] Wherein, the input end is connected with one end of the resistor R1, the other end of the resistor R1 is connected with one end of the resistor R2, one end of the capacitor C6 and the pin 2 of the chip AD811 respectively, the pin 3 of the chip AD811 is grounded, the pin 4 of the chip AD811 is connected with the -12V voltage end and one end of the capacitor C1 respectively, the other end of the capacitor C1 is grounded, the pin 7 of the chip AD811 is connected with the +12V voltage end and one end of the capacitor C2 respectively, the other end of the capacitor C2 is grounded, the output end of the chip AD811 is connected with the pin 4 of the chip PB50, the pin 3 of the chip PB50 is connected with the +48V voltage end, one end of the capacitor C3, the positive pole of the capacitor E1, the positive pole of the capacitor E3 and the positive pole of the capacitor E4 respectively, the other end of the capacitor C3 is grounded, the negative pole of the capacitor E1 is connected with the negative pole of the capacitor E3 and the negative pole of the capacitor E4 and grounded, the pin 2 of the chip PB50 is connected with one end of the resistor R6, the pin 1 of the chip PB50 is connected with one end of the resistor R5, the pin 8 of the chip PB50 is connected with one end of the capacitor C5, the pin 7 of the chip PB50 is connected with one end of the resistor R4, the pin 5 of the chip PB50 is grounded, the pin 6 of the chip PB50 is connected with the -48V voltage end, the negative pole of the capacitor E4, one end of the capacitor C4, the negative pole of the capacitor E5, the negative pole of the capacitor E6 respectively, the positive pole of the capacitor E4 is connected with the other end of the capacitor C4, the positive pole of the capacitor E5 and the positive pole of the capacitor E6 respectively, the other end of the resistor R6 is connected with the other end of the resistor R5, the other end of the resistor R4, the other end of the resistor R2 and one end of the resistor R3 respectively, the other end of the resistor R3 is connected with the other end of the capacitor C6, the other end of the capacitor C5 is connected with the positive pole of the diode D3, the negative pole of the diode D4 and the OUT2 end respectively, the negative pole of the diode D3 is connected with the +48V voltage end, and the positive pole of the diode D4 is connected with the -48V voltage end.

[0050] The utility model discloses a half bridge inverter module, its metal shell appearance package, convenient integral installation on radiator, help long -term work in high -power output occasion, the working voltage of PB50 is positive and negative 30V to positive and negative 100V, can obtain continuous 2A's direct current output, has voltage and current gain, high voltage change rate, can reach, working frequency can reach 160KHz, and current precision can reach 12mA.

[0051] As Figure 8 The pulse width modulation circuit includes a pulse signal generator, a VCC, a Vee, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first potentiometer Rw1, a second potentiometer Rw2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first diode VD1, a second diode VD2, a third diode VD3, and a first operational amplifier U1.

[0052] The positive terminal of the pulse signal generator is connected with the b terminal of the first potentiometer Rw1, the a terminal of the first potentiometer Rw1 is connected with one end of the first resistor R1, the other end of the first resistor R1 is connected with the negative terminal of the pulse signal generator and grounded, the sliding terminal c of the first potentiometer Rw1 is connected with one end of the first capacitor C1, the other end of the first capacitor C1 is connected with the non-inverting input terminal of the first operational amplifier U1, the non-inverting input terminal of the first operational amplifier U1 is connected with one end of the third resistor R3, the other end of the third resistor R3 is connected with the negative voltage supply terminal VEE, the sliding terminal c terminal and the a terminal of the second potentiometer Rw2, the Vee terminal, one end of the third capacitor C3 and the negative power supply terminal of the first operational amplifier U1 respectively, the b terminal of the second potentiometer Rw2 is connected with one end of the second resistor R2 and the inverting input terminal of the first operational amplifier U1 respectively, the other end of the second resistor R2 is connected with the VCC terminal, one end of the second capacitor C2 and the positive power supply terminal of the first operational amplifier U1 respectively, the other end of the second capacitor C2 is grounded, the other end of the third capacitor C3 is connected with the anode terminal of the first diode VD1 and one end of the fifth resistor R5 and grounded, the other end of the fourth resistor R4 is connected with the cathode terminal of the first diode VD1, the anode terminal of the second diode VD2 and the anode terminal of the third diode VD3 respectively, the cathode terminal of the second diode VD2 is connected with one end of the fifth resistor R5 and the uo1 terminal respectively, and the cathode terminal of the third diode VD3 is connected with one end of the fifth resistor R5 and the uo1 terminal respectively.

[0053] The pulse signal to be processed is uin, the first potentiometer Rw1 and the first resistor R1 form a simple voltage dividing circuit, the resistance value of the first potentiometer Rw1 is adjusted to realize the preliminary adjustment of the pulse signal voltage; the second resistor R2 and the second potentiometer Rw2 are connected in series, the resistance value of the second potentiometer Rw2 is adjusted to change the voltage value of the inverting input terminal of the first operational amplifier U1, then the differential signal generated by the non-inverting terminal of the first operational amplifier U1 is compared, the pulse signal pulse width is adjusted, and the power supply voltage of the first operational amplifier U1 is adjusted to realize the further adjustment of the pulse signal voltage; the first capacitor C1, the second potentiometer Rw2, the second resistor R2, the third resistor R3 and the first operational amplifier U1 form a high-speed adjustable comparison differential circuit, the second capacitor R2 and the third capacitor R3 have the decoupling filtering effect, and the integrity of the power supply of the first operational amplifier U1 is ensured, and the high-frequency signal is processed stably and reliably.

[0054] As will be understood by one of ordinary skill in the art upon reading the present disclosure, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs unless otherwise defined. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0055] The above embodiments only illustrate the technical idea of the present application, and cannot limit the protection scope of the present application. Any modification made on the basis of the technical solutions according to the technical idea of the present application falls within the protection scope of the present application. The embodiments of the present application are described in detail above, but the present application is not limited to the above embodiments. Within the knowledge range of those skilled in the art, various changes can be made without departing from the purpose of the present application.

[0056] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A plating power supply communication module that prevents data loss, characterized by: The communication module comprises a frequency down-conversion circuit, a filter amplification circuit, an analog-to-digital conversion module, a filter power amplification circuit, an IF gain module, a digital-to-analog conversion module, a clock module, a power module, a serial peripheral interface, and an FPGA module, wherein the analog-to-digital conversion module, the digital-to-analog conversion module, the clock module, the power module, and the serial peripheral interface are connected with the FPGA module respectively, the frequency down-conversion circuit, the filter amplification circuit, and the analog-to-digital conversion module are connected in sequence, and the filter power amplification circuit, the IF gain module, and the digital-to-analog conversion module are connected in sequence. The plating power module comprises an external power supply AC220V, a rectifier module, a silicon-controlled soft start module, a filter module, a half-bridge inverter module, a rectifier filter module, a pulse conversion module, an output end, a current detection module, a driving circuit module, a sampling amplification module, an isolation feedback module, a pulse width modulation circuit, a control center, a driving circuit, a liquid crystal screen display module, and a button / knob input module, wherein the output end of the external power supply AC220V is connected with the input end of the rectifier module, the output end of the rectifier module is connected with the input end of the silicon-controlled soft start module, the output end of the silicon-controlled soft start module is connected with the input end of the filter module, the output end of the filter module is connected with the input end of the half-bridge inverter module, the output end of the half-bridge inverter module is connected with the input end of the rectifier filter module, the output end of the rectifier filter module is connected with the input end of the pulse conversion module, and the output end of the pulse conversion module is connected with the output end; the output end of the filter module is also connected with the input end of the current detection module, the output end of the current detection module is connected with the input end of the pulse width modulation circuit, the output end of the pulse width modulation circuit is connected with the half-bridge inverter module through the driving circuit, the output end of the rectifier filter module is connected with the input end of the control center and the input end of the pulse width modulation circuit in sequence through the sampling amplification module and the isolation feedback module respectively, the output end of the button / knob input module is connected with the input end of the control center module, the output end of the control center is connected with the input end of the driving circuit, and the output end of the driving circuit is connected with the input end of the pulse conversion module. The FPGA module comprises a collection control unit, a data processing and RAM read-write module unit, a port control unit, a synchronous clock control unit, a command frame decoding unit, a FIFO data buffer unit, a Flash data storage control unit, and a data interpretation unit, wherein the collection control unit, the port control unit, the synchronous clock control unit, the command frame decoding unit, the FIFO data buffer unit, the Flash data storage control unit, and the data interpretation unit are connected with the data processing and RAM read-write module unit respectively.

2. The plating power supply communication module of claim 1, wherein: ​ 3. The plating power supply communication module of claim 1, wherein: The control center comprises a high-stable crystal oscillator module, an FPGA master control module, a USB transmission module, a serial port module, a data processing center, a USB interface, a gigabit network interface and an HDMI interface, the high-stable crystal oscillator module is connected with the FPGA master control module, the FPGA master control module is connected with the data processing center through the SB transmission module and the serial port module respectively, and the USB interface, the gigabit network interface and the HDMI interface are connected with the data processing center respectively.

4. The plating power supply communication module of claim 3, wherein: The chip model of the USB transmission module is XY7C68013.

5. The plating power supply communication module of claim 3, wherein: The high-stable crystal oscillator module comprises a control chip 7N10.000MBP, a capacitor C45, a resistor R22, a resistor R23, a resistor R24, a capacitor C69 and a voltage VCC end, one end of the resistor R22 is connected with the 8 interface of the control chip 7N10.000MBP, the other end of the resistor R22 is connected with one end of the capacitor C45, the 9 interface of the control chip 7N10.000MBP, one end of the resistor R23 and the voltage VCC end respectively, the other end of the capacitor C45 is grounded, one end of the resistor R23 is connected with one end of the resistor R24, the other end of the resistor R24 is grounded, one end of the capacitor C69 is connected with the 10 interface of the control chip 7N10.000MBP, and the other end of the capacitor C69 is grounded.

6. The plating power supply communication module of claim 1, wherein: The half-bridge inverter module comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a resistor R8, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor E1, a capacitor E2, a capacitor E3, a capacitor E4, a capacitor E5, a capacitor E6, a diode D3, a diode D4, an input end, an OUT2 end, a +48V voltage end, a -48V voltage end, a +12V voltage end, a -12V voltage end, a chip AD811 and a chip PB50. The input end is connected with one end of the resistor R1, the other end of the resistor R1 is connected with one end of the resistor R2, one end of the capacitor C6 and the pin 2 of the chip AD811 respectively, the pin 3 of the chip AD811 is grounded, the pin 4 of the chip AD811 is connected with the -12V voltage end and one end of the capacitor C1 respectively, the other end of the capacitor C1 is grounded, the pin 7 of the chip AD811 is connected with the +12V voltage end and one end of the capacitor C2 respectively, the other end of the capacitor C2 is grounded, the output end of the chip AD811 is connected with the pin 4 of the chip PB50, the pin 3 of the chip PB50 is connected with the +48V voltage end, one end of the capacitor C3, the positive electrode of the capacitor E1, the positive electrode of the capacitor E3 and the positive electrode of the capacitor E4 respectively, the other end of the capacitor C3 is grounded, the negative electrode of the capacitor E1 is connected with the negative electrode of the capacitor E3 and the negative electrode of the capacitor E4 respectively and grounded, one end of the resistor R6 is connected with the pin 2 of the chip PB50, one end of the resistor R5 is connected with the pin 1 of the chip PB50, one end of the capacitor C5 is connected with the pin 8 of the chip PB50, one end of the resistor R4 is connected with the pin 7 of the chip PB50, the pin 5 of the chip PB50 is grounded, the pin 6 of the chip PB50 is connected with the -48V voltage end, the negative electrode of the capacitor E4, one end of the capacitor C4, the negative electrode of the capacitor E5 and the negative electrode of the capacitor E6 respectively, the positive electrode of the capacitor E4 is connected with the other end of the capacitor C4, the positive electrode of the capacitor E5 and the positive electrode of the capacitor E6 respectively, the other end of the resistor R6 is connected with the other end of the resistor R5, the other end of the resistor R4, the other end of the resistor R2 and one end of the resistor R3 respectively, the other end of the resistor R3 is connected with the other end of the capacitor C6, the other end of the capacitor C5 is connected with the positive electrode of the diode D3, the negative electrode of the diode D4 and the OUT2 end respectively, the negative electrode of the diode D3 is connected with the +48V voltage end, and the positive electrode of the diode D4 is connected with the -48V voltage end.

7. The plating power supply communication module of claim 1, wherein: The pulse width modulation circuit comprises a pulse signal generator, a VCC, a Vee, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first potentiometer Rw1, a second potentiometer Rw2, a first capacitor C1, a second capacitor C2, a third capacitor C3, a first diode VD1, a second diode VD2, a third diode VD3, a first operational amplifier U1; The positive terminal of the pulse signal generator is connected to the b terminal of the first potentiometer Rw1, one end of the first potentiometer Rw1 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to the negative terminal of the pulse signal generator and grounded, the sliding terminal c of the first potentiometer Rw1 is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is connected to the non-inverting input terminal of the first operational amplifier U1, one end of the third resistor R3 is connected to the non-inverting input terminal of the first operational amplifier U1, the other end of the third resistor R3 is connected to the negative voltage supply terminal VEE, the sliding terminal c and a terminal of the second potentiometer Rw2, the Vee terminal, one end of the third capacitor C3 and the negative power supply terminal of the first operational amplifier U1, respectively, the b terminal of the second potentiometer Rw2 is connected to one end of the second resistor R2 and the inverting input terminal of the first operational amplifier U1, respectively, the other end of the second resistor R2 is connected to the VCC terminal, one end of the second capacitor C2 and the positive power supply terminal of the first operational amplifier U1, respectively, the other end of the second capacitor C2 is grounded, the other end of the third capacitor C3 is connected to the anode terminal of the first diode VD1, one end of the fifth resistor R5 and grounded, the other end of the fourth resistor R4 is connected to the cathode terminal of the first diode VD1, the anode terminal of the second diode VD2 and the anode terminal of the third diode VD3, respectively, the cathode terminal of the second diode VD2 is connected to one end of the fifth resistor R5 and the uo1 terminal, respectively, the cathode terminal of the third diode VD3 is connected to one end of the fifth resistor R5 and the uo1 terminal, respectively.

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