Straight-through prevention protection circuit

Abstract

The utility model discloses an anti-straight-through protection circuit, which relates to the technical field of protection circuits and comprises a first logic gate, a second logic gate, a third logic gate, a triode, a resistor R1, a resistor R2, a resistor R3 and a resistor R4. The three logic gates are OR gates or NOR gates; first input ends of the first logic gate and the second logic gate are respectively grounded through resistors R1 and R2, second input ends of the first logic gate and the second logic gate are respectively connected with two input ends of the third logic gate, and output ends of the first logic gate and the second logic gate are respectively connected with a first driving end and a second driving end; the output end of the third logic gate is connected with a resistor R3 and then is fed back to the input end a1 of the first logic gate connected with the resistor R1 through a triode, and the second logic gate connected with the input end a2 of the resistor R2; one end of the resistor R4 is connected with a power supply, and the other end is connected with a common node between the resistor R3 and the triode. According to the utility model, drive signal hardware interlocking can be realized, the influence on drive signal transmission is small, and the circuit structure is simple.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of protection circuit, in particular to a kind of protection circuit of anti straight-through. BACKGROUND

[0002] Power electronic devices are widely used in automobile, energy storage and other industries, and the current mainstream power module is mainly half-bridge module or full-bridge module. The power electronic devices (also known as power devices) used in the power module need to be matched with corresponding driving signals and driving circuits to work normally. During the operation of the power module, the upper and lower tubes need to be alternately turned on. Since there is usually a certain delay in the turn-on and turn-off of the power electronic devices, there is a possibility that the upper and lower tubes are turned on at the same time, which can cause a short circuit at the power end and damage the power device.

[0003] Currently, the methods to solve the above problems mainly fall into two categories. The first category is to set a dead time for upper and lower tube lockout protection in software, and to realize signal interlocking through dead time management control to prevent the same bridge arm power device from being straight-through. The second category is to process the driving signal through some circuit design from the hardware perspective to achieve anti-straight-through, such as the utility model patent with publication number CN216751525U and the name "a power module anti-straight-through protection circuit", which uses an OR gate + an OR gate + a three-state gate logic circuit to process the driving signal and constitutes an anti-straight-through protection circuit. The utility model patent with publication number CN209151038U and the patent name "a DC brushless motor driver interlocking circuit to prevent bridge arm straight-through" uses a NOT gate + a NAND gate logic circuit to process the driving signal and constitutes an anti-straight-through protection circuit. As can be seen from the two patents, the second category of methods generally uses a 2-3 stage gate circuit to form a logic circuit to process the driving signal and constitutes an anti-straight-through protection circuit. The use of multiple stage gate circuits increases the driving signal load, and the increase in the number of gate circuits also makes the overall circuit structure complex, increases the cost and failure rate. In addition, the driving signal of the logic circuit in the prior art is either high or low, and cannot satisfy the interlocking of high / low level driving signal without changing the circuit design, which has low compatibility.

[0004] Therefore, for the second category of methods, a new anti-straight-through protection circuit with simple structure and high compatibility is needed to be provided without changing the circuit design to solve the above technical problems. UTILITY MODEL CONTENT

[0005] The utility model aims to provide an anti-straight-through protection circuit to realize driving signal interlocking. Without changing the circuit design, a driving interlocking circuit compatible with high / low level driving signal is provided to improve the compatibility of the anti-straight-through protection circuit and simplify the circuit structure.

[0006] To achieve the above-mentioned purpose, the utility model provides the following scheme:

[0007] The anti-through protection circuit comprises a first logic gate, a second logic gate, a third logic gate, a transistor and resistors R1, R2, R3 and R4.

[0008] The first input end of the first logic gate and the first input end of the second logic gate are grounded through resistors R1 and R2 respectively, the second input end of the first logic gate and the second input end of the second logic gate are connected to two input ends of the third logic gate, the output end of the first logic gate is connected to a first driving end, the output end of the second logic gate is connected to a second driving end, the output end of the third logic gate is connected to the resistor R3, and then the output end of the third logic gate is fed back to the input end a1 of the resistor R1 connected to the first logic gate and the input end a2 of the resistor R2 connected to the second logic gate through the transistor, one end of the resistor R4 is connected to a power supply, and the other end of the resistor R4 is connected to a common node between the resistor R3 and the transistor, and the emitter of the transistor is connected to the power supply.

[0009] When the first logic gate, the second logic gate and the third logic gate are all or gates, the driving signal is low-level effective, at this time, the transistor is a PNP transistor, and when the first logic gate, the second logic gate and the third logic gate are all NAND gates, the driving signal is high-level effective, at this time, the transistor is an NPN transistor.

[0010] Further, the first logic gate, the second logic gate and the third logic gate are three logic gates in the same chip.

[0011] According to the specific embodiment provided by the utility model, the utility model discloses the following technical effects: the anti-through protection circuit provided by the utility model can realize the hardware interlocking of the driving signal by using one level or gate / NAND gate circuit (selecting according to the driving signal level) and a PNP / NPN transistor, the circuit structure is simple and clear, thereby avoiding the problem of complex circuit structure caused by adopting 2-3 level gate circuit to constitute the anti-through protection circuit in the prior art. Since the number of gate circuits used in the one-level architecture of the utility model is small, the cost and the failure rate of the logic circuit part can be reduced, and the reliability of the driving signal can be ensured. In addition, the logic circuit provided by the utility model can realize the interlocking of the high / low level of the driving signal by only changing the gate circuit chip and the transistor without changing the circuit design, and the circuit compatibility is high. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0013] Fig. 1 The schematic diagram of the logic circuit when the driving signal is low level effective for the embodiment 1 of the present application;

[0014] Fig. 2 The schematic diagram of the logic circuit when the driving signal is high level effective for the embodiment 2 of the present application. DETAILED DESCRIPTION

[0015] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0016] The purpose of the present application is to provide a kind of anti straight-through protection circuit, on the basis of not changing circuit design, realize driving signal interlock, and reduce the influence to driving signal, and improve the compatibility of the anti straight-through circuit, simplify circuit structure.

[0017] In order to make the above purposes, characteristics and advantages of the present application more apparent and easy to understand, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0018] As Figs. 1-2 As shown in the present application, a kind of or gate / or not gate (select according to driving signal level)+1 PNP / NPN triode architecture logic circuit is provided.When driving signal is low level effective, or gate is used, when driving signal is high level effective, or not gate is used. In the above-mentioned architecture, to realize the interlock of upper and lower tube driving signals of one bridge arm, three or gates / or not gates are needed, and there are mature chips with four or gates / or not gates inside at present, so one chip can meet the above requirements.

[0019] The anti straight-through protection circuit provided in the embodiment includes first logic gate, second logic gate, third logic gate, triode and resistors R1, R2, R3, R4;The first logic gate, the second logic gate, the third logic gate are the same kind of logic gate, and are or gate or or not gate;

[0020] The first input end of the first logic gate and the first input end of the second logic gate are connected to ground through resistors R1 and R2 respectively, the second input end of the first logic gate and the second input end of the second logic gate are connected to two input ends of the third logic gate respectively, the output end of the first logic gate is connected to the first driving end, the output end of the second logic gate is connected to the second driving end; the output end of the third logic gate is connected to the resistor R3, and then fed back to the input end a1 of the resistor R1 connected to the first logic gate and the input end a2 of the resistor R2 connected to the second logic gate through a transistor; one end of the resistor R4 is connected to the power supply, and the other end is connected to the common node between the resistor R3 and the transistor; the emitter of the transistor is connected to the power supply.

[0021] Embodiment 1

[0022] When the first logic gate, the second logic gate and the third logic gate are all OR gates, the driving signal is low level effective, at this time, the transistor is a PNP type transistor.

[0023] As Fig. 1The schematic diagram of the logic circuit is shown when the driving signal is low level effective, wherein the or gate N1, the or gate N2 and the or gate N3 are three or gates integrated in the same chip. The logic circuit is composed of three or gates N1, N2, N3, a PNP transistor and resistors R1, R2, R3 and R4. Two driving signals A1 and A2 of the upper and lower tubes in the same bridge arm are respectively connected to one input end of the or gates N1 and N2, and the other input end of the or gates N1 and N2 is respectively connected to the ground through resistors R1 and R2, and DRV1 and DRV2 are the output signals of the logic circuit through the two driving signals. The inputs of the or gate N3 are respectively connected to the two driving signals A1 and A2, and the output end of the or gate N3 is connected to the resistor R3, and then fed back to the input ends a1 and a2 of the or gates N1 and N2 through the PNP transistor Q1. The level logic of the A1 and A2 signals will affect the output level logic of the or gate N3, thereby controlling the on-off of the transistor Q1, and the on-off of the NPN transistor Q1 will affect the level logic at the input ends a1 and a2 of the or gates N1 and N2. For example, when A1 is 0 (low level) and A2 is 1 (high level), the output of the or gate N3 is 1 (high level), the PNP transistor Q1 is not conductive, and a1 and a2 are 0 (low level). At this time, the level state of the output signals DRV1 and DRV2 is only related to the state of A1 and A2, that is, DRV1 is 0 (low level) and DRV2 is 1 (high level), and the driving signal is normally transmitted. Conversely, when A1 is 1 (high level) and A2 is 0 (low level), the outputs of the or gates N1 and N2 are DRV1 is 1 (high level) and DRV2 is 0 (low level), and the driving signal is normally transmitted. When A1 is 0 (low level) and A2 is also 0 (low level), that is, the driving signal is simultaneously conductive for the upper and lower tubes, at this time, the output of the or gate N3 is 0 (low level), the PNP transistor Q1 is conductive, the level of a1 and a2 is pulled up to 1 (high level), and the output signals DRV1 and DRV2 of the or gates N1 and N2 are both 1 (high level), and the driving output signal is closed, thereby preventing the upper and lower tubes from being directly connected. The truth table of the above logic circuit is as follows:

[0024]

[0025]

[0026] Example 2

[0027] When the first logic gate, the second logic gate and the third logic gate are all nor gates, the driving signal is high level effective, at this time, the transistor is an NPN type transistor.

[0028] As Fig. 2 shown, when the driving signal is high level effective, the principle of the logic circuit is as follows:

[0029] The logic circuit is composed of three NOR gates N4, N5, N6, an NPN transistor and resistors R1, R2, R3 and R4.

[0030] When A1 is 0 (low level) and A2 is 1 (high level), the output of NOR gate N6 is 0 (low level), NPN transistor Q2 is not turned on, a1 and a2 are 0 (low level), and the level state of the output driving signals DRV1 and DRV2 is: DRV1 is 1 (high level) and DRV2 is 0 (low level), and the driving signals are normally transmitted. Conversely, when A1 is 1 (high level) and A2 is 0 (low level), NPN transistor Q2 is not turned on, a1 and a2 are 0 (low level), the output of NOR gates N4 and N5 is DRV1 is 0 (low level) and DRV2 is 1 (high level), and the driving signals are normally transmitted. When A1 is 1 (high level) and A2 is also 1 (high level), i.e. the driving signals are simultaneously turned on, the output of NOR gate N6 is 0 (low level), NPN transistor Q2 is not turned on, a1 and a2 are 0 (low level), the output signals DRV1 and DRV2 of NOR gates N4 and N5 are both 0 (low level), and the driving output signals are blocked, thereby preventing the straight-through of the upper and lower tubes. The truth table of the logic circuit is as follows:

[0031]

[0032] The anti-straight-through protection circuit can realize hardware interlocking of the driving signals, prevent the straight-through of the bridge arm caused by the failure of software interlocking due to improper setting of the dead time or unstable software running, and damage the power device, and the utility model provides a kind of secondary protection for guaranteeing reliable driving signals.

[0033] In summary, the anti-straight-through protection circuit provided by the utility model only needs an OR gate / NOR gate (selected according to the driving signal level) plus a PNP / NPN transistor, which can simplify the circuit to realize signal interlocking. Moreover, the OR gate and NOR gate provided by the utility model can be mature chips, which can be pin compatible, and the PNP and NPN transistors can also be pin compatible. The logic circuit provided by the utility model can realize the interlocking of high / low levels of driving signals by only changing the gate circuit chip and the transistor without changing the circuit design, i.e. the driving signal interlocking can be realized regardless of whether the driving signal is low level effective or high level effective (the circuit design is not changed, only the chip is welded), and the circuit is simple, which can improve the compatibility of the anti-straight-through circuit.

[0034] The remaining technical features in the embodiment can be flexibly selected by those skilled in the art according to actual conditions to meet different specific actual needs. However, it is obvious to those skilled in the art that the specific details do not have to be used to implement the present application. In other examples, in order to avoid confusion of the present application, well-known components, structures or parts are not specifically described, and are within the technical scope defined in the claims of the present application.

[0035] Changes and variations made by those skilled in the art without departing from the spirit and scope of the present application shall be within the scope of protection of the appended claims of the present application. In the above description, a large number of specific details are set forth in order to provide a thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application does not have to be implemented with these specific details. In other examples, in order to avoid confusion of the present application, well-known technologies, such as specific construction details, operating conditions and other technical conditions, are not specifically described.

[0036] The principles and implementation modes of the present application are described by applying specific examples in this paper, and the above embodiment description is only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in specific implementation modes and application scope. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. An anti-pass-through protection circuit, characterized by comprising: The application relates to a drive circuit, which comprises a first logic gate, a second logic gate, a third logic gate, a transistor and resistors R1, R2, R3 and R4; the first logic gate, the second logic gate and the third logic gate are the same kind of logic gate and are or gates or nor gates; The first input end of the first logic gate and the first input end of the second logic gate are grounded through resistors R1 and R2 respectively, the second input end of the first logic gate and the second input end of the second logic gate are connected to two input ends of the third logic gate, the output end of the first logic gate is connected to a first driving end, the output end of the second logic gate is connected to a second driving end; the output end of the third logic gate is connected to the resistor R3 and then fed back to the input end a1 of the resistor R1 connected to the first logic gate and the input end a2 of the resistor R2 connected to the second logic gate through the transistor; one end of the resistor R4 is connected to a power supply and the other end is connected to a common node between the resistor R3 and the transistor; the emitter of the transistor is connected to the power supply; When the first logic gate, the second logic gate and the third logic gate are or gates, the driving signal is low-level effective, at this time, the transistor is a PNP type transistor; when the first logic gate, the second logic gate and the third logic gate are nor gates, the driving signal is high-level effective, at this time, the transistor is an NPN type transistor.

2. The anti-shunt protection circuit of claim 1, wherein, The first logic gate, the second logic gate and the third logic gate are three logic gates in the same chip.

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