Single-phase three-interlaced SEPIC circuit

Abstract

The utility model belongs to the technical field of circuits, and discloses a single-phase three-interlaced SEPIC circuit, which comprises a port ACL and a port ACN, the port ACL is connected with the positive end of a diode D101 and the negative end of a diode D103, the port ACN is connected with the positive end of the diode D103 and the negative end of a diode D104, the positive end of the diode D102 and the positive end of the diode D104 are connected with a port GND, and the negative end of the diode D104 is connected with the port ACL. The negative end of the diode D101 and the negative end of the diode D103 are connected with one end of a capacitor C110, and the other end of the capacitor C110 is connected with a port GND. The utility model has the beneficial effects of stable structure, adjustable output voltage, less input current ripple, less output switch ripple, simple structure, isolability, difficult damage, no need of considering the input and output voltage of the pfc, lifting function, and wide application in the aspect of switching power supply.

Description

TECHNICAL FIELD

[0001] The utility model relates to circuit technical field especially relates to a single -phase three staggered SEPIC circuit. BACKGROUND

[0002] In switching power supply, PFC converter has wide application, and the main role of PFC circuit in switching power supply is to improve power factor, reduce harmonic content, solve electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems caused by serious distortion of current waveform due to capacitive load, typical topology has Boost, flyback, buck etc., the mainstream pfc circuit on the market is mainly boost circuit and its derivative topology, the main defect of single -phase Boost is that input voltage cannot be lower than output voltage, and output and input are not isolated, and use is limited.

[0003] Therefore, it is necessary to provide a single -phase three staggered SEPIC circuit, which can consider the input and output voltage of the pfc, and has the functions of ascending and descending, simple structure, small input and output current ripple and self-isolation. UTILITY MODEL CONTENT

[0004] The utility model discloses a single -phase three staggered SEPIC circuit relates to power electronics technical field, and in switching power supply aspect can be widely applied, it can effectively solve the technical problem in background art.

[0005] To achieve the above object, the technical scheme of the utility model is as follows:

[0006] A single -phase three staggered SEPIC circuit, including port AC_L and port AC_N, the positive terminal of diode D101 and the negative terminal of diode D103 are connected with port AC_L, the positive terminal of diode D103 and the negative terminal of diode D104 are connected with port AC_N, the positive terminal of diode D102 and the positive terminal of diode D104 are connected with port GND, the negative terminal of diode D101 and the negative terminal of diode D103 are connected with one end of capacitor C110, the other end of capacitor C110 is connected with port GND;

[0007] One end of capacitor C110 is connected with one end of inductor L3, the other end of inductor L3 is connected with the drain of MOS tube Q3 and one end of capacitor C3, the other end of capacitor C3 is connected with the pin 1 of transformer T3, the source of MOS tube Q3 is connected with the pin 2 of transformer T3 and port GND, the pin 3 of transformer T3 is connected with one end of capacitor C10 and port AGND, the pin 4 of transformer T3 is connected with the positive terminal of diode D3, the negative terminal of diode D3 is connected with the other end of capacitor C10;

[0008] One end of the capacitor C110 is connected with one end of the inductor L1, the other end of the inductor L1 is connected with the drain of the MOS tube Q1 and one end of the capacitor C1, the other end of the capacitor C1 is connected with the pin 1 of the transformer T1, the source of the MOS tube Q1 is connected with the pin 2 of the transformer T1 and the port GND, the pin 3 of the transformer T1 is connected with one end of the capacitor C10 and the port AGND, the pin 4 of the transformer T1 is connected with the positive end of the diode D1, the negative end of the diode D1 is connected with the other end of the capacitor C10;

[0009] One end of the capacitor C110 is connected with one end of the inductor L2, the other end of the inductor L2 is connected with the drain of the MOS tube Q2 and one end of the capacitor C2, the other end of the capacitor C2 is connected with the pin 1 of the transformer T2, the source of the MOS tube Q2 is connected with the pin 2 of the transformer T2 and the port GND, the pin 3 of the transformer T2 is connected with one end of the capacitor C10 and the port AGND, the pin 4 of the transformer T2 is connected with the positive end of the diode D2, the negative end of the diode D2 is connected with the other end of the capacitor C10.

[0010] As a preferred improvement of the utility model: the port AC_L and the port AC_N connect commercial power.

[0011] As a preferred improvement of the utility model: the two ends of the capacitor C10 connect load.

[0012] As a preferred improvement of the utility model: the gate of the MOS tube Q3 is connected with one end of the resistance R103, one end of the capacitor C103 and the port PWMA, the other end of the resistance R103 is connected with the other end of the capacitor C103, the port GND and the source of the MOS tube Q3, and the port PWMA is connected with MCU.

[0013] As a preferred improvement of the utility model: the gate of the MOS tube Q1 is connected with one end of the resistance R101, one end of the capacitor C101 and the port PWMB, the other end of the resistance R101 is connected with the other end of the capacitor C101, the port GND and the source of the MOS tube Q1, and the port PWMB is connected with MCU.

[0014] As a preferred improvement of the utility model: the gate of the MOS tube Q2 is connected with one end of the resistance R102, one end of the capacitor C102 and the port PWMC, the other end of the resistance R102 is connected with the other end of the capacitor C102, the port GND and the source of the MOS tube Q2, and the port PWMC is connected with MCU.

[0015] As a preferred improvement of the utility model: the MOS tube Q1, the MOS tube Q2 and the MOS tube Q3 work 120 degrees out of phase.

[0016] The utility model discloses the beneficial effect is as follows:

[0017] Stable structure, output voltage can adjust, input current ripple is few simultaneously, output switch ripple reduces, simple structure, can isolate, not easy to damage, can not need to consider the input and output voltage of pfc, and possess the function of lifting and lowering, can be widely used in switching power supply aspect. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical scheme in the utility model embodiment, the following will be to the embodiment description needed to use the drawing briefly introduced, obviously, the following description in the drawing is only some embodiments of the utility model, for ordinary skilled person in the art comes, under the premise of not paying creative labor, can also obtain other drawings according to these drawings, wherein:

[0019] Figure 1 It is a schematic diagram of a single-phase three-interleaved SEPIC circuit. DETAILED DESCRIPTION

[0020] The technical scheme in the utility model embodiment will be described clearly and completely below, obviously, the described embodiment is only a part of the embodiment of the utility model, not all the embodiment. Based on the embodiment in the present application, all other embodiments obtained by ordinary skilled person in the art without making creative labor are within the scope of the present application.

[0021] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative positional relationship, movement condition, etc. between components in a certain specific posture (as shown in the drawings), and if the specific posture changes, the directional indications will also change accordingly.

[0022] In addition, in the present application, the description such as "first", "second" and the like is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0023] In the present application, unless otherwise explicitly specified and limited, the terms "connection", "fixation" and the like should be understood broadly, for example, "fixation" can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be direct connection, or indirect connection through intermediate medium, can be internal communication of two elements or interaction relationship of two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0024] In addition, the technical solutions among various embodiments of the present application can be combined with each other, but it must be based on the fact that a person skilled in the art can realize it, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor is it within the protection scope required by the present application.

[0025] Please refer to Figure 1 As shown in the drawings, the utility model provides a single -phase three staggered SEPIC circuit, including port AC_L and port AC_N, port AC_L and port AC_N connect commercial power or other power supply, port AC_L connects the positive end of diode D101 and the negative end of diode D103, port AC_N connects the positive end of diode D103 and the negative end of diode D104, the positive end of diode D102 and the positive end of diode D104 connect port GND, the negative end of diode D101 and the negative end of diode D103 connect one end of capacitor C110, the other end of capacitor C110 connects port GND.

[0026] One end of capacitor C110 connects one end of inductance L3, the other end of inductance L3 connects the drain of MOS tube Q3 and one end of capacitor C3, the other end of capacitor C3 connects the pin 1 of transformer T3, the source of MOS tube Q3 connects the pin 2 of transformer T3 and port GND, the pin 3 of transformer T3 connects one end of capacitor C10 and port AGND, the pin 4 of transformer T3 connects the positive end of diode D3, the negative end of diode D3 connects the other end of capacitor C10, the gate of MOS tube Q3 connects one end of resistance R103, one end of capacitor C103 and port PWMA, the other end of resistance R103 connects the other end of capacitor C103, port GND and the source of MOS tube Q3, port PWMA connects MCU, both ends of capacitor C10 connect load or battery.

[0027] One end of the capacitor C110 is connected to one end of the inductor L1, the other end of the inductor L1 is connected to the drain of the MOS tube Q1 and one end of the capacitor C1, the other end of the capacitor C1 is connected to the pin 1 of the transformer T1, the source of the MOS tube Q1 is connected to the pin 2 of the transformer T1 and the port GND, the pin 3 of the transformer T1 is connected to one end of the capacitor C10 and the port AGND, the pin 4 of the transformer T1 is connected to the positive end of the diode D1, the negative end of the diode D1 is connected to the other end of the capacitor C10, the gate of the MOS tube Q1 is connected to one end of the resistor R101, one end of the capacitor C101 and the port PWMB, the other end of the resistor R101 is connected to the other end of the capacitor C101, the port GND and the source of the MOS tube Q1, and the port PWMB is connected to the MCU.

[0028] One end of the capacitor C110 is connected to one end of the inductor L1, the other end of the inductor L1 is connected to the drain of the MOS tube Q1 and one end of the capacitor C1, the other end of the capacitor C1 is connected to the pin 1 of the transformer T1, the source of the MOS tube Q1 is connected to the pin 2 of the transformer T1 and the port GND, the pin 3 of the transformer T1 is connected to one end of the capacitor C10 and the port AGND, the pin 4 of the transformer T1 is connected to the positive end of the diode D1, the negative end of the diode D1 is connected to the other end of the capacitor C10, the gate of the MOS tube Q1 is connected to one end of the resistor R101, one end of the capacitor C101 and the port PWMB, the other end of the resistor R101 is connected to the other end of the capacitor C101, the port GND and the source of the MOS tube Q1, and the port PWMB is connected to the MCU.

[0029] Working principle:

[0030] The circuit is composed of D3, C3, L3 and Q3.

[0031] When Q3 is just closed, the input AC stores energy in L3, C3 charges the primary excitation inductance of T3 through Q3, D3 is reversed biased, and the load energy is provided by the output capacitor.

[0032] When Q3 is off, L3 and T3 transmit energy to the secondary load, and also charge C3, and the excitation inductance of the primary side of T3 also transmits energy to the secondary load through T3.

[0033] Three groups of SEPIC circuits work 120 degrees out of phase, and the working principle is the same as that of a single circuit.

[0034] The input inductor in the figure is a coupled inductor, and can also be an uncoupled inductor. The device for switching in the figure is a SiC MOSFET, and the device for the secondary semiconductor is SiC. The transformer in the figure is used as a transformer, and the primary excitation inductor is also used as a common inductor to reset the intermediate capacitor. It should be further explained that other components can be used to achieve the above effects, which should be within the inventive concept of the utility model, and should be within the protection scope of the utility model.

[0035] The circuit structure is stable, the output voltage can be adjusted, the input current ripple is small, the output switch ripple is reduced, the structure is simple, the circuit can be isolated and is not easy to be damaged, the input and output voltages do not need to be considered, the circuit has the functions of rising and falling, and can be widely applied in switching power supplies.

[0036] Although the embodiments of the utility model have been disclosed as above, it is not limited to the application listed in the specification and the embodiments, and can be fully applied to various fields suitable for the utility model. For those skilled in the art, other modifications can be easily realized, and therefore the utility model is not limited to specific details and the figures shown and described herein, without departing from the general concept defined by the claims and the equivalent scope.

Claims

1. A single phase triple interleaved SEPIC circuit characterized by: The port AC_L connects the positive end of diode D101 and the negative end of diode D103, the port AC_N connects the positive end of diode D103 and the negative end of diode D104, the positive end of diode D102 and the positive end of diode D104 connect the port GND, one end of the capacitor C110 connects the negative end of diode D101 and the negative end of diode D103, the other end of the capacitor C110 connects the port GND; One end of the capacitor C110 connects one end of the inductor L3, the other end of the inductor L3 connects the drain of MOS tube Q3 and one end of the capacitor C3, the other end of the capacitor C3 connects the pin 1 of transformer T3, the source of the MOS tube Q3 connects the pin 2 of the transformer T3 and the port GND, the pin 3 of the transformer T3 connects one end of the capacitor C10 and the port AGND, the pin 4 of the transformer T3 connects the positive end of diode D3, the negative end of diode D3 connects the other end of the capacitor C10; One end of the capacitor C110 connects one end of the inductor L1, the other end of the inductor L1 connects the drain of MOS tube Q1 and one end of the capacitor C1, the other end of the capacitor C1 connects the pin 1 of transformer T1, the source of the MOS tube Q1 connects the pin 2 of the transformer T1 and the port GND, the pin 3 of the transformer T1 connects one end of the capacitor C10 and the port AGND, the pin 4 of the transformer T1 connects the positive end of diode D1, the negative end of diode D1 connects the other end of the capacitor C10; One end of the capacitor C110 connects one end of the inductor L2, the other end of the inductor L2 connects the drain of MOS tube Q2 and one end of the capacitor C2, the other end of the capacitor C2 connects the pin 1 of transformer T2, the source of the MOS tube Q2 connects the pin 2 of the transformer T2 and the port GND, the pin 3 of the transformer T2 connects one end of the capacitor C10 and the port AGND, the pin 4 of the transformer T2 connects the positive end of diode D2, the negative end of diode D2 connects the other end of the capacitor C10.

2. A single phase three interleaved SEPIC circuit as claimed in claim 1 characterized in that: The port AC_L and the port AC_N connect the commercial power.

3. A single phase three interleaved SEPIC circuit as claimed in claim 1 characterized in that: The two ends of the capacitor C10 connect the load.

4. A single phase triple interleaved SEPIC circuit as claimed in claim 1 characterized in that: The gate of the MOS tube Q3 connects one end of the resistor R103, one end of the capacitor C103 and the port PWMA, the other end of the resistor R103 connects the other end of the capacitor C103, the port GND and the source of the MOS tube Q3, the port PWMA connects the MCU.

5. A single phase triple interleaved SEPIC circuit as claimed in claim 1 characterized in that: The gate of the MOS tube Q1 connects one end of the resistor R101, one end of the capacitor C101 and the port PWMB, the other end of the resistor R101 connects the other end of the capacitor C101, the port GND and the source of the MOS tube Q1, the port PWMB connects the MCU.

6. A single phase triple interleaved SEPIC circuit as claimed in claim 1 characterized in that: One end of a resistor R102, one end of a capacitor C102 and a port PWMC are connected to a gate of the MOS transistor Q2, the other end of the resistor R102 is connected to the other end of the capacitor C102, a port GND and a source of the MOS transistor Q2, and the port PWMC is connected to an MCU.

7. A single phase triple interleaved SEPIC circuit as claimed in claim 1 characterized by: The MOS transistor Q1, the MOS transistor Q2 and the MOS transistor Q3 work in a phase difference of 120 degrees.

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