Discrete time integrator

Abstract

The utility model provides a discrete time integrator which comprises an operational amplifier. The operational amplifier comprises a first differential operational amplification circuit, a second differential operational amplification circuit and a second switch combination, the first differential operational amplification circuit is connected between the power supply end and the grounding end, and the second switch combination enables the second differential operational amplification circuit to be connected between the power supply end and the grounding end in a controlled mode. In the integration period, the second switch combination is switched on, so that the second differential operation amplification circuit is connected between the power supply end and the grounding end, and in the sampling period, the second switch combination is switched off, so that the second differential operation amplification circuit is disconnected from the power supply end and the grounding end. This can significantly reduce the power consumption of the discrete time integrator.

Description

TECHNICAL FIELD

[0001] The utility model relates to integrator field especially relates to a discrete time integrator. BACKGROUND

[0002] The discrete time integrator of prior art, in the two periods of sampling period and integration period, the power consumption is always changeless.

[0003] In addition, the traditional dynamic bias circuit is easy to lead to the floating of common mode voltage and the circuit asymmetry.

[0004] Therefore, a new technical scheme is urgently needed to solve the above problems. UTILITY MODEL CONTENTS

[0005] One of the purposes of the utility model is to provide a discrete time integrator, which has lower power consumption.

[0006] According to one aspect of the utility model, the utility model provides a discrete time integrator, which comprises: an operational amplifier, including a first differential operational amplifier circuit, a second differential operational amplifier circuit and a second switch combination, wherein the first differential operational amplifier circuit is connected between a power supply end and a ground end, the second switch combination connects the second differential operational amplifier circuit controlledly between the power supply end and the ground end, in the integration period, the second switch combination is turned on, so that the second differential operational amplifier circuit is connected between the power supply end and the ground end, in the sampling period, the second switch combination is turned off, so that the second differential operational amplifier circuit is disconnected with the power supply end and the ground end.

[0007] In a further embodiment, the first differential operational amplifier circuit comprises a first input end, a second input end and an output end, the second differential operational amplifier circuit comprises a first input end, a second input end and an output end, the first input end of the first differential operational amplifier is connected with the first input end of the second differential operational amplifier circuit and serves as the first input end of the operational amplifier, the second input end of the first differential operational amplifier is connected with the second input end of the second differential operational amplifier circuit and serves as the second input end of the operational amplifier, and the output end of the first differential operational amplifier is connected with the output end of the second differential operational amplifier circuit and serves as the output end of the operational amplifier.

[0008] In a further embodiment, the first differential operational amplifier circuit and the second differential operational amplifier circuit are symmetrical, the operational amplifier further comprises a first switch combination, the first switch combination and the second switch combination are symmetrical, the first switch combination connects the first differential operational amplifier circuit controlledly between the power supply end and the ground end, and in the integration period and the sampling period, the first switch combination is always turned on, so that the first differential operational amplifier circuit is always connected between the power supply end and the ground end.

[0009] In a further embodiment, the symmetry of the first switch combination and the second switch combination refers to the number, connection position and connection mode of the first switches included in the first switch combination being the same as or opposite to the number, connection position and connection mode of the second switches included in the second switch combination, and the symmetry of the first differential operational amplifier circuit and the second differential operational amplifier circuit refers to the number, connection position and connection mode of the MOS transistors included in the first differential operational amplifier circuit being the same as or opposite to the number, connection position and connection mode of the MOS transistors included in the first differential operational amplifier circuit.

[0010] Compared with the prior art, the second differential operational amplifier circuit in the operational amplifier is turned off in the sampling period, and the first differential operational amplifier circuit in the operational amplifier can also ensure the output signal of the discrete-time integrator at this time. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor. Among them:

[0012] Figure 1 Fig. 1 is a structural schematic diagram of a discrete-time integrator in the present application;

[0013] Figure 2 Fig. 2 is a circuit structure diagram of the operational amplifier in Fig. 1 in an embodiment; Figure 1

[0014] Figure 3 Fig. 3 is a timing diagram of each signal in Fig. 1 and Fig. 2. Figure 1 Figure 2 DETAILED DESCRIPTION

[0015] In order to make the above-mentioned purposes, features and advantages of the present application more apparent and easy to understand, the following will further describe the present application in detail with reference to the drawings and specific embodiments.

[0016] ​​​The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that excludes other embodiments. In this invention, unless otherwise expressly specified and limited, terms such as "connected," "linked," and "coupled," indicating electrical connection, should be interpreted broadly; for example, it can refer to a direct electrical connection or an indirect electrical connection through an intermediate medium, such as an electronic component or functional circuit. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0017] Existing discrete-time integrators show almost no change in output signal during the sampling period. Therefore, the power consumption of the operational amplifier can be reduced during the sampling period.

[0018] Figure 1 This is a schematic diagram of the structure of a discrete-time integrator according to the present invention. Figure 2 for Figure 1 A circuit diagram of an operational amplifier in one embodiment; Figure 3 for Figure 1 and Figure 2 The timing diagram of each signal in the diagram.

[0019] like Figure 1 As shown, the discrete-time integrator 100 includes an operational amplifier 110. The operational amplifier 110 includes a first input terminal, a second input terminal, and an output terminal. The non-inverting input terminal of the operational amplifier 110 can be used as either the first or the second input terminal, and the inverting input terminal of the operational amplifier 110 can be used as either the second or the first input terminal.

[0020] like Figure 1As shown, the discrete-time integrator 100 further comprises: a first capacitor C1; a second capacitor C2 coupled between the first input terminal and the output terminal of the operational amplifier; a third capacitor C3 having its second terminal connected to the ground terminal; a first sampling switch SS1 coupled between the signal input terminal IN of the discrete-time integrator and the first terminal of the first capacitor C1; a second sampling switch SS2 coupled between the second terminal of the first capacitor C1 and the ground terminal; a first integration switch Si1 coupled between the first terminal of the first capacitor C1 and the ground terminal; a second integration switch Si2 coupled between the second terminal of the first capacitor C1 and the first input terminal of the operational amplifier; and a third integration switch Si3 coupled between the output terminal of the operational amplifier and the first terminal of the third capacitor C3. During a sampling period, the first sampling switch SS1 and the second sampling switch SS2 are turned on, and each integration switch is turned off. During an integration period, each sampling switch is turned off, and each integration switch is turned on. The output terminal of the operational amplifier serves as the signal output terminal OUT of the discrete-time integrator.

[0021] As shown in FIG. 1, the discrete-time integrator 100 further comprises a first differential operational amplifier circuit 110 and a second differential operational amplifier circuit 120. The first differential operational amplifier circuit 110 is connected between a power supply terminal VDD and a ground terminal GND. The second differential operational amplifier circuit 120 is connected between the power supply terminal VDD and the ground terminal GND through a second switch combination S21-S25. Figure 3 As shown in FIG. 1, the second sampling switch SS2 is controlled by a sampling control signal P1, and the first sampling switch SS1 is controlled by a delayed signal P1D of the sampling control signal P1, so that the second sampling switch SS1 is turned on and turned off earlier than the first sampling switch SS2. The second integration switch Si2 is controlled by a sampling control signal P2, and the first integration switch Si1 and the third integration switch Si3 are controlled by a delayed signal P2D of the sampling control signal P2, so that the second integration switch Si2 is turned on and turned off earlier than the first integration switch Si1 and the third integration switch Si3. In this embodiment, P1 / P1D is high, corresponding sampling switch is turned on; P1 / P1D is low, corresponding sampling switch is turned off; P2 / P2D is high, corresponding integration switch is turned on; and P2 / P2D is low, corresponding integration switch is turned off.

[0022] As shown in FIG. 1, the second sampling switch SS2 is controlled by a sampling control signal P1, and the first sampling switch SS1 is controlled by a delayed signal P1D of the sampling control signal P1, so that the second sampling switch SS1 is turned on and turned off earlier than the first sampling switch SS2. The second integration switch Si2 is controlled by a sampling control signal P2, and the first integration switch Si1 and the third integration switch Si3 are controlled by a delayed signal P2D of the sampling control signal P2, so that the second integration switch Si2 is turned on and turned off earlier than the first integration switch Si1 and the third integration switch Si3. In this embodiment, P1 / P1D is high, corresponding sampling switch is turned on; P1 / P1D is low, corresponding sampling switch is turned off; P2 / P2D is high, corresponding integration switch is turned on; and P2 / P2D is low, corresponding integration switch is turned off. Figure 2 As shown in FIG. 1, the second sampling switch SS2 is controlled by a sampling control signal P1, and the first sampling switch SS1 is controlled by a delayed signal P1D of the sampling control signal P1, so that the second sampling switch SS1 is turned on and turned off earlier than the first sampling switch SS2. The second integration switch Si2 is controlled by a sampling control signal P2, and the first integration switch Si1 and the third integration switch Si3 are controlled by a delayed signal P2D of the sampling control signal P2, so that the second integration switch Si2 is turned on and turned off earlier than the first integration switch Si1 and the third integration switch Si3. In this embodiment, P1 / P1D is high, corresponding sampling switch is turned on; P1 / P1D is low, corresponding sampling switch is turned off; P2 / P2D is high, corresponding integration switch is turned on; and P2 / P2D is low, corresponding integration switch is turned off.

[0023] In the integration period, the second switch combination S21-S25 is turned on, so that the second differential operational amplifier circuit is connected between the power supply terminal and the ground terminal, at this time the operational amplifier 110 operates based on the first differential operational amplifier circuit and the second differential operational amplifier circuit. In the sampling period, the second switch combination S21-S25 is turned off, so that the second differential operational amplifier circuit is disconnected from the power supply terminal and the ground terminal, at this time the operational amplifier 110 operates based on the first differential operational amplifier circuit, at this time the second differential operational amplifier circuit has no power consumption, and the first differential operational amplifier circuit can ensure the output signal of the discrete-time integrator, without affecting the normal operation of the discrete-time integrator 100. In this way, the power consumption of the discrete-time integrator 100 can be significantly reduced, for example, more than 40% of the power consumption can be saved.

[0024] The first differential operational amplifier circuit includes a first input terminal INPUT+, a second input terminal INPUT-, and an output terminal, and the second differential operational amplifier circuit includes a first input terminal INPUTc+, a second input terminal INPUTc-, and an output terminal. The first input terminal INPUT+ of the first differential operational amplifier is connected to the first input terminal INPUTc+ of the second differential operational amplifier circuit as the first input terminal of the operational amplifier, the second input terminal INPUT- of the first differential operational amplifier is connected to the second input terminal INPUTc- of the second differential operational amplifier circuit as the second input terminal of the operational amplifier, and the output terminal of the first differential operational amplifier is connected to the output terminal of the second differential operational amplifier circuit as the output terminal Vout of the operational amplifier.

[0025] The first differential operational amplifier circuit and the second differential operational amplifier circuit are symmetrical.

[0026] In a preferred embodiment, the operational amplifier 100 further includes a first switch combination S11-S15, and the first switch combination S11-S15 and the second switch combination S21-S25 are symmetrical. The first switch combination S11-S15 controls the connection of the first differential operational amplifier circuit between the power supply terminal VDD and the ground terminal GND. In the integration period and the sampling period, the first switch combination S11-S15 is always turned on, so that the first differential operational amplifier circuit is always connected between the power supply terminal and the ground terminal. The first switch combination S11-S15 is always turned on for a long time, which is to ensure the symmetry with the second switch combination S21-S25. If there is no first switch combination S11-S15, there is no circuit symmetrical with the second switch combination S21-S25, which affects the symmetry of the circuit, and there will be even harmonics in the frequency spectrum of the output signal of the discrete-time integrator 100.

[0027] In one embodiment, the symmetry between the first switch combination S11-S15 and the second switch combination S21-S25 means that the number, connection position, and connection method of the first switches included in the first switch combination are the same as or opposite to the number, connection position, and connection method of the second switches included in the second switch combination. The symmetry between the first differential operational amplifier circuit and the second differential operational amplifier circuit means that the number, connection position, and connection method of the MOS transistors included in the first differential operational amplifier circuit are the same as or opposite to the number, connection position, and connection method of the MOS transistors included in the second differential operational amplifier circuit.

[0028] In a specific embodiment, such as Figure 2 As shown, the first differential operational amplifier circuit includes PMOS transistors M3, Mi1, Mi2, M4, M5, M6, and M7, and NMOS transistors M8, M9, M1, and M2. The first switch combination includes first switches S11, S12, S13, S14, and S15. The second differential operational amplifier circuit includes PMOS transistors M3c, Mi1c, Mi2c, M4c, M5c, M6c, and M7c, and NMOS transistors M8c, M9c, M1c, and M2c. The second switch combination includes second switches S21, S22, S23, S24, and S25. The PMOS transistors M3, Mi1, Mi2, M4, M5, M6, and M7, and the NMOS transistors M8, M9, M1, and M2 in the first differential operational amplifier circuit are symmetrical to the PMOS transistors M3c, Mi1c, Mi2c, M4c, M5c, M6c, and M7c, and the NMOS transistors M8c, M9c, M1c, and M2c in the second differential operational amplifier circuit, respectively. The first switches S11, S12, S13, S14, and S15 in the first switch combination are symmetrical to the second switches S21, S22, S23, S24, and S25 in the second switch combination, respectively.

[0029] like Figure 2 As shown, the source of PMOS transistor M3 is coupled to the power supply terminal through the first switch S11, and its drain is coupled to the source of PMOS transistors Mi1 and Mi2. The gate of PMOS transistor M3 is connected to the bias voltage Vbias.

[0030] The drain of PMOS transistor Mi1 is coupled to the drain of NMOS transistor M1, and the drain of PMOS transistor Mi2 is coupled to the drain of NMOS transistor M2. The gate of PMOS transistor Mi1 serves as the first input terminal of the first differential operational amplifier, and the gate of PMOS transistor Mi2 serves as the second input terminal of the first differential operational amplifier.

[0031] The gate of the NMOS transistor M1 is connected with the gate of the NMOS transistor M2, the source of the NMOS transistor M1 is coupled to the ground end through the first switch S14, and the source of the NMOS transistor M2 is coupled to the ground end through the first switch S15.

[0032] The source of the PMOS transistor M4 is coupled to the power supply end through the first switch S12, the gate of the PMOS transistor M4 is connected with the gate of the PMOS transistor M5, and the drain of the PMOS transistor M4 is connected with the source of the PMOS transistor M6.

[0033] The source of the PMOS transistor M5 is coupled to the power supply end through the first switch S13, and the drain of the PMOS transistor M5 is connected with the source of the PMOS transistor M7.

[0034] The gate of the PMOS transistor M6 is connected with the gate of the PMOS transistor M7, the drain of the PMOS transistor M6 is connected with the drain of the NMOS transistor M8 and the gate of the PMOS transistor M4.

[0035] The drain of the PMOS transistor M7 is connected with the drain of the NMOS transistor M9.

[0036] The gate of the NMOS transistor M8 is connected with the gate of the NMOS transistor M9, and the source of the NMOS transistor M8 is connected with the drain of the NMOS transistor M1.

[0037] The source of the NMOS transistor M9 is connected with the drain of the NMOS transistor M2.

[0038] The drain of the PMOS transistor M7 is used as the output end of the first differential amplification circuit.

[0039] The source of the PMOS transistor M3c is coupled to the power supply end through the first switch S21, the drain of the PMOS transistor M3c is coupled to the source of the PMOS transistor M11c and the source of the PMOS transistor M12c, and the gate of the PMOS transistor M3c is connected with the bias voltage Vbias.

[0040] The drain of the PMOS transistor M11c is coupled to the drain of the NMOS transistor M1c, the drain of the PMOS transistor M12c is coupled to the drain of the NMOS transistor M2c, the gate of the PMOS transistor M11c is used as the first input end of the second differential operational amplifier, and the gate of the PMOS transistor M12c is used as the second input end of the second differential operational amplifier.

[0041] The gate of the NMOS transistor M1c is connected with the gate of the NMOS transistor M2c, the source of the NMOS transistor M1c is coupled to the ground end through the second switch S24, and the source of the NMOS transistor M2c is coupled to the ground end through the second switch S25.

[0042] The source of the PMOS transistor M4c is coupled to a power supply end through a second switch S22, the gate thereof is connected with the gate of the PMOS transistor M5c, and the drain thereof is connected with the source of the PMOS transistor M6c.

[0043] The source of the PMOS transistor M5c is coupled to a power supply end through a second switch S23, and the drain thereof is connected with the source of the PMOS transistor M7c.

[0044] The gate of the PMOS transistor M6c is connected with the gate of the PMOS transistor M7c, and the drain thereof is connected with the drain of the NMOS transistor M8c and the gate of the PMOS transistor M4c.

[0045] The drain of the PMOS transistor M7c is connected with the drain of the NMOS transistor M9c.

[0046] The gate of the NMOS transistor M8c is connected with the gate of the NMOS transistor M9c, and the source thereof is connected with the drain of the NMOS transistor M1c.

[0047] The source of the NMOS transistor M9c is connected with the drain of the NMOS transistor M2c.

[0048] The drain of the PMOS transistor M7c is used as an output end of a second differential amplification circuit.

[0049] The operational amplifier 100 further comprises an NMOS transistor M10, the gate of the NMOS transistor M10 is connected with the drain thereof, the gate thereof is connected with the gates of the NMOS transistors M1 and M1c, the source of the NMOS transistor M10 is grounded, and the drain of the NMOS transistor M10 receives a bias current Ibias.

[0050] The NMOS transistors M1, M2, the NMOS transistors M1c and M2c, and the NMOS transistor M10 jointly constitute a current mirror, and the currents on the NMOS transistors M1, M2, M1c and M2c can be controlled based on the bias current Ibias. The overall current of the operational amplifier 100 is controlled by the current mirror and the bias current, and the current mode control is adopted, so that the high-speed application can be adapted.

[0051] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "an example", "a specific example" or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms is not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, a person skilled in the art can combine and combine different embodiments or examples described in the present specification.

[0052] Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications and variations to the above embodiments within the scope of the present application.

Claims

1. A discrete-time integrator characterized by, It comprises: The operational amplifier comprises a first differential operational amplifier circuit, a second differential operational amplifier circuit and a second switch combination, wherein the first differential operational amplifier circuit is connected between a power supply end and a ground end, and the second switch combination connects the second differential operational amplifier circuit between the power supply end and the ground end under control, During an integration period, the second switch combination is turned on, so that the second differential operational amplifier circuit is connected between the power supply end and the ground end; during a sampling period, the second switch combination is turned off, so that the second differential operational amplifier circuit is disconnected from the power supply end and the ground end.

2. The discrete-time integrator of claim 1, wherein The first differential operational amplifier circuit comprises a first input end, a second input end and an output end, and the second differential operational amplifier circuit comprises a first input end, a second input end and an output end; the first input end of the first differential operational amplifier is connected to the first input end of the second differential operational amplifier circuit to serve as a first input end of the operational amplifier; the second input end of the first differential operational amplifier is connected to the second input end of the second differential operational amplifier circuit to serve as a second input end of the operational amplifier; the output end of the first differential operational amplifier is connected to the output end of the second differential operational amplifier circuit to serve as an output end of the operational amplifier; and the first differential operational amplifier circuit and the second differential operational amplifier circuit are symmetrical.

3. The discrete-time integrator of claim 2, wherein The operational amplifier further comprises a first switch combination, and the first switch combination and the second switch combination are symmetrical, The first switch combination connects the first differential operational amplifier circuit between the power supply end and the ground end under control; during the integration period and the sampling period, the first switch combination is always turned on, so that the first differential operational amplifier circuit is always connected between the power supply end and the ground end.

4. The discrete-time integrator of claim 3, wherein, The first switch combination and the second switch combination are symmetrical in that the number, connection position and connection mode of the first switches included in the first switch combination are the same as or opposite to the number, connection position and connection mode of the second switches included in the second switch combination. The first differential operational amplifier circuit and the second differential operational amplifier circuit are symmetrical in that the number, connection position and connection mode of the MOS transistors included in the first differential operational amplifier circuit are the same as or opposite to the number, connection position and connection mode of the MOS transistors included in the second differential operational amplifier circuit.

5. The discrete-time integrator of claim 3, wherein The first differential operational amplifier circuit comprises PMOS transistors M3, M11, M12, M4, M5, M6 and M7, and NMOS transistors M8, M9, M1 and M2; The first switch combination comprises first switches S11, S12, S13, S14 and S15; The second differential operational amplifier circuit comprises PMOS transistors M3c, M11c, M12c, M4c, M5c, M6c and M7c, and NMOS transistors M8c, M9c, M1c and M2c; The second switch combination comprises second switches S21, S22, S23, S24 and S25. The PMOS transistors M3, M11, M12, M4, M5, M6, M7 and the NMOS transistors M8, M9, M1, M2 in the first differential operational amplifier circuit are symmetrical with the PMOS transistors M3c, M11c, M12c, M4c, M5c, M6c, M7c and the NMOS transistors M8c, M9c, M1c, M2c in the second differential operational amplifier circuit respectively, The first switches S11, S12, S13, S14, S15 in the first switch combination are symmetrical with the second switches S21, S22, S23, S24, S25 in the second switch combination respectively.

6. The discrete-time integrator of claim 5, wherein The source of the PMOS transistor M3 is coupled to a power supply terminal through the first switch S11, the drain of the PMOS transistor M3 is coupled to the sources of the PMOS transistors M11 and M12, and the gate of the PMOS transistor M3 is connected to a bias voltage, The drain of the PMOS transistor M11 is coupled to the drain of the NMOS transistor M1, the drain of the PMOS transistor M12 is coupled to the drain of the NMOS transistor M2, the gate of the PMOS transistor M11 is the first input terminal of the first differential operational amplifier, and the gate of the PMOS transistor M12 is the second input terminal of the first differential operational amplifier, The gate of the NMOS transistor M1 is connected to the gate of the NMOS transistor M2, the source of the NMOS transistor M1 is coupled to a ground terminal through the first switch S14, and the source of the NMOS transistor M2 is coupled to the ground terminal through the first switch S15, The source of the PMOS transistor M4 is coupled to the power supply terminal through the first switch S12, the gate of the PMOS transistor M4 is connected to the gate of the PMOS transistor M5, and the drain of the PMOS transistor M4 is connected to the source of the PMOS transistor M6, The source of the PMOS transistor M5 is coupled to the power supply terminal through the first switch S13, and the drain of the PMOS transistor M5 is connected to the source of the PMOS transistor M7, The gate of the PMOS transistor M6 is connected to the gate of the PMOS transistor M7, the drain of the PMOS transistor M6 is connected to the drain of the NMOS transistor M8 and the gate of the PMOS transistor M4, The drain of the PMOS transistor M7 is connected to the drain of the NMOS transistor M9, The gate of the NMOS transistor M8 is connected to the gate of the NMOS transistor M9, and the source of the NMOS transistor M8 is connected to the drain of the NMOS transistor M1, The source of the NMOS transistor M9 is connected to the drain of the NMOS transistor M2, The drain of the PMOS transistor M7 is the output terminal of the first differential amplifier circuit, The source of the PMOS transistor M3c is coupled to the power supply terminal through the first switch S21, the drain of the PMOS transistor M3c is coupled to the sources of the PMOS transistors M11c and M12c, and the gate of the PMOS transistor M3c is connected to a bias voltage, The drain of the PMOS transistor M1c is coupled to the drain of the NMOS transistor M1c, the drain of the PMOS transistor M2c is coupled to the drain of the NMOS transistor M2c, the gate of the PMOS transistor M1c is the first input terminal of the second differential operational amplifier, the gate of the PMOS transistor M2c is the second input terminal of the second differential operational amplifier, The gate of the NMOS transistor M1c is connected to the gate of the NMOS transistor M2c, the source of the NMOS transistor M1c is coupled to the ground terminal through the second switch S24, the source of the NMOS transistor M2c is coupled to the ground terminal through the second switch S25, The source of the PMOS transistor M4c is coupled to the power supply terminal through the second switch S22, the gate thereof is connected to the gate of the PMOS transistor M5c, and the drain thereof is connected to the source of the PMOS transistor M6c, The source of the PMOS transistor M5c is coupled to the power supply terminal through the second switch S23, and the drain thereof is connected to the source of the PMOS transistor M7c, The gate of the PMOS transistor M6c is connected to the gate of the PMOS transistor M7c, the drain thereof is connected to the drain of the NMOS transistor M8c and the gate of the PMOS transistor M4c, The drain of the PMOS transistor M7c is connected to the drain of the NMOS transistor M9c, The gate of the NMOS transistor M8c is connected to the gate of the NMOS transistor M9c, and the source thereof is connected to the drain of the NMOS transistor M1c, The source of the NMOS transistor M9c is connected to the drain of the NMOS transistor M2c, The drain of the PMOS transistor M7c is the output terminal of the second differential amplifier circuit, The first input terminal of the first differential amplifier is connected to the first input terminal of the second differential amplifier as the first input terminal of the operational amplifier, The second input terminal of the first differential amplifier is connected to the second input terminal of the second differential amplifier as the second input terminal of the operational amplifier, The output terminal of the first differential amplifier is connected to the output terminal of the second differential amplifier as the output terminal of the operational amplifier, The operational amplifier further comprises an NMOS transistor M10, the gate of the NMOS transistor M10 is connected to the drain thereof, the gate thereof is connected to the gate of the NMOS transistors M1 and M1c, the source of the NMOS transistor M10 is grounded, and the drain of the NMOS transistor M10 receives a bias current.

7. The discrete-time integrator of claim 1, wherein, The operational amplifier comprises a first input terminal, a second input terminal and an output terminal; The discrete-time integrator further comprises: a first capacitor C1; a second capacitor C2 coupled between the first input terminal and the output terminal of the operational amplifier; a third capacitor C3, the second end of which is connected to the ground terminal; a first sampling switch coupled between the signal input terminal of the discrete-time integrator and the first end of the first capacitor C1; a second sampling switch coupled between the second end of the first capacitor C1 and the ground terminal; a first integration switch coupled between the first end of the first capacitor C1 and the ground terminal; a second integration switch coupled between the second end of the first capacitor C1 and the first input terminal of the operational amplifier; and a third integration switch coupled between the first end of the first capacitor C1 and the output terminal of the operational amplifier. a third integration switch coupled to an output of the operational amplifier and a first terminal of a third capacitor C3, wherein during a sampling period, the first and second sampling switches are on and each integration switch is off, and during an integration period, each sampling switch is off and each integration switch is on, an output of the operational amplifier as a signal output of the discrete-time integrator.

8. The discrete-time integrator of claim 7, wherein the second sampling switch is controlled by a sampling control signal P1 and the first sampling switch is controlled by a delayed version P1D of the sampling control signal P1 such that the second sampling switch turns on and off before the first sampling switch, the second integration switch is controlled by an integration control signal P2 and the first and third integration switches are controlled by a delayed version P2D of the integration control signal P2 such that the second integration switch turns on and off before the first and third integration switches.

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