USB bus circuit of feeder terminal unit

Abstract

The utility model discloses a USB bus circuit of a feeder terminal unit, and relates to the technical field of communication of the feeder terminal unit in an intelligent power grid. In order to solve the problems that an internal communication bus of an existing feeder terminal unit is complex in structure, low in cost performance, poor in anti-interference capability and insufficient in real-time communication efficiency, a high-performance RensauPD720115 chip is adopted as a master control, and input, processing and output of four paths of USB signals are achieved in combination with a common-mode inductor, a matched resistor and a common-mode filter. Meanwhile, the hot plug characteristic and efficient real-time communication are supported, and the power-on reset module provides a stable reset signal; the working state monitoring and configuration module performs over-current detection and state selection configuration, and the clock synchronization module uses a 24MHz passive crystal oscillator to provide accurate clock signals for the system; according to the scheme, the internal communication efficiency of the feeder terminal unit is greatly improved, and the stability, reliability and response speed of the system are remarkably improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to the communication technical field of feeder terminal unit in intelligent power grid, and more exactly relates to a feeder terminal unit USB bus circuit. BACKGROUND

[0002] With the continuous progress of intelligent power grid technology, the intelligent management and monitoring demand of distribution transformer area increases sharply. In order to improve the operation efficiency and reliability of power system, as the key node connecting the distribution side and the master station system, the importance of feeder terminal unit (FTU) is increasingly prominent. Especially for the real-time acquisition of power consumption data, fault detection and transformer state monitoring functions, the application of new generation FTU significantly enhances the quality and response speed of power service.

[0003] In the existing design, the feeder terminal unit mainly relies on RS-485 or CAN bus and other serial communication modes to complete the data exchange between internal devices. Although the RS-485 or CAN bus and other communication modes used by the traditional feeder terminal unit meet the past data transmission requirements to some extent, there are obvious deficiencies in structure simplification, cost performance and stability. First of all, the wiring complexity of these bus systems is high, which increases the installation and maintenance cost; secondly, in the strong electromagnetic interference power environment, the anti-interference ability of the traditional bus is poor, which easily leads to data transmission error; thirdly, due to the lack of hot plug feature, when new devices need to be added or faulty components need to be replaced, the whole system must be stopped, which affects the availability and response speed of the system. Finally, the traditional bus cannot efficiently support the real-time communication and transmission of key data on the distribution transformer side, especially in emergency situations, it cannot ensure that the information is reported to the master station in time and accurately, which limits the ability of power companies to quickly handle problems. UTILITY MODEL CONTENT

[0004] The utility model aims at: design a feeder terminal unit USB bus circuit solves the shortcomings in the background art.

[0005] In order to realize the above technical effect, the utility model adopts the following technical scheme:

[0006] A feeder terminal unit USB bus circuit, comprising:

[0007] Multi-channel USB signal input processing module, for receiving USB differential signals of different subsystems, filtering electromagnetic interference through common mode inductance and matching resistance and ensuring signal integrity;

[0008] Master control chip, for receiving and processing multi-channel USB signals, and transmitting the processed data to USB output and filtering module;

[0009] USB output and filter module, for processing USB signal output from the master chip, and ensuring signal quality and realizing hot plug function through matching resistance and common mode filter;

[0010] Power-on reset module, for providing reset signal when system starts;

[0011] Working state monitoring and configuration module, for overcurrent detection and state selection configuration;

[0012] Clock synchronization module, for providing clock signal for the master chip, ensuring time synchronization among all components;

[0013] The output end of the multi-channel USB signal input processing module is connected with the input end of the master chip; the output end of the master chip is connected with the input end of the USB output and filter module; the output end of the USB output and filter module is connected with the input end of the master chip; the output end of the power-on reset module is connected with the reset pin of the master chip; the output end of the working state monitoring and configuration module is connected with the state selection pin of the master chip; the output end of the clock synchronization module is connected with the clock pin of the master chip.

[0014] Further technical solution, the multi-channel USB signal input processing module includes common mode inductance TL2, TL3, TL4, TL5, matching resistance R5 and R6, R7 and R9, R13 and R14, R15 and R16, differential signal input end DM1 and DP1, DM2 and DP2, DM3 and DP3, DM4 and DP4; the signal line of each USB input branch is firstly connected to the differential signal input end through a common mode inductance in series with a pair of matching resistance; the first group of differential signals DM1 and DP1 of the differential signal input end are connected to the 21st and 22nd pins of the master chip, the second group of differential signals DM2 and DP2 are connected to the 23rd and 24th pins, the third group of differential signals DM3 and DP3 are connected to the 25th and 26th pins, and the fourth group of differential signals DM4 and DP4 are connected to the 27th and 28th pins.

[0015] Further technical solution, the model of the master chip is RENESAS uPD720115.

[0016] Further technical solution, the USB output and filter module includes matching resistance R1 and R2 and common mode filter TL1; the 38th pin and the 39th pin of the master chip are USB output signals, and are connected to one end of the matching resistance R1 and R2, respectively; the other end of the matching resistance R1 and R2 is connected with the input end of the common mode filter TL1, and the output end of the common mode filter TL1 is connected to the USB input port of the master chip.

[0017] Further technical solutions, the power-on reset module includes resistance R25 and capacitor C7;The one end of resistance R25 is connected to the positive pole of the power supply of the system, and the other end is connected to the one end of capacitor C7 and the reset pin ResetPin of the master control chip;The other end of capacitor C7 is grounded.

[0018] Further technical solutions, the working state monitoring and configuration module includes resistors R17 to R24, one end of the resistors R17 to R24 is connected to the 3.3V power supply, and the other end is connected to the 40 pin to the 47 pin of the master control chip respectively.

[0019] Further technical solutions, the clock synchronization module includes passive crystal oscillator Y1 and load capacitors C1, C2, one end of the passive crystal oscillator Y1 is connected to the 32nd pin of the master control chip, and the other end is connected to the 33rd pin of the master control chip;At the same time, a load capacitor is connected in parallel at both ends of the crystal oscillator Y1, one end of the load capacitor C1 is connected to the 32nd pin and grounded, and one end of the load capacitor C2 is connected to the 33rd pin and grounded.

[0020] Further technical solutions, the passive crystal oscillator Y1 is a 24MHz passive crystal oscillator.

[0021] In summary, due to the adoption of the above technical solutions, the beneficial effects of the utility model are:

[0022] 1、By adopting USB bus instead of traditional RS-485 or CAN bus, the complex wiring requirement is reduced, and the installation and maintenance cost is reduced.The versatility and easy expansion of USB interface make the system more flexible, facilitating subsequent upgrade and maintenance.

[0023] 2、The common-mode inductor and matching resistor are used in the multi-channel USB signal input processing module to effectively filter electromagnetic interference, ensuring the integrity of the signal and the stability of the transmission.This design is particularly suitable for power systems with complex electromagnetic environment, reducing data transmission errors caused by interference.

[0024] 3、The design of USB output and filtering module supports hot plug function, allowing new devices to be added or faulty components to be replaced without interrupting system operation, greatly improving the availability and response speed of the system, and ensuring the continuous operation ability of the system.

[0025] 4、The high speed and low delay characteristics provided by the USB bus ensure that the key data on the distribution side can be transmitted to the master station in real time and accurately.Especially in emergency situations, information can be reported to the master station in the first time, enhancing the ability of the power company to quickly handle problems and improving the emergency response efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0027] Fig. 1 It is a general working architecture diagram of the present application.

[0028] Fig. 2 It is a circuit principle diagram of the present application.

[0029] Fig. 3 It is a single USB channel working principle diagram of the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments only constitute some embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0031] As shown in Figs. 1-3 A feeder terminal unit USB bus circuit, comprising:

[0032] A multi-channel USB signal input processing module is used for receiving USB differential signals of different subsystems, filtering electromagnetic interference through common mode inductance and matching resistance and ensuring signal integrity. The multi-channel USB signal input processing module comprises common mode inductance TL2, TL3, TL4, TL5, matching resistance R5 and R6, R7 and R9, R13 and R14, R15 and R16, differential signal input end DM1 and DP1, DM2 and DP2, DM3 and DP3, and DM4 and DP4. The signal line of each USB input branch is firstly connected to the differential signal input end through a common mode inductance in series with a pair of matching resistors. The first group of differential signals DM1 and DP1 of the differential signal input end are connected to the 21st and 22nd pins of the master control chip, the second group of differential signals DM2 and DP2 are connected to the 23rd and 24th pins, the third group of differential signals DM3 and DP3 are connected to the 25th and 26th pins, and the fourth group of differential signals DM4 and DP4 are connected to the 27th and 28th pins.

[0033] In the USB bus circuit of the feeder terminal unit, the core technical principle of the multi-channel USB signal input processing module lies in using the combination of common-mode inductors and matching resistors to effectively manage the USB differential signals from different subsystems. The common-mode inductors (such as TL2, TL3, TL4, and TL5) play two key roles in the circuit: one is to filter out common-mode noise, i.e., electromagnetic interference that occurs simultaneously on both ends of the signal line, which helps to maintain the purity of the signal; the other is to provide a certain impedance to limit the transmission of high-frequency signals, further reducing the impact of electromagnetic interference. The matching resistors (such as R5 and R6, R7 and R9, R13 and R14, and R15 and R16) are used to ensure the integrity of the signal, which are connected in series with the signal line to absorb reflected waves and reduce signal reflection on the transmission line, thereby achieving stable transmission of the signal. The differential signal input end (such as DM1 and DP1, DM2 and DP2, etc.) is responsible for transmitting the processed signals to the master chip to ensure accurate reception and processing of data.

[0034] In practical applications, the multi-channel USB signal input processing module works as follows: when USB differential signals from different subsystems enter the feeder terminal unit, they first pass through their respective common-mode inductors. The common-mode inductor converts common-mode noise into heat energy consumption through its inductive properties, while maintaining the integrity of the differential signal. Subsequently, the signal passes through a pair of matching resistors, which are selected based on the characteristic impedance of the signal line to ensure impedance matching of the signal, reduce signal reflection and distortion. After these processes, the differential signal is stably transmitted to the differential signal input end and ultimately connected to the relevant pins (such as pins 21 and 22, 23 and 24, etc.) of the master chip. The master chip is responsible for decoding and processing these signals to achieve data communication and transmission.

[0035] Compared with the prior art, the multi-channel USB signal input processing module uses the combination of common-mode inductors and matching resistors, which can effectively filter out common-mode noise and reduce the impact of electromagnetic interference on the signal, thereby improving the electromagnetic compatibility of the system. In addition, the addition of matching resistors ensures impedance matching of the signal on the transmission line, reducing signal reflection and distortion, thereby improving the integrity and stability of the signal. Secondly, the module design supports the input processing of multi-channel USB signals, which can easily expand the number of USB interfaces as needed to meet the connection needs of different subsystems. By optimizing the signal transmission path and reducing electromagnetic interference, the module helps to improve the reliability and stability of the entire USB bus circuit of the feeder terminal unit, reducing system failure rates.

[0036] The master chip is used to receive and process multi-channel USB signals and transmit the processed data to the USB output and filtering module; the model of the master chip is RENESAS uPD720115;

[0037] In a specific implementation, the Renesas uPD720115 chip is a high-performance master chip specifically designed for USB bus circuits to receive and process multiple USB signals and transmit processed data to the USB output and filtering module. The technical principle of this chip is based on its internal digital signal processing capabilities, which can collect, process, and forward USB signals at high speed. The uPD720115 chip integrates an advanced USB protocol processing engine, which can effectively manage USB data streams and ensure the stability and reliability of data transmission. In addition, the chip has good electromagnetic compatibility and anti-interference ability, allowing it to work stably in complex electromagnetic environments. In the feeder terminal unit USB bus circuit, the Renesas uPD720115 chip as the core component, its working mode mainly includes three stages of signal reception, processing and output. First, the chip receives signals from multiple USB devices through its USB interface; second, the internal processor decodes, formats and buffers the signals to meet the requirements of the USB protocol; finally, the processed data is transmitted to the USB output and filtering module to further ensure the integrity and accuracy of the signal. Throughout the process, the uPD720115 chip can also perform error detection and correction to improve data transmission reliability.

[0038] The Renesas uPD720115 chip has many advantages and characteristics compared to existing technologies. First, its high-performance processing capability makes data transmission faster and response time shorter, which is particularly important for USB bus circuits that need to handle large amounts of data. Second, the chip has high integration, which can reduce the need for external components, thereby reducing the complexity and cost of the overall system. In addition, the uPD720115 chip also has good compatibility and scalability, which can support multiple USB standards and devices, adapting to changing technology needs. Finally, its optimized power management technology helps reduce the energy consumption of the entire system, achieving more environmentally friendly and energy-efficient operation.

[0039] In actual work, the application of the Renesas uPD720115 chip can significantly improve the performance of the feeder terminal unit USB bus circuit. It not only improves the efficiency and stability of data transmission, but also reduces system failure rate and prolongs the service life of the device. At the same time, due to its optimized power management, the energy consumption of the entire system is reduced, which helps to achieve more green and sustainable electronic device design. In addition, the high compatibility and scalability of the uPD720115 chip also provide convenience for future technology upgrades and device expansion, making the entire system more flexible and adaptable.

[0040] The USB output and filtering module is used for processing the USB signal output from the main control chip and ensuring signal quality and realizing the hot plug function through matching resistance and common mode filter; the USB output and filtering module comprises matching resistance R1 and R2 and common mode filter TL1; the 38th pin and the 39th pin of the main control chip are USB output signals and are connected to one end of the matching resistance R1 and R2 respectively, the other end of the matching resistance R1 and R2 is connected to the input end of the common mode filter TL1, and the output end of the common mode filter TL1 is connected to the USB input port of the main control chip;

[0041] In the feeder terminal unit USB bus circuit, the core technical principle of the USB output and filtering module is to ensure the USB signal quality output from the main control chip through the combined use of matching resistance and common mode filter, while realizing the hot plug function. The main role of the matching resistance R1 and R2 is to perform impedance matching to reduce signal reflection on the transmission line and ensure signal integrity. The common mode filter TL1 is used to filter out common mode noise in the signal, which is usually caused by external electromagnetic interference and can negatively affect signal quality. In addition, the common mode filter TL1 can also provide necessary protection during the hot plug process to prevent damage to the circuit caused by instantaneous current or voltage changes.

[0042] In specific implementation, the working process of the USB output and filtering module is as follows: first, the 38th pin (D+) and the 39th pin (D-) of the main control chip uPD720115 are connected to one end of the matching resistance R1 and R2 respectively as USB output signal sources. These matching resistances provide necessary impedance matching to ensure that the signal will not be distorted due to reflection during transmission. Next, the other end of the matching resistance R1 and R2 is connected to the input end of the common mode filter TL1, which effectively removes common mode noise through its internal structure to maintain signal purity. Finally, the output end of the common mode filter TL1 is directly connected to the USB input port of the main control chip to deliver the optimized USB signal to the MCU for further processing. The entire process not only relies on the synergistic effect of hardware components, but also benefits from carefully designed electrical connections to ensure efficient and stable transmission of signals from the main control chip to the MCU. In addition, the design of the USB output and filtering module also supports the hot plug function, allowing devices to be added or replaced without stopping, greatly improving the usability and response speed of the system.

[0043] Compared with the prior art, the USB output and filtering module can significantly reduce signal reflection and distortion during transmission, improve signal integrity and quality by using a combination of matching resistance and common-mode filter. This helps to ensure accurate data transmission and reduce bit error rate. The common-mode filter not only has filtering function, but also provides necessary protection during hot plug. This helps to prevent damage to the circuit caused by instantaneous current or voltage change, improves the stability and reliability of the system. In addition, the common-mode filter can effectively filter out common-mode noise in the signal, which is usually caused by external electromagnetic interference. By reducing the influence of electromagnetic interference, the USB output and filtering module helps to improve the electromagnetic compatibility of the system and reduce interference to other electronic devices. At the same time, the USB output and filtering module integrates matching resistance and common-mode filter together, simplifying the design of the circuit. This not only reduces the complexity and cost of the circuit, but also improves the reliability and maintainability of the circuit.

[0044] The power-on reset module is used to provide a reset signal when the system starts. The power-on reset module includes a resistor R25 and a capacitor C7. One end of the resistor R25 is connected to the positive terminal of the system power supply, and the other end is connected to one end of the capacitor C7 and the reset pin Reset Pin of the master control chip. The other end of the capacitor C7 is grounded.

[0045] In the USB bus circuit of the feeder terminal unit, the core technical principle of the power-on reset module is based on the charging and discharging characteristics of the RC (resistor-capacitor) circuit. When the system power is just turned on, since the initial state of the capacitor C7 is not charged, it is equivalent to a short circuit, at this time the power supply charges the capacitor C7 rapidly through the resistor R25. This charging process will form a short current pulse between the resistor R25 and the capacitor C7, and the pulse is transmitted to the reset pin Reset Pin of the master control chip through the resistor R25. Since the duration of this pulse is determined by the values of R25 and C7, it is sufficient to trigger the reset logic of the master control chip, so that the internal registers and state machine of the chip return to the initial state. As the capacitor C7 gradually fills with electricity, the charging current decreases to zero, and the reset signal disappears, and the system formally enters the normal working state. This process ensures that the system can start running from a certain, known state when powered on, avoiding abnormal states caused by unstable power supply or accidental power failure.

[0046] In practical applications, when the power is turned on, the current flows through the resistor R25 to the capacitor C7, starting the charging process. Since the initial voltage of the capacitor is zero, the current is large at the beginning of charging. This high current signal is transmitted to the reset pin of the master chip through R25, triggering the reset operation. As the voltage of capacitor C7 rises, the charging current gradually decreases until it reaches a threshold value, at which point the reset signal disappears and the master chip begins to execute the startup program, and the system enters a normal working state. This working method is simple and reliable, does not require additional control logic or complex circuit structure, and is very suitable for resource-limited or fast-starting application scenarios.

[0047] Compared with some complex reset circuits, the power-on reset module based on RC circuit has significant advantages. First, its structure is simple, low in cost, and easy to integrate into existing circuit designs, reducing the overall cost of the system. Second, the RC reset circuit works stably and reliably, is not affected by power voltage fluctuations, and can provide consistent reset signals under various power conditions, ensuring stable system startup. In addition, since the response time of the RC circuit is relatively short, it can quickly complete the reset operation, shorten the system startup time, and improve overall efficiency. Finally, this module does not require external control signals or additional software programming, reducing system complexity and potential failure points, improving system reliability and maintainability. These advantages make the power-on reset module based on RC circuit an ideal choice for embedded systems such as feeder terminal unit USB bus circuits, effectively improving system performance and stability.

[0048] The working state monitoring and configuration module is used for overcurrent detection and state selection configuration; the working state monitoring and configuration module includes resistors R17 to R24, one end of each of the resistors R17 to R24 is connected to a 3.3V power supply, and the other end is connected to the 40th to 47th pins of the master chip, respectively.

[0049] In the USB bus circuit of the feeder terminal unit, the working state monitoring and configuration module utilizes the resistance voltage division principle and the pin state detection function of the master control chip to realize real-time monitoring and flexible configuration of the circuit working state. Resistors R17 to R24 serve as voltage division resistors, one end of each of which is connected to a stable 3.3V power supply, and the other end is connected to the 40th to 47th pins of the master control chip. By carefully selecting the resistance values, it can be ensured that under different current conditions, the voltage levels on these pins can reflect the working state of the circuit. For example, under overcurrent conditions, the increase of current will cause the voltage drop on the voltage division resistor to increase, so that the voltage on the corresponding pin of the master control chip exceeds the preset threshold, triggering the overcurrent detection mechanism. At the same time, by changing the resistance values or connecting different resistance combinations, the working mode of the circuit can also be configured, such as setting different working voltage ranges, adjusting current protection thresholds, etc. This technical principle not only realizes real-time monitoring of the circuit state, but also provides flexible configuration options, enhancing the adaptability and reliability of the circuit.

[0050] In specific implementation, the working state monitoring and configuration module works as follows: when the circuit is powered on, 3.3V voltage is loaded onto the 40th to 47th pins of the master control chip through resistors R17 to R24, forming a series of voltage division circuits. The master control chip monitors the voltage levels on these pins in real time through the internal ADC (analog-to-digital converter) or comparator circuit. According to the preset voltage threshold or logic judgment, the master control chip can identify the current working state of the circuit, such as normal, overcurrent, etc. Once overcurrent is detected, the master control chip will immediately take protective measures, such as cutting off the power supply, restarting the system, etc., to prevent damage to the circuit. At the same time, by programming or external configuration, the resistance values or combinations can also be adjusted to realize flexible configuration of the circuit working mode. This working mode not only improves the monitoring accuracy and response speed of the circuit, but also enhances the flexibility and configurability of the circuit, meeting the needs of different application scenarios.

[0051] The application of the working state monitoring and configuration module in the USB bus circuit of the feeder terminal unit brings significant advantages and characteristics. First, the module can monitor the working state of the circuit in real time, timely discover and handle abnormal situations such as overcurrent, effectively avoiding equipment damage or data loss caused by circuit failure. Second, by flexibly configuring resistance values or combinations, the circuit working mode can be diversified, meeting the needs of different application scenarios and improving the adaptability and flexibility of the circuit. In addition, the module is simple in design, low in cost and easy to integrate into existing circuit systems, reducing the overall cost of the system. At the same time, since hardware monitoring and configuration are used, no additional software programming or external control signals are needed, reducing the complexity and potential failure points of the system and improving the reliability and stability of the system. These advantages and characteristics make the working state monitoring and configuration module an ideal choice for embedded systems such as the USB bus circuit of the feeder terminal unit, effectively improving the performance and user experience of the system. In practical applications, the module can significantly improve the reliability and stability of the circuit, reduce maintenance costs and provide a strong guarantee for the efficient operation of the feeder terminal unit.

[0052] The clock synchronization module is used to provide a clock signal for the main control chip to ensure time synchronization between all components. The clock synchronization module includes a passive crystal oscillator Y1 and load capacitors C1 and C2. One end of the passive crystal oscillator Y1 is connected to pin 32 of the main control chip, and the other end is connected to pin 33 of the main control chip. Meanwhile, a load capacitor is connected in parallel at both ends of the crystal oscillator Y1. One end of the load capacitor C1 is connected to pin 32 and grounded, and one end of the load capacitor C2 is connected to pin 33 and grounded. The passive crystal oscillator Y1 is a 24MHz passive crystal oscillator.

[0053] In the USB bus circuit of the feeder terminal unit, the clock synchronization module uses a passive crystal oscillator Y1 and its matching load capacitors C1 and C2 to generate a stable and accurate 24MHz clock signal, which is used by the main control chip to synchronize the operation time of all components. The passive crystal oscillator Y1 acts as an oscillator, with its two ends connected to pin 32 and pin 33 of the main control chip, forming an oscillation circuit. When the circuit is powered on, the mechanical structure inside the crystal oscillator Y1 begins to vibrate under the action of the electric field, generating an oscillation signal of a specific frequency. To ensure the stability of oscillation and the accuracy of frequency, load capacitors C1 and C2 are usually connected in parallel at both ends of the crystal oscillator, which adjust the frequency characteristics of the oscillation circuit and stabilize the oscillation amplitude. The value of the load capacitor is carefully selected according to the specifications of the crystal oscillator and the requirements of the circuit to ensure that the generated clock signal meets the system requirements. Through this technical principle, the clock synchronization module can provide a stable and reliable clock signal for the main control chip, ensuring time synchronization between all components inside the entire feeder terminal unit, thereby ensuring the accuracy of data transmission and stable operation of the system.

[0054] In a specific implementation, the clock synchronization module works as follows: first, after power-on, the passive crystal oscillator Y1 starts to vibrate under the action of the electric field, generating a 24MHz oscillation signal. This signal is transmitted through the two ends of the crystal oscillator to the 32nd and 33rd pins of the main control chip, respectively. At the same time, the load capacitors C1 and C2 are connected in parallel across the crystal oscillator, which stabilizes the oscillation frequency and amplitude, ensuring that the generated clock signal has sufficient stability and precision. The clock circuit inside the main control chip receives this clock signal and processes it to generate the required clock pulses for the system. These clock pulses are used to synchronize the operation of various modules inside the main control chip and data transmission with other components. In this way, the clock synchronization module ensures time synchronization between all components inside the feeder terminal unit, providing a solid foundation for the stable operation of the system.

[0055] In a specific implementation, the clock synchronization module composed of passive crystal oscillator Y1 and load capacitors C1 and C2 has the advantages of simple structure and low cost, making it easy to integrate into existing circuit systems. Secondly, due to the high frequency stability and precision of passive crystal oscillators, the generated clock signal can meet the high requirements of the system for time synchronization, ensuring the accuracy of data transmission and the stable operation of the system. In addition, the design of the clock synchronization module also considers electromagnetic compatibility (EMC) and electromagnetic interference (EMI) issues, reducing interference to the surrounding circuit and improving the overall performance of the system. Finally, since the clock synchronization module is implemented in hardware, it does not require additional software programming or external control signals, thus reducing the complexity and potential failure points of the system, improving the reliability and stability of the system. These advantages and characteristics make the clock synchronization module an ideal choice for embedded systems such as the USB bus circuit of the feeder terminal unit, effectively improving the performance and user experience of the system.

[0056] The output end of the multi-channel USB signal input processing module is connected to the input end of the main control chip; the output end of the USB output and filtering module is connected to the input end of the main control chip; the output end of the USB output and filtering module is connected to the input end of the main control chip; the output end of the power-on reset module is connected to the reset pin of the main control chip; the output end of the working state monitoring and configuration module is connected to the state selection pin of the main control chip; the output end of the clock synchronization module is connected to the clock pin of the main control chip.

[0057] The following is a specific example of the USB bus circuit of the feeder terminal unit:

[0058] When the system is powered on for the first time, the power-on reset module starts working. One end of resistor R25 is connected to the positive power supply (VCC) of the system, the other end is connected to one end of capacitor C7 and the reset pin (Reset Pin) of the main control chip Renesas uPD720115. The other end of capacitor C7 is grounded (GND). As the current provided by the positive power supply charges capacitor C7 through resistor R25, a high-level pulse is generated as a reset signal to the main control chip. This pulse ensures that the main control chip can complete the initialization process under stable conditions, avoiding the risk of incomplete startup or startup failure.

[0059] After the system starts, the multi-channel USB signal input processing module starts to receive USB differential signals from different subsystems. The signal lines of each USB input branch are first connected in series with a pair of matching resistors (such as R5 and R6, R7 and R9, etc.) through common-mode inductors (TL2, TL3, TL4, TL5). These components effectively filter electromagnetic interference and ensure signal integrity. The processed differential signals are connected to different pins (pins 21 to 28) of the main control chip uPD720115, ready for further processing.

[0060] After the main control chip receives the differential signal, the internal USB controller decodes, verifies and reorganizes the received data to ensure data integrity and accuracy. According to the set communication protocol, uPD720115 performs necessary conversion and optimization on the data, preparing to pass it to the USB output and filtering module. In addition, uPD720115 also supports multiple configuration options, allowing users to adjust working parameters such as power management and clock synchronization according to actual needs.

[0061] The processed data is output from pin 38 (D+) and pin 39 (D-) of the main control chip, connected to one end of matching resistors R1 and R2 respectively. These matching resistors provide proper impedance matching to ensure that the signal will not be distorted due to reflection during transmission. Next, the other end of matching resistors R1 and R2 is connected to the input end of common-mode filter TL1, which effectively removes common-mode noise through its internal structure to maintain signal purity. Finally, the output end of common-mode filter TL1 is directly connected to the USB input port of the main control MCU, passing the optimized USB signal to the MCU for further processing. The whole process not only relies on the synergistic effect of hardware components, but also benefits from the careful design of electrical connections, ensuring efficient and stable transmission of signals from the main control chip to the MCU.

[0062] In order to maintain the optimal working state of the system, the working state monitoring and configuration module is connected to the state selection pins (40 to 47 pins) of the master control chip through resistors R17 to R24. When an overcurrent or other abnormal condition is detected, the master control chip can control the level change of the corresponding pin through software, trigger the internal protection mechanism or adjust the working parameters. For example, the change of the level of a certain specific pin can activate the overcurrent protection circuit, disconnect the possibly damaged components, and prevent further damage. In addition, by programming the state of these pins, different working modes of the system, such as energy-saving mode, high-performance mode, etc., can also be flexibly configured to adapt to different application scenario requirements.

[0063] To ensure time synchronization between all components, the clock synchronization module uses a 24MHz passive crystal oscillator Y1 and load capacitors C1 and C2 to provide an accurate clock signal for the system. One end of the crystal oscillator Y1 is connected to pin 32 of the master control chip, and the other end is connected to pin 33; at the same time, a load capacitor is connected in parallel across the crystal oscillator, one end of C1 is connected to pin 32 and grounded, and one end of C2 is connected to pin 33 and grounded. This design ensures that the system can run on an accurate time reference, improving the accuracy and real-time performance of data transmission.

[0064] As can be seen from the above specific embodiments, the close cooperation between the modules enables the feeder terminal unit USB bus circuit to maintain high-performance operation in complex power environments. The system not only achieves efficient data transmission and processing, but also enhances the anti-interference and self-protection capabilities, ensuring the stability and reliability of the system. The hot-plug feature of the USB bus and the ease of expansion simplify the maintenance and upgrade process of the system, reducing the overall cost of ownership. Most importantly, the improvement of real-time communication efficiency ensures that key data on the distribution side can be reported to the master station in a timely and accurate manner, greatly improving the response speed and processing capacity of the power company in emergency situations. In summary, the application of this scheme not only significantly improves the performance of the system, but also lays a solid foundation for the efficient operation and development of smart grids.

[0065] Although the specific embodiments of the present application have been described above, those skilled in the art should understand that these specific embodiments are only illustrative, and those skilled in the art can make various omissions, substitutions and changes to the details of the above method and system without departing from the principles and essence of the present application. For example, combining the above method steps, performing substantially the same function in substantially the same way to achieve substantially the same result according to the same method is within the scope of the present application. Therefore, the scope of the present application is only limited by the appended claims.

Claims

1. A feeder terminal unit USB bus circuit, characterized by: The application relates to a multi-channel USB signal input processing module, a main control chip, a USB output and filtering module, a power-on reset module, a working state monitoring and configuration module and a clock synchronization module. The multi-channel USB signal input processing module is used for receiving USB differential signals of different subsystems, filtering electromagnetic interference through common-mode inductors and matching resistors and ensuring signal integrity; the main control chip is used for receiving and processing multi-channel USB signals and transmitting processed data to the USB output and filtering module; the USB output and filtering module is used for processing USB signals output from the main control chip and ensuring signal quality and realizing hot plug function through matching resistors and common-mode filters; the power-on reset module is used for providing a reset signal when the system starts; the working state monitoring and configuration module is used for overcurrent detection and state selection configuration; and the clock synchronization module is used for providing a clock signal for the main control chip and ensuring time synchronization among all components. The output end of the multi-channel USB signal input processing module is connected with the input end of the main control chip; the output end of the main control chip is connected with the input end of the USB output and filtering module; the output end of the USB output and filtering module is connected with the input end of the main control chip; the output end of the power-on reset module is connected with the reset pin of the main control chip; the output end of the working state monitoring and configuration module is connected with the state selection pin of the main control chip; and the output end of the clock synchronization module is connected with the clock pin of the main control chip. The multi-channel USB signal input processing module comprises common-mode inductors TL2, TL3, TL4 and TL5, matching resistors R5 and R6, R7 and R9, R13 and R14 and R15 and R16, and differential signal input ends DM1 and DP1, DM2 and DP2, DM3 and DP3 and DM4 and DP4; the signal line of each USB input branch is firstly connected with a common-mode inductor in series with a pair of matching resistors and then connected with the differential signal input end; the first group of differential signals DM1 and DP1 of the differential signal input end are connected with the 21st and 22nd pins of the main control chip, the second group of differential signals DM2 and DP2 are connected with the 23rd and 24th pins, the third group of differential signals DM3 and DP3 are connected with the 25th and 26th pins, and the fourth group of differential signals DM4 and DP4 are connected with the 27th and 28th pins. The model of the main control chip is RENESAS uPD720115. The USB output and filtering module comprises matching resistors R1 and R2 and a common-mode filter TL1; the 38th and 39th pins of the main control chip are USB output signals and are connected with one end of the matching resistors R1 and R2 respectively, the other end of the matching resistors R1 and R2 is connected with the input end of the common-mode filter TL1, and the output end of the common-mode filter TL1 is connected with the USB input port of the main control chip. The power-on reset module comprises a resistor R25 and a capacitor C7; one end of the resistor R25 is connected with the positive pole of the power supply of the system, the other end is connected with one end of the capacitor C7 and the reset pin of the main control chip, and the other end of the capacitor C7 is grounded. ​ 2. A feeder terminal unit USB bus circuit according to claim 1, wherein: ​ 3. A feeder terminal unit USB bus circuit according to claim 1, wherein: ​ 4. A feeder terminal unit USB bus circuit according to claim 1 wherein: ​ 5. A feeder terminal unit USB bus circuit according to claim 1 wherein: ​ 6. A feeder terminal unit USB bus circuit according to claim 1 wherein: The working state monitoring and configuration module comprises resistors R17 to R24, one end of each of the resistors R17 to R24 is connected to a 3.3V power supply, and the other end is respectively connected to the 40th pin to the 47th pin of the master control chip.

7. A feeder terminal unit USB bus circuit according to claim 1 wherein: The clock synchronization module comprises a passive crystal oscillator Y1 and load capacitors C1 and C2, one end of the passive crystal oscillator Y1 is connected to the 32nd pin of the master control chip, and the other end is connected to the 33rd pin of the master control chip; meanwhile, one load capacitor is connected in parallel at both ends of the crystal oscillator Y1, one end of the load capacitor C1 is connected to the 32nd pin and grounded, and one end of the load capacitor C2 is connected to the 33rd pin and grounded.

8. A feeder terminal unit USB bus circuit according to claim 7, wherein: The passive crystal oscillator Y1 is a 24MHz passive crystal oscillator.

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