Solar cell
By employing a P-type diffusion layer and an N-type tunneling passivation contact structure in BC cells, combined with a small-sized textured surface structure and optimized film design, the problem of poor P-poly passivation effect was solved, improving the short-circuit current and bifaciality of solar cells, reducing manufacturing costs, and simplifying the process.
Patent Information
- Application Number
- CN202422761079.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-12
- Publication Date
- 2025-11-18
- Estimated Expiration
- 2034-11-12
AI Technical Summary
In existing BC battery technology, P-poly has poor passivation effect, which affects battery efficiency, and its bifaciality is not advantageous, resulting in high manufacturing costs.
The P-type diffusion layer and N-type tunneling passivation contact structure are combined with a small-size textured structure and optimized film design, including a first textured structure of 0.1μm to 1μm and a density of 0.5E5mm-2 to 1E5mm-2, which increases the specific surface area, improves metal contact and reduces the passivation effect.
It improves the short-circuit current and bifaciality of solar cells, reduces manufacturing costs, simplifies the process, and increases cell efficiency and open-circuit voltage.
Smart Images
Figure CN223568004U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to photovoltaic field especially relates to a solar cell with good metal contact. BACKGROUND
[0002] BC battery is full back electrode contact (full back electrode contact) crystalline silicon photovoltaic cell, its characteristics are that all grid lines of the positive surface of the battery are transferred to the back surface, the shading to incident light is greatly reduced, and the battery has the advantages of high efficiency, high optimization degree of grid lines, simple packaging, and attractive appearance. However, with the increase of process flow, the precision requirement of the process is improved, which leads to the increase of manufacturing cost and restricts the industrial development of BC battery.
[0003] Benefiting from the maturity of TOPCon battery process, TBC battery combining BC battery process and TOPCon battery technology becomes the most cost-effective BC battery route at present. Generally, the P-type doped crystalline silicon layer (P-poly layer) is formed by low pressure chemical vapor deposition (LPCVD) process and boron diffusion, and the N-type doped crystalline silicon layer (N-poly layer) is formed by LPCVD process and phosphorus diffusion.
[0004] Compared with the N-poly structure, the passivation effect of the P-poly is slightly poor, because compared with phosphorus, boron is more difficult to diffuse in poly silicon and more likely to gather in the oxide layer, which destroys the tunneling structure and thus greatly affects the overall efficiency of the battery; and the double-sided rate of the BC battery itself does not have an advantage.
[0005] Therefore, it is necessary to provide an improved solar cell to solve the above technical problems. UTILITY MODEL CONTENT
[0006] The utility model aims at being able to at least solve one of the technical problems existing in the prior art, and provides a solar cell.
[0007] To achieve the above utility model purposes, the utility model adopts the following technical scheme:
[0008] A solar cell, comprising a silicon substrate, a P-type diffusion layer and an N-type tunneling passivation contact structure located on the back surface of the silicon substrate, a first electrode located on the back surface of the P-type diffusion layer, and a second electrode located on the back surface of the N-type tunneling passivation contact structure; the N-type tunneling passivation contact structure comprises a tunneling layer and an N-type doped crystalline silicon layer located on the back surface of the tunneling layer; the surface of the P-type diffusion layer has a first textured structure, the base width of the pyramid of the first textured structure is 0.1-1 μm, and / or the density of the pyramid of the first textured structure is 0.5E5-1E6 mm -2~1E5mm -2 .
[0009] In one embodiment, the front surface of the silicon substrate has a second texturing structure, and the second texturing structure has a roughness greater than the roughness of the first texturing structure.
[0010] In one embodiment, the front surface of the silicon substrate has a second texturing structure, and the second texturing structure has a pyramid base width of 1 μm to 5 μm, and / or the second texturing structure has a pyramid density of 2E5mm -2 ~3E5mm -2 .
[0011] In one embodiment, the P-type diffusion layer has a diffusion depth of 0.3 μm to 2 μm.
[0012] In one embodiment, the tunneling layer has a thickness of 0.5 nm to 3 nm, and the N-type doped crystalline silicon layer has a thickness of 100 nm to 200 nm.
[0013] In one optional embodiment, the tunneling layer is a silicon oxide layer or a silicon carbide layer, and the tunneling layer has a thickness of 0.5 nm to 3 nm.
[0014] In one embodiment, the N-type doped crystalline silicon layer is one or a combination of an N-type doped microcrystalline silicon layer or an N-type doped polycrystalline silicon layer, and the N-type doped crystalline silicon layer has a thickness of 100 nm to 200 nm.
[0015] In one embodiment, the solar cell further comprises a spacer region between the P-type diffusion layer and the N-type tunneling passivation contact structure.
[0016] In one embodiment, the back surface of the spacer region has a third texturing structure, and the third texturing structure has a roughness greater than the roughness of the first texturing structure.
[0017] In one embodiment, the front surface of the silicon substrate has a second texturing structure, and the back surface of the spacer region has a third texturing structure, and the third texturing structure is consistent with the second texturing structure.
[0018] In one embodiment, the solar cell further comprises a back surface passivation layer and a back surface anti-reflection layer on the back surface of the P-type diffusion layer, the N-type tunneling passivation contact structure, and the spacer region, the first electrode contacts the P-type diffusion layer through the back surface anti-reflection layer and the back surface passivation layer, and the second electrode contacts the N-type doped crystalline silicon layer through the back surface anti-reflection layer and the back surface passivation layer.
[0019] In one embodiment, the solar cell further comprises a front surface passivation layer on the front surface of the silicon substrate, and a front surface anti-reflection layer on the front surface of the front surface passivation layer.
[0020] In one embodiment, the bonding depth of the first electrode and the P-type diffusion layer is 1 / 2-1 / 3 of the depth of the P-type diffusion layer, and the bonding depth of the second electrode and the N-type doped crystalline silicon layer is 1 / 2-1 / 3 of the thickness of the N-type doped crystalline silicon layer.
[0021] The beneficial effects of the solar cell are as follows: the surface of the P-type diffusion layer has a first textured structure, the specific surface area is increased, the metal contact of the P region can be improved, the short circuit current is improved, the efficiency is improved, the double surface rate of the BC cell is improved, the first textured structure is a small-size textured structure with a pyramid height-width range of 0.1-1 microns and a density of 0.5E5-1E5 mm-2, the influence of the small-size textured structure on the passivation effect of the P region surface is reduced, the open circuit voltage is ensured, and the influence of the small-size textured structure on the subsequent other film layer deposition process is small. BRIEF DESCRIPTION OF DRAWINGS
[0022] Figure 1 The solar cell is a structure diagram of a preferred embodiment of the utility model.
[0023] Figure 2 The solar cell is a structure diagram of a preferred embodiment of the utility model. Figure 1 The solar cell is a structure diagram of a preferred embodiment of the utility model.
[0024] Wherein, 100-solar cell, 1-silicon substrate, 11-main grid, 12-sub grid, 13-frame grid line, 2-P-type diffusion layer, 3-N-type tunneling passivation contact structure, 31-tunneling layer, 32-N-type doped crystalline silicon layer, 4-separation area, 5-back passivation layer, 6-back anti-reflection layer, 71-first electrode, 72-second electrode, 8-front passivation layer, 9-front anti-reflection layer. DETAILED DESCRIPTION
[0025] The utility model will be described in detail below in combination with the specific embodiments shown in the drawings. However, these embodiments do not limit the utility model, and the changes in structure, method or function made by those skilled in the art based on these embodiments are all included in the protection scope of the utility model.
[0026] In various drawings of the utility model, in order to facilitate the illustration, some dimensions of the structure or part are exaggerated relative to other structures or parts, therefore, only used for illustrating the basic structure of the subject of the utility model.
[0027] For the convenience of description, the light receiving surface (main light receiving surface) of the silicon substrate 1 is defined as the front surface, and the back surface (secondary light receiving surface) of the silicon substrate 1 is defined as the back surface with the silicon substrate 1 as a reference. The film layer located on the front surface of the silicon substrate 1 is collectively referred to as the front surface film layer, the surface of the front surface film layer away from or facing away from the silicon substrate 1 is the front surface, and the surface of the front surface film layer facing the silicon substrate 1 is the back surface. The film layer located on the back surface of the silicon substrate is collectively referred to as the back surface film layer, the surface of the back surface film layer facing the silicon substrate 1 is the front surface, and the surface of the back surface film layer away from or facing away from the silicon substrate is the back surface.
[0028] Please refer to Figures 1-2 As shown in FIG. 1, the solar cell 100 of the preferred embodiment of the present application comprises a silicon substrate 1, a P-type diffusion layer 2 (P region) and an N-type tunneling passivation contact structure 3 (N region) located on the back surface of the silicon substrate 1, a first electrode 71 located on the back surface of the P-type diffusion layer 2, and a second electrode 72 located on the back surface of the N-type tunneling passivation contact structure 3.
[0029] The silicon substrate 1 is an N-type silicon wafer with a resistivity of 0.3Ω·cm to 7Ω·cm, preferably 1Ω·cm to 3.5Ω·cm.
[0030] In an embodiment, the front surface of the silicon substrate 1 has a second textured structure, which can reduce the reflectivity of the front surface, improve the light utilization rate, and improve the cell efficiency.
[0031] In a specific embodiment, the second textured structure is a pyramid texture, the base width of the pyramid of the second textured structure is 1μm to 5μm, and / or the density of the pyramid of the second textured structure is 2E5mm -2 to 3E5mm -2 .
[0032] The common P-poly structure on the market is formed by LPCVD + boron expansion two-step method, which is subject to the characteristics of long time-consuming of poly layer preparation by LPCVD and poor thickness stability of tunneling layer, so it is difficult to have operation space for the plan of shortening time and reducing cost in the P-poly layer preparation process. The P-poly structure of the P region is changed to a P-type diffusion layer in the present application, which is formed by P-type doping source diffusing inwardly from the back surface of the silicon substrate 1. On the one hand, the P-type doping source one-step diffusion can greatly shorten the process time and reduce the process cost; and the full-line equipment of TOPCon can be directly used for the development of BC cell structure, greatly reducing the development cost. On the other hand, compared with the P-poly structure, the P-type diffusion layer can reduce the infrared absorption of the back surface poly layer, improve the light utilization rate, improve the short-circuit current of the cell, and enhance the double-sided rate of the cell.
[0033] In the present application, the P-type doping source is boron (B), aluminum (Al) or gallium (Ga) and the like.
[0034] In an embodiment, the P-type diffusion layer 2 is a boron diffusion layer, with a doping concentration of 1E18cm -3 ~1E20cm -3 , a sheet resistance of 50Ω / sq~400Ω / sq, and a junction depth of 0.3μm~2μm, preferably 0.5μm~1.0μm. By controlling the diffusion depth of boron, the passivation effect and metal contact of the P region are optimized. If the diffusion depth of boron exceeds this range, Auger recombination will increase, and the bulk lifetime of the silicon wafer will decrease. If the diffusion depth of boron is less than 0.3μm, there is a risk of the Ag piercing the PN junction region when preparing the metal electrode.
[0035] The surface of the P-type diffusion layer 2 has a first textured structure, which increases the specific surface area and can improve the metal contact of the P region, increase the short-circuit current, and play a role in improving efficiency, and also has a role in improving the double-sided rate of the BC battery.
[0036] In an embodiment, the base width of the pyramids of the first textured structure is 0.1μm~1μm. That is, the textured structure on the surface of the P-type diffusion layer is set to a small-size texture. Compared with a regular-size texture (such as the second textured structure), the small-size texture reduces the influence on the passivation effect of the P region surface, ensuring the open-circuit voltage, and has little influence on the subsequent deposition process of other film layers.
[0037] In an embodiment, the first textured structure is a pyramid texture, and the distribution density of the pyramids is 0.5E5mm -2 ~1E5mm -2 . The sparse texture has little influence on the passivation effect of the P region surface and can also improve the double-sided rate of the BC battery.
[0038] When the second textured structure is provided on the front surface of the silicon substrate 1, the roughness of the first textured structure is less than the roughness of the second textured structure, that is, the size of the first textured structure is less than the size of the second textured structure. In this way, the light limiting effect and light utilization rate of the front surface can be ensured, and the back surface has good passivation and metal contact effect, thereby comprehensively improving the battery efficiency.
[0039] The first textured structure with a small size and sparsity is formed by reducing the mass concentration of the NaOH solution and the additive and the reaction time of the back P region.
[0040] The N-type tunneling passivation contact structure 3 includes a tunneling layer 31 on the back surface of the silicon substrate 1 and an N-type doped silicon layer 32 on the back surface of the tunneling layer 31.
[0041] The tunneling layer 31 is a silicon oxide layer or a silicon carbide layer, and the thickness of the tunneling layer 31 is 0.5nm~3nm.
[0042] The N-type doped crystalline silicon layer 32 is a combination of one or more of N-type doped microcrystalline silicon layer or N-type doped polysilicon layer. The thickness of the N-type doped crystalline silicon layer 32 is 50-200 nm, preferably 80-120 nm.
[0043] The N-type doped element in the N-type doped crystalline silicon layer 32 is preferably phosphorus (P), arsenic (As) or the like. In one embodiment, the N-type doped crystalline silicon layer 32 is a phosphorus doped polysilicon layer with a surface doping particle concentration of 5E20 cm -3 -2E21 cm -3 and a thickness of 50-100 nm.
[0044] In addition, the solar cell 100 further comprises a spacing region 4 between the P-type diffusion layer 2 and the N-type tunneling passivation contact structure 3, the spacing region 4 is recessed from the back surface to the front surface of the silicon substrate 1, and separates the P-type diffusion layer 2 and the N-type tunneling passivation contact structure 3 to prevent leakage.
[0045] In one embodiment, the depth L1 of the spacing region 4 is greater than the diffusion depth of the P-type diffusion layer 2. Alternatively, the depth L1 of the spacing region 4 is 1-20 μm, preferably 5-10 μm. This depth can insulate the P-type diffusion layer 2 and the N-type tunneling passivation contact structure 3 to avoid leakage.
[0046] In one embodiment, the width L2 of the spacing region 4 is 10-150 μm, preferably 50-100 μm. In the extension direction of the silicon substrate 1, the P-type diffusion layer 2 and the N-type tunneling passivation contact structure 3 are isolated to avoid leakage.
[0047] In one embodiment, the P-type diffusion layer 2 is higher than the N-type tunneling passivation contact structure 3, so that the entire back surface is similar to a wave shape, and the light can be reflected multiple times on the back surface, which is beneficial to improve light absorption.
[0048] In one embodiment, the height difference between the P-type diffusion layer 2 and the N-type tunneling passivation contact structure 3 is 2-10 μm, preferably 4-7 μm.
[0049] In addition, the back surface of the spacing region 4 has a third textured structure, which improves light absorption at the spacing region 4 and is beneficial to improve cell efficiency.
[0050] In one embodiment, the roughness of the third textured structure is greater than the roughness of the first textured structure, the light reflectivity at the spacing region 4 is low, which improves the back surface light absorption and thus improves the cell efficiency.
[0051] In another embodiment, the third textured structure is consistent with the second textured structure, and both can be formed in the same process, which can simplify the process flow.
[0052] The solar cell 100 further comprises a back passivation layer 5 on the back of the P-type diffusion layer 2, the N-type tunneling passivation contact structure 3 and the spacer region 4, a back anti-reflection layer 6 on the back of the back passivation layer 5.
[0053] The back passivation layer 5 is used to passivate the P region, the N region and the spacer region 4, reduce the interface recombination and improve the open circuit voltage. In the utility model, the back passivation layer 5 adopts an aluminum oxide layer, and the thickness of the back passivation layer 5 is 2nm-10nm, preferably 3nm-6nm.
[0054] The back anti-reflection layer 6 is used to reduce the light reflection of the back, and can significantly improve the cell efficiency, especially in a double glass assembly. In the utility model, the back anti-reflection layer 6 is one or more laminated films of silicon nitride, silicon oxynitride and silicon oxide, and the thickness is 60nm-130nm, preferably 60nm-90nm.
[0055] The first electrode 71 is located on the back of the P-type diffusion layer 2, contacts the P-type diffusion layer 2 through the back anti-reflection layer 6 and the back passivation layer 5, does not penetrate the P-type diffusion layer 2 and directly contacts the silicon substrate 1, ensures the metal contact of the P-type diffusion layer 2 and can reduce the metal recombination.
[0056] The second electrode 72 contacts the N-type doped silicon layer 32 through the back anti-reflection layer 6 and the back passivation layer 5, does not penetrate the tunneling layer 31 and contacts the silicon substrate 1, and reduces the metal recombination.
[0057] Preferably, the first electrode 71 and the second electrode 72 are metal electrodes processed through a laser-assisted sintering process, and the J0 under the metal of the P-type diffusion layer 2 is greatly reduced.
[0058] The bonding depth of the first electrode 71 and the P-type diffusion layer 2 is 1 / 2-1 / 3 of the depth of the P-type diffusion layer 2, which ensures the metal contact of the first electrode 71 and the P-type diffusion layer 2 and reduces the contact resistance. The bonding depth of the second electrode 72 and the N-type doped silicon layer 32 is 1 / 2-1 / 3 of the thickness of the N-type doped silicon layer 32, which ensures the good metal contact of the second electrode 72 and the N-type doped silicon layer 32, reduces the contact resistance and improves the overall cell efficiency.
[0059] The solar cell 100 further comprises a front passivation layer 8 on the front thereof, which passivates the front of the silicon substrate 1 and reduces the surface recombination.
[0060] Preferably, the front passivation layer 8 and the back passivation layer 5 are consistent in material and thickness, can be deposited on both sides in the same process, do not need to be deposited twice and can simplify the process flow.
[0061] In one embodiment, the front passivation layer 8 is preferably an aluminum oxide layer, with a thickness of 2-10 nm, preferably 3-6 nm.
[0062] The solar cell 100 also includes a front anti-reflective layer 9 on the front side of the front passivation layer 8, which reduces the light reflectivity of the front side and improves light absorption, thereby improving the cell efficiency.
[0063] Preferably, the front anti-reflective layer 9 has the same material and thickness as the back anti-reflective layer 6, and can be formed by double-sided deposition in the same process, without the need for two-time deposition, thereby simplifying the process flow.
[0064] In one embodiment, the anti-reflective layer is one or more of a silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 60-130 nm, preferably 60-90 nm.
[0065] In the following, a method for preparing a solar cell 100 will be provided to obtain the solar cell 100 having the above structure.
[0066] S1, double-sided texturing: using an N-type silicon wafer with a resistivity of 0.3-7 Ω-cm as the silicon substrate 1; using a NaOH solution to form a first textured structure.
[0067] In one embodiment, the NaOH solution has a mass concentration of 0.2-2%, the additive has a mass concentration of 0.2-2%, the texturing time is 50-200 s, and the temperature is 50-70°C, to obtain a small-pyramid textured surface, with a pyramid base width of 0.1-1 μm and a pyramid density of 0.5E5 mm -2 -1E5 mm -2 .
[0068] S2, forming a P-type diffusion layer: using boron doping as an example, using a tube diffusion method with BCl3 or BBr3 as the diffusion source, and controlling the temperature at 900-1100°C, to obtain a boron diffusion layer (boron junction) with a sheet resistance of 50-400 ohmm / sq, a BSG layer thickness of 30-150 nm, a surface doping concentration of 1E18 cm -3 -1E20 cm -3 , and a junction depth of 0.3-2 μm.
[0069] S3, removing the BSG layer of the back N region and the spacer region 4: performing laser slotting on the back N region and the spacer region 4 according to a pattern design, to remove the BSG layer.
[0070] The laser grooving in each process step is selected from, but not limited to, any one of the following: ultraviolet picosecond laser grooving, spot power is 3W~20W, spot diameter is 100μm~150μm, frequency is 500kHz~600kHz, and scanning speed is 40m / s~80m / s.
[0071] S4, boron knot removal: first, remove the BSG layer around the front and side surfaces, for example, add hydrofluoric acid solution in the single-sided chain device to remove the BSG layer around the front and side surfaces; then, remove the boron knot around the front surface and the boron knot in the laser grooving area on the back surface.
[0072] In an embodiment, the front and back laser grooving areas are subjected to alkali polishing by using a polishing NaOH solution, the boron knot is removed, and a flat tower base is formed; the width of the pyramid tower base in the laser grooving area is controlled to be 10μm~50μm, and the boron knot and the BSG layer in the non-laser grooving area (P area) are all reserved.
[0073] S5, N-type tunneling passivation contact structure is prepared on the back surface: in-situ doping by PECVD is performed on the entire back surface, a tunneling layer and a phosphorus-doped poly layer are grown on the entire back surface, and the PSG layer mask protects the poly layer.
[0074] In an embodiment, the tunneling layer is SiOx, the thickness is preferably 1nm~2nm, the N-poly layer has a thickness of preferably 100nm~200nm, and the PSG layer has a thickness of 10nm~50nm.
[0075] S6, annealing and activation: annealing treatment is performed in a high-temperature annealing furnace, the annealing temperature ranges from 880℃ to 980℃, after annealing, the doped amorphous silicon is converted into doped polysilicon, phosphorus is activated, the N-type tunneling passivation contact structure is formed on the back surface, the surface concentration of the N-poly layer phosphorus doping ranges from 1E19cm -3 ~1E21cm -3 .
[0076] S7, PSG layer removal in the P area and the interval area: the PSG layer is removed by laser grooving in the P area and the interval area according to the patterning, and the N-poly layer is exposed.
[0077] S8, N-poly layer removal: first, remove the PSG layer around the front and side surfaces, for example, add hydrofluoric acid solution in the single-sided chain device to remove the PSG layer around the front and side surfaces; then, remove the N-poly layer around the front surface and the N-poly layer in the laser grooving area on the back surface.
[0078] The N-poly layer of the front and back laser grooving area is removed by adding a NaOH solution in a tank machine, and the corresponding area is textured, while a second textured structure is formed on the front surface of the silicon substrate 1, and a third textured structure is formed in the interval area, the pyramid size of the second and third textured structures is larger than that of the first textured structure, the base width of the pyramid is 1-5 microns, and the density of the pyramid is 2E5-3E5 mm -2 . -2 .
[0079] The mass concentration of NaOH is 0.5-5%, and the mass concentration of the additive is 1-10%; the processing time in the tank machine is 100-800 seconds, and the temperature is 65-90 DEG C. Finally, the PSG layer of the back N area and the BSG layer of the P area are removed by using hydrofluoric acid, and RCA cleaning is performed.
[0080] S9, passivation layer is prepared on the front and back surfaces: an aluminum oxide layer is deposited on the front and back surfaces as a passivation layer by using an ALD process, and the thickness is 2-7 nm.
[0081] S10, antireflection layer is prepared on the front surface: an antireflection layer is deposited on the front surface by using a PECVD process, and the antireflection layer can be one or more stacked films of silicon nitride, silicon oxynitride and silicon oxide, and the thickness of the antireflection layer is 60-130 nm.
[0082] S11, antireflection layer is prepared on the back surface: an antireflection layer is deposited on the back surface by using a PECVD process, and the antireflection layer can be one or more stacked films of silicon nitride, silicon oxynitride and silicon oxide, and the thickness of the antireflection layer is 60-130 nm.
[0083] S12, screen printing metal electrodes: electrodes are prepared by screen printing, including preparation of a back surface main grid electrode DE and preparation of a back surface P area and N area auxiliary grid electrode.
[0084] S13, laser-assisted sintering technology: the slurry sintering of the P area and the N area of the back surface of the battery is optimized by using a laser-assisted sintering technology. The bias voltage is 5-20 V, preferably 8-12 V. The laser can be a long-wave 1064 nm or green light 532 nm on the market, and the laser width is 1-2 mm.
[0085] S14, test sorting: the battery piece is tested and sorted, and is stored in a warehouse.
[0086] In summary, the surface of the P-type diffusion layer 2 is provided with a first textured structure, the specific surface area is increased, the metal contact of the P area can be improved, the short-circuit current is improved, the efficiency is improved, and the double-sided rate of the BC battery is improved. Further, the first textured structure is a small-size textured structure with a height-width range of 0.1-1 micron, and the density is 0.5E5-1E5 mm -2 .-2 , reduce the passivation effect of the surface of the P region, and ensure the open circuit voltage; and the small size of the suede has little effect on the subsequent deposition process of other film layers.
[0087] It should be understood that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be combined appropriately to form other embodiments that those skilled in the art can understand.
[0088] The series of detailed descriptions listed above are only specific descriptions of the feasible embodiments of the present application, and are not intended to limit the protection scope of the present application. Any equivalent embodiments or changes made without departing from the spirit of the present application should be included in the protection scope of the present application.
Claims
1. A solar cell comprising a silicon substrate, a P-type diffusion layer and an N-type tunneling passivation contact structure located at the backside of the silicon substrate, a first electrode located at the backside of the P-type diffusion layer, a second electrode located at the backside of the N-type tunneling passivation contact structure; the N-type tunneling passivation contact structure comprises a tunneling layer, an N-type doped crystalline silicon layer located at the backside of the tunneling layer; characterized in that, The surface of the P-type diffusion layer has a first textured structure, the base width of the pyramids of the first textured structure is 0.1 μm to 1 μm, and / or the density of the pyramids of the first textured structure is 0.5E5 mm -2 to 1E5 mm -2 .
2. The solar cell of claim 1, wherein: The front surface of the silicon substrate has a second textured structure, and the roughness of the second textured structure is greater than the roughness of the first textured structure.
3. The solar cell of claim 1, wherein: The front surface of the silicon substrate has a second texture structure, the base width of the pyramids of the second texture structure is 1 μm to 5 μm, and / or the density of the pyramids of the second texture structure is 2E5 mm -2 to 3E5 mm -2 .
4. The solar cell of claim 1, wherein: The diffusion depth of the P-type diffusion layer is 0.3-2 μm.
5. The solar cell of claim 1, wherein: The thickness of the tunneling layer is 0.5-3 nm, and the thickness of the N-type doped crystalline silicon layer is 100-200 nm. Alternatively, the tunneling layer is a silicon oxide layer or a silicon carbide layer, and the thickness of the tunneling layer is 0.5-3 nm. Alternatively, the N-type doped crystalline silicon layer is one or a combination of N-type doped microcrystalline silicon layer and N-type doped polycrystalline silicon layer, and the thickness of the N-type doped crystalline silicon layer is 100-200 nm.
6. The solar cell according to any one of claims 1 to 5, characterized by: The solar cell further comprises a spacer between the P-type diffusion layer and the N-type tunneling passivation contact structure.
7. The solar cell of claim 6, wherein: The back surface of the spacer has a third textured structure, and the roughness of the third textured structure is greater than the roughness of the first textured structure. Alternatively, The front surface of the silicon substrate has a second textured structure, and the back surface of the spacer has a third textured structure, and the third textured structure is consistent with the second textured structure.
8. The solar cell of claim 6, wherein: The solar cell further comprises a back surface passivation layer and a back surface anti-reflection layer on the back surface of the P-type diffusion layer, the N-type tunneling passivation contact structure and the spacer, the first electrode contacts the P-type diffusion layer through the back surface anti-reflection layer and the back surface passivation layer, and the second electrode contacts the N-type doped crystalline silicon layer through the back surface anti-reflection layer and the back surface passivation layer.
9. The solar cell of claim 1, wherein: The solar cell further comprises a front surface passivation layer on the front surface of the silicon substrate and a front surface anti-reflection layer on the front surface of the front surface passivation layer.
10. The solar cell of claim 1, wherein: The bonding depth of the first electrode to the P-type diffusion layer is 1 / 2-1 / 3 of the depth of the P-type diffusion layer, and the bonding depth of the second electrode to the N-type doped crystalline silicon layer is 1 / 2-1 / 3 of the thickness of the N-type doped crystalline silicon layer.