Solar cell

Abstract

A solar cell comprises a P-type diffusion layer, an N-type tunneling passivation contact structure, a first electrode and a second electrode, wherein the P-type diffusion layer and the N-type tunneling passivation contact structure are located on the back face of a silicon substrate, the first electrode is located on the back face of the P-type diffusion layer, and the second electrode is located on the back face of the N-type tunneling passivation contact structure. The N-type tunneling passivation contact structure comprises a tunneling layer and an N-type doped crystalline silicon layer positioned on the back surface of the tunneling layer; the P-type diffusion layer comprises an electrode region and a non-electrode region, the surface of the electrode region is a suede, the surface of the non-electrode region is a plane, and the first electrode is in contact with the electrode region. In the solar cell provided by the utility model, the P-type diffusion layer is provided with the electrode region and the non-electrode region, and the surface of the non-electrode region is a plane, so that a good passivation effect can be realized, and the open-circuit voltage is improved; and the surface of the electrode area in contact with the first electrode is the suede, so that the contact resistance is small, the filling factor can be improved, and the battery efficiency is comprehensively improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to photovoltaic field especially relates to a solar cell with good metal contact. BACKGROUND

[0002] BC battery is full back electrode contact (full back electrode contact) crystalline silicon photovoltaic cell, its characteristics are that all grid lines of the positive surface of the battery are transferred to the back surface, the shading to incident light is greatly reduced, and the battery has the advantages of high efficiency, high optimization degree of grid lines, simple packaging, and attractive appearance. However, with the increase of process flow, the precision requirement of the process is improved, which leads to the increase of manufacturing cost and restricts the industrial development of BC battery.

[0003] Benefiting from the maturity of TOPCon battery process, TBC battery combining BC battery process and TOPCon battery technology becomes the most cost-effective BC battery route. Generally, P-poly is formed by LPCVD process and boron diffusion, and N-poly is formed by LPCVD process and phosphorus diffusion, so the demand for LPCVD equipment is large. In addition, the thickness of P-poly needs to provide a part for growing silicon oxide and a part for resisting the penetration of paste, so a relatively thick thickness is required, generally more than 200 nm; therefore, the process time is long.

[0004] Therefore, it is necessary to provide an improved solar cell to solve the above technical problems. CONTENT OF THE UTILITY MODEL

[0005] The utility model aims at at least solving one of the technical problems existing in the prior art, and provides a solar cell.

[0006] To achieve the above-mentioned one of the purposes of the utility model, the utility model adopts the following technical scheme:

[0007] A solar cell comprises a P-type diffusion layer and an N-type tunneling passivation contact structure located on the back surface of a silicon substrate, a first electrode located on the back surface of the P-type diffusion layer, and a second electrode located on the back surface of the N-type tunneling passivation contact structure; the N-type tunneling passivation contact structure comprises a tunneling layer and an N-type doped crystalline silicon layer located on the back surface of the tunneling layer; the P-type diffusion layer comprises an electrode area and a non-electrode area, the surface of the electrode area is a rough surface, the surface of the non-electrode area is a flat surface, and the first electrode is in contact with the electrode area.

[0008] In an embodiment, the surface of the electrode area is a pyramid rough surface, and the base width of the pyramid is 0.1 μm to 1 μm.

[0009] In an embodiment, the front surface of the silicon substrate is a rough surface, and the roughness of the front surface is not less than the roughness of the electrode area.

[0010] In one embodiment, the front surface of the silicon substrate is a pyramidal texture, and the base width of the pyramids is 1-5 μm; and / or the surface of the electrode region is a pyramidal texture, and the base width of the pyramids is 0.1-1 μm.

[0011] In one embodiment, the non-electrode region is located around the electrode region.

[0012] In one embodiment, the width of the electrode region is 5-25 μm.

[0013] In one embodiment, in the width direction of the first electrode, the electrode region is wider than the first electrode by 5-50 μm.

[0014] In one embodiment, the thickness of the tunneling layer is 0.5-3 nm, and the thickness of the N-type doped crystalline silicon layer is 50-200 nm.

[0015] In one embodiment, the tunneling layer is a silicon oxide layer or a silicon carbide layer, and the thickness of the tunneling layer is 0.5-3 nm.

[0016] In one embodiment, the N-type doped crystalline silicon layer is one or a combination of N-type doped microcrystalline silicon layer or N-type doped polycrystalline silicon layer, and the thickness of the N-type doped crystalline silicon layer is 50-200 nm.

[0017] In one embodiment, the P-type diffusion layer is higher than the N-type tunneling passivation contact structure, and the height difference between the P-type diffusion layer and the N-type tunneling passivation contact structure is 2-10 μm.

[0018] In one embodiment, the solar cell further comprises a spacer region between the P-type diffusion layer and the N-type tunneling passivation contact structure.

[0019] In one embodiment, the back surface of the spacer region is a planar structure.

[0020] In one embodiment, the back surface of the spacer region is a textured surface, and the roughness of the back surface of the spacer region is greater than the roughness of the electrode region.

[0021] In one embodiment, the back surface of the spacer region is a textured surface, and the front surface of the silicon substrate is a textured surface, and the roughness of the back surface of the spacer region is consistent with the roughness of the front surface of the silicon substrate.

[0022] In one embodiment, the spacer region is recessed from the back surface to the front surface of the silicon substrate, and the depth of the spacer region is greater than the diffusion depth of the P-type diffusion layer, or the depth of the spacer region is 1-20 μm; and / or, the width of the spacer region is 10-150 μm.

[0023] In an embodiment, the solar cell further comprises a back passivation layer and / or a back anti-reflection layer on the P-type diffusion layer, the N-type tunneling passivation contact structure, the back surface of the spacer region, the first electrode contacts the electrode region through the back passivation layer and / or the back anti-reflection layer, and the second electrode contacts the N-type doped silicon layer through the back passivation layer and / or the back anti-reflection layer; the bonding depth of the first electrode with the P-type diffusion layer is 1 / 2-1 / 3 of the depth of the P-type diffusion layer, and / or the bonding depth of the second electrode with the N-type doped silicon layer is 1 / 2-1 / 3 of the thickness of the N-type doped silicon layer.

[0024] The solar cell has the advantages that: the P-type diffusion layer is provided with an electrode region and a non-electrode region, the surface of the non-electrode region is a plane, good passivation effect can be realized, and the open circuit voltage is improved; the surface of the electrode region in contact with the first electrode is a rough surface, the contact resistance is small, the fill factor can be improved, and the battery efficiency is improved comprehensively. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 It is a structural schematic view of the solar cell of the preferred embodiment of the utility model;

[0026] Figure 2 It is a structural schematic view of the solar cell of the preferred embodiment of the utility model; Figure 1 It is a local enlarged view of A in the middle.

[0027] Wherein, 100-solar cell, 1-silicon substrate, 2-P-type diffusion layer, 21-electrode region, 22-non-electrode region, 3-N-type tunneling passivation contact structure, 31-tunneling layer, 32-N-type doped silicon layer, 4-spacer region, 5-back passivation layer, 6-back anti-reflection layer, 71-first electrode, 72-second electrode, 8-front passivation layer, 9-front anti-reflection layer. DETAILED DESCRIPTION

[0028] The utility model will be described in detail below in combination with the specific embodiment shown in the drawings. But these embodiments do not limit the utility model, the conversion of structure, method or function made by the ordinary skilled in the art according to these embodiments is included in the protection scope of the utility model.

[0029] In each drawing of the utility model, in order to facilitate the illustration, the size of some structures or parts will be exaggerated relative to other structures or parts, therefore, only for illustrating the basic structure of the subject of the utility model.

[0030] For the convenience of description, the light receiving surface (main light receiving surface) of the silicon substrate 1 is defined as the front surface, and the back light surface (secondary light receiving surface) of the silicon substrate 1 is defined as the back surface with the silicon substrate 1 as a reference. The film layer located on the front surface of the silicon substrate 1 is collectively referred to as a front surface film layer, the surface of the front surface film layer away from or facing away from the silicon substrate 1 is the front surface, and the surface of the front surface film layer facing the silicon substrate 1 is the back surface. The film layer located on the back surface of the silicon substrate is collectively referred to as a back surface film layer, the surface of the back surface film layer facing the silicon substrate 1 is the front surface, and the surface of the back surface film layer away from or facing away from the silicon substrate is the back surface.

[0031] The inventors have found that in the back surface cell, the passivation effect and metal contact of the P region and the N region have a great influence on the efficiency of the cell; and under normal circumstances, the metal contact and the passivation effect cannot be compatible, resulting in poor cell efficiency.

[0032] The utility model aims at providing a solar cell 100, through the improvement of the structure of the back surface of the cell, the optimization of passivation and metal lower contact, improve the efficiency of the cell.

[0033] Please refer to Figures 1-2 As shown in the figure, the solar cell 100 includes a silicon substrate 1, a P-type diffusion layer 2 and an N-type tunneling passivation contact structure 3 located on the back surface of the silicon substrate 1, a first electrode 71 located on the back surface of the P-type diffusion layer 2, and a second electrode 72 located on the back surface of the N-type tunneling passivation contact structure 3.

[0034] For the convenience of expression, the P-type diffusion layer 2 is usually referred to as the P region, and the N-type tunneling passivation contact structure 3 is usually referred to as the N region.

[0035] In the utility model, the silicon substrate 1 adopts an N-type silicon wafer, and the resistivity is 0.3Ω·cm~7Ω·cm, preferably 1Ω·cm~3.5Ω·cm.

[0036] The P-type diffusion layer 2 is formed by directly diffusing a P-type doping source from the back surface of the silicon substrate 1 inward, and a PN junction is formed in the silicon substrate 1, which is beneficial to the separation, transmission and collection of carriers. And by replacing the traditional LPCVD process and boron expansion two-step forming method with a one-step diffusion process, the process flow is simple, and the cost is low.

[0037] In the utility model, the P-type doping elements include but are not limited to boron (B), aluminum (Al) or gallium (Ga).

[0038] In an embodiment, the P-type diffusion layer 2 is a boron diffusion layer (boron junction) formed by directly diffusing boron from the back surface of the silicon substrate 1 inward. The surface doping concentration of the boron diffusion layer is 1E18cm -3 ~1E20cm -3 , the square resistance is 100ohm / sq~500ohm / sq, and the junction depth is 0.3μm~2μm.

[0039] The P-type diffusion layer 2 includes electrode regions 21 and non-electrode regions 22, and the first electrode 71 is in contact with the electrode regions 21.

[0040] The surface of the electrode regions 21 is a rough surface, and the specific surface area is large, which can increase the metal contact area with the first electrode 71, reduce the contact resistance, and thus improve the fill factor and short-circuit current, and comprehensively improve the battery efficiency. The surface of the non-electrode regions 22 is a flat surface, and the surface defects are few, so the surface recombination is less; and the flat surface is conducive to forming a continuous, dense and uniform passivation film layer, which can achieve good passivation effect and improve the open-circuit voltage.

[0041] In an embodiment, the electrode regions 21 have a small rough surface, which does not produce too many recombination points on the premise of improving metal contact; and the roughness difference between the small rough surface and the non-electrode regions 22 is small, and the influence on the surface film deposition process is small.

[0042] For example, the surface of the electrode regions 21 is a pyramid rough surface, and the base width size of the pyramid is 0.1 μm to 1 μm. The purpose of the rough surface of the electrode regions 21 is to improve the metal contact on the premise of not damaging the passivation effect too much, rather than to improve the light limitation of the region.

[0043] In an embodiment, the front surface of the silicon substrate 1 is a rough surface, and the roughness of the electrode regions 21 is smaller than that of the front surface of the silicon substrate 1. For example, the base width size of the pyramid of the electrode regions 21 is smaller than that of the pyramid of the front surface.

[0044] In an embodiment, the surface of the electrode regions 21 is a pyramid rough surface, and the base width size of the pyramid is 0.1 μm to 1 μm; and / or the front surface of the silicon substrate 1 is a pyramid rough surface, and the base width size of the pyramid of the front surface is 1 μm to 5 μm.

[0045] The positional relationship between the electrode regions 21 and the non-electrode regions 22 includes but is not limited to the following cases.

[0046] In an embodiment, the non-electrode regions 22 are located around the electrode regions 21. On the one hand, a good passivation effect is formed around the metal contact, and on the other hand, the electrode regions 21 and the N-type tunneling passivation contact structure 3 are separated by the non-electrode regions 22, which is conducive to forming a uniform tunneling layer 31.

[0047] The relationship between the electrode regions 21 and the first electrode 71 is that the width of the electrode regions 21 is consistent with the width of the first electrode 71, or the electrode regions 21 are wider than the first electrode 71, which can ensure that the electrode falls within the electrode regions even if there is an error or poor precision when the first electrode 71 is prepared.

[0048] In one embodiment, the width of the electrode region 21 is 5 μm to 25 μm.

[0049] In another embodiment, the width of the electrode region 21 is 5 μm to 50 μm wider than the first electrode 71 in the width direction of the first electrode 71, i.e. the width of the edge of the electrode region 21 not covered by the first electrode 71 is 5 μm to 50 μm. The width of the electrode region 21 is designed to ensure that the first electrode 71 is completely within the electrode region 21, and the proportion of the electrode region 21 to the entire P-type diffusion layer 2 is not too large, ensuring the passivation effect of the non-electrode region.

[0050] The N-type tunneling passivation contact structure 3 comprises a tunneling layer 31 and an N-type doped crystalline silicon layer 32 on the back of the tunneling layer 31. The N-type doping element in the N-type doped crystalline silicon layer 32 is preferably phosphorus (P), arsenic (As), etc.

[0051] The tunneling layer 31 is a silicon oxide layer or a silicon carbide layer, and the thickness of the tunneling layer 31 is 0.5 nm to 3 nm.

[0052] The N-type doped crystalline silicon layer 32 is one or a combination of N-type doped microcrystalline silicon layer or N-type doped polycrystalline silicon layer. The thickness of the N-type doped crystalline silicon layer 32 is 50 nm to 200 nm, preferably 80 nm to 120 nm.

[0053] In one embodiment, the N-type doped crystalline silicon layer 32 is a phosphorus-doped polycrystalline silicon layer, and the doping concentration is 1E19 cm -3 to 1E21 cm -3 , preferably 5E19 cm -3 to 5E20 cm-3; and the thickness is 50 nm to 200 nm.

[0054] In addition, the solar cell 100 further comprises a separation region 4 between the P-type diffusion layer 2 and the N-type tunneling passivation contact structure 3. The separation region 4 is recessed from the back to the front of the silicon substrate 1, separating the P-type diffusion layer 2 and the N-type tunneling passivation contact structure 3 to prevent leakage.

[0055] In one embodiment, the depth L1 of the separation region 4 is greater than the diffusion depth of the P-type diffusion layer 2. Alternatively, the depth L1 of the separation region 4 is 1 μm to 20 μm, preferably 5 μm to 10 μm. This depth can insulate the P-type diffusion layer 2 and the N-type tunneling passivation contact structure 3 to avoid leakage.

[0056] In one embodiment, the width L2 of the separation region 4 is 10 μm to 150 μm, preferably 50 μm to 100 μm. In the extension direction of the silicon substrate 1, the P-type diffusion layer 2 and the N-type tunneling passivation contact structure 3 are isolated to avoid leakage.

[0057] In an embodiment, the P-type diffusion layer 2 on both sides of the interval region 4 is higher than the N-type tunneling passivation contact structure 3, and the side of the P-type diffusion layer 2 can also absorb sunlight, thereby increasing the light receiving area, and the light can be reflected multiple times at the interval region 4, which is conducive to improving the light absorption. In an embodiment, the height difference between the P-type diffusion layer 2 and the N-type tunneling passivation contact structure 3 is 2 μm to 10 μm, and preferably 4 μm to 7 μm.

[0058] In addition, the back surface of the interval region 4 is a planar structure, and the surface defects and surface recombination are small, and the planar structure is conducive to forming a continuous, dense and uniform passivation film layer in the subsequent process, so that a good passivation effect can be achieved.

[0059] The back surface of the interval region 4 can also be a rough surface, which can improve the light absorption at the interval region 4 and improve the cell efficiency.

[0060] In an embodiment, the roughness of the interval region 4 is greater than the roughness of the electrode region 21, so as to ensure the light limiting effect at the interval region 4.

[0061] In another embodiment, the roughness of the interval region 4 is consistent with the roughness of the front surface of the silicon substrate 1, that is, the rough surface of the interval region 4 is consistent with the rough surface of the front surface of the silicon substrate 1, and the two can be formed in the same process, thereby simplifying the process flow.

[0062] The solar cell 100 further comprises a back passivation layer 5 and / or a back anti-reflection layer 6 on the back surface. When both the film layers are provided, the back anti-reflection layer 6 is located on the back surface of the back passivation layer 5.

[0063] The back passivation layer 5 is used to passivate the P region, the N region and the interval region 4, reduce the interface recombination and improve the open circuit voltage. In the present application, the back passivation layer 5 is a silicon oxide layer or an aluminum oxide layer, and the thickness of the back passivation layer 5 is 2 nm to 7 nm, and preferably 3 nm to 6 nm.

[0064] The back anti-reflection layer 6 is used to reduce the light reflection on the back surface, and in particular in a double-glass assembly, the cell efficiency can be significantly improved. In the present application, the back anti-reflection layer 6 is one or more stacked films of silicon nitride, silicon oxynitride and silicon oxide, and the thickness is 60 nm to 130 nm, and preferably 60 nm to 90 nm.

[0065] The first electrode 71 is located in the electrode region 21 of the P-type diffusion layer 2 and only contacts the electrode region 21, so as not to penetrate the P-type diffusion layer 2 and directly contact the silicon substrate 1, thereby ensuring the metal contact of the P-type diffusion layer 2 and reducing the metal recombination.

[0066] The second electrode 72 is in contact with the N-type doped crystalline silicon layer 32 and does not penetrate the tunneling layer 31 to contact the silicon substrate 1, thereby reducing metal recombination.

[0067] Preferably, the first electrode 71 and the second electrode 72 are metal electrodes processed by a laser-assisted sintering process, which greatly reduces the J0 of the metal under the P-type diffusion layer 2.

[0068] The laser-assisted sintering process can deepen the bonding depth of the first electrode 71 and the P-type diffusion layer 2. In an embodiment, the bonding depth of the first electrode 71 and the P-type diffusion layer 2 is 1 / 2 to 1 / 3 of the diffusion depth of the P-type diffusion layer 2, which ensures that the first electrode 71 is in metal contact with the P-type diffusion layer 2 and reduces the contact resistance.

[0069] The laser-assisted sintering process can deepen the bonding depth of the second electrode 72 and the N-type doped crystalline silicon layer 32. In an embodiment, the bonding depth of the second electrode 72 and the N-type doped crystalline silicon layer 32 is 1 / 2 to 1 / 3 of the thickness of the N-type doped crystalline silicon layer 32, which ensures that the second electrode 72 forms a good metal contact with the N-type doped crystalline silicon layer 32, reduces the contact resistance, and overall improves the cell efficiency.

[0070] The solar cell 100 further comprises a front passivation layer 8 on the front surface thereof, which passivates the front surface of the silicon substrate 1 and reduces surface recombination.

[0071] Preferably, the front passivation layer 8 and the back passivation layer 5 have the same material and thickness, and can be deposited on both surfaces in the same process without the need for two separate depositions, thereby simplifying the process flow.

[0072] In an embodiment, the front passivation layer 8 is preferably an aluminum oxide layer with a thickness of 2 nm to 7 nm, preferably 3 nm to 6 nm.

[0073] The solar cell 100 further comprises a front anti-reflective layer 9 on the front surface of the front passivation layer 8, which reduces the light reflectivity of the front surface and improves light absorption, thereby improving cell efficiency.

[0074] Preferably, the front anti-reflective layer 9 and the back anti-reflective layer 6 have the same material and thickness, and can be deposited on both surfaces in the same process without the need for two separate depositions, thereby simplifying the process flow.

[0075] In an embodiment, the anti-reflective layer is one or more of a silicon nitride, silicon oxynitride, and silicon oxide stacked film with a thickness of 60 nm to 130 nm, preferably 60 nm to 90 nm.

[0076] Hereinafter, a preparation method of a solar cell 100 will be provided to obtain the solar cell 100 with the above structure.

[0077] Step 1, texturing: N-type silicon wafers with resistivity of 0.3Ω·cm-7Ω·cm are used to form a first textured structure by double-side texturing.

[0078] The first textured structure is formed by using a first texturing alkali solution, and the first textured structure is a pyramid texture with a tower base width of 0.1μm-1μm.

[0079] The first texturing alkali solution includes an alkali solution with a mass concentration of 0.5%-5% and an additive with a mass concentration of 0.5%-5%, and the texturing time is 100s-500s and the temperature is 60°C-80°C. The texturing alkali solution is NaOH or KOH, and the additive for texturing is tetramethylammonium hydroxide (TMAH).

[0080] Step 2, forming a first mask layer on the back surface: an oxide layer such as silicon oxide or silicon oxynitride is prepared on the back surface, and the thickness is 1nm-50nm, preferably 1nm-20nm. The oxide layer can be prepared by thermal growth, such as high-temperature oxygenation, or by wet oxidation, such as ozone water or high-temperature hydrogen peroxide, or by CVD deposition.

[0081] Step 3, removing the first mask layer except the back electrode area 21. The first mask layer except the electrode area 21 is removed by laser slotting.

[0082] The laser slotting process used in each process step of the utility model is selected from but not limited to any one of the following: ultraviolet picosecond laser, spot power is 3W-20W, spot diameter is 100μm-150μm, laser frequency is 500kHz-600kHz, scanning speed is 40m / s-80m / s. Green picosecond laser, spot power is 5W-50W, spot diameter is 100μm-500μm, laser frequency is 500kHz-600kHz, scanning speed is 40m / s-80m / s.

[0083] Step 4, removing the first textured structure except the back electrode area 21 to form a flat tower base, and only retaining the first textured structure at the electrode area 21. Add polishing alkali solution in the slot machine to remove the first textured structure of the laser slotted area and form a polished surface. Then use hydrofluoric acid to remove the first mask layer on the electrode area 21.

[0084] Step 5, backside doping to form P-type diffusion layer: by means of tube diffusion, BCl3 or BBr3 is used as diffusion source, temperature is controlled at 900-1100°C, boron diffusion layer is formed, sheet resistance is 50-400 ohm / sq, BSG layer thickness is 30-150 nm, surface concentration is 1E18-1E20 cm -3 . -3 , junction depth is 0.3-2 μm.

[0085] Step 6, removing BSG layer outside electrode area 21: laser slotting is performed in N area and interval area 4, BSG layer is removed.

[0086] Step 7, removing boron junction outside electrode area 21: first, second mask layer of front side and side around diffusion is removed; then, polishing is performed to remove diffusion layer of front side and laser slotting area.

[0087] First, chain type equipment is used to inject hydrofluoric acid solution to remove BSG layer of front side and side around diffusion; then, tank type machine is used to inject polishing alkali solution to remove boron junction of front side around diffusion and boron junction of backside laser slotting area, alkali polishing is performed on front side and backside laser slotting area, tower base width size of laser slotting area is 15 μm, boron junction and BSG layer of backside non-laser slotting area (electrode area 21) are reserved.

[0088] Step 8, preparing N-type tunneling passivation contact structure 3 on backside: taking phosphorus doping as an example, the following two ways can be used:

[0089] ① Way one: PECVD+annealing way. In-situ doping way is used to grow tunneling layer and phosphorus-doped poly layer, PSG layer is formed to protect poly layer.

[0090] If tunneling layer is SiOx, thickness is preferably 1-2 nm, N-poly layer thickness is preferably 100-200 nm; mask thickness can be in the range of 10-50 nm. Then, annealing activation is performed: annealing treatment is performed in high temperature annealing furnace, annealing temperature is in the range of 880-980°C, after annealing, doped amorphous silicon is converted into doped polysilicon, doped amorphous silicide is converted into doped polysilicide, phosphorus is activated, tunneling passivation contact structure is formed on backside, N-poly layer phosphorus doping surface concentration is in the range of 1E19-1E21 cm -3 .

[0091] ② Way two, LPCVD+phosphorus expansion way, if tunneling layer is SiOx, thickness is preferably 1-2 nm, N-poly layer thickness is preferably 100-200 nm; mask thickness can be in the range of 10-50 nm; then, high temperature phosphorus expansion is performed at 850-920°C, PSG layer thickness is 10-50 nm.

[0092] Step 9, removing PSG layer outside N region: according to the laser slotting of the P region and the interval region 4 on the back, the PSG layer is removed to expose the N-poly layer.

[0093] Step 10, removing N-poly layer outside N region: first, removing the PSG layer around the front and side; then, removing the N-poly layer of the front and the laser slotting area on the back.

[0094] First, the chain device is advanced into the hydrofluoric acid solution to remove the PSG layer around the front and side; then, the tank device is advanced into the second etching alkali solution to remove the poly layer around the front and the N-poly layer of the laser slotting area on the back; and the interval region 4 on the front and back is etched to form a textured surface, and the size of the tower base of the pyramid is 1 μm-5 μm. Finally, the hydrofluoric acid is used to remove the PSG layer of the N region on the back and the BSG layer of the P region, and RCA cleaning is performed if necessary.

[0095] The second etching alkali solution includes an alkali solution with a mass concentration of 0.5%-5% and an additive with a mass concentration of 1%-10%, and the etching time is 100 s-800 s and the temperature is 65°C-90°C.

[0096] Step 11, front and back passivation layer 5 preparation: an aluminum oxide passivation layer with a thickness of 5 nm is deposited on the front and back by ALD process. 11, electrode preparation: a first electrode 71 is formed at the electrode area 21 of the P region by screen printing and sintering process, a second electrode 72 is formed in the N region, and a back main grid is also formed on the back.

[0097] Step 12, laser-assisted sintering: laser-assisted sintering is performed on the auxiliary grid electrodes of the P region and the N region on the back.

[0098] In the conventional TBC battery, the P region and the N region are both poly, and the J0 level under the metal can be lowered to a low level of about 50 fA / cm 2 ; and in this application, one of the P region and the N region is a diffusion layer, and the laser-assisted sintering technology is superimposed on the first electrode 71 and the second electrode 72, which can improve the contact between silver and silicon in the electrode, reduce the contact resistance, greatly reduce the J0 level of the diffusion region, improve the open circuit voltage and can slightly improve the short circuit current.

[0099] In the laser-assisted sintering process, the bias voltage is 5V-20V, the laser wavelength is 1064nm or 532nm, and the laser width is 1mm-2mm.

[0100] In summary, in the solar cell, the P-type diffusion layer 2 is provided with the electrode area 21 and the non-electrode area 22, the surface of the non-electrode area 22 is a plane, good passivation effect can be realized, and the open circuit voltage is improved; and the surface of the electrode area 21 in contact with the first electrode 71 is a suede surface, the contact resistance is small, the fill factor can be improved, and the battery efficiency is comprehensively improved.

[0101] It should be understood that, although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the specification is described in this way only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be appropriately combined to form other embodiments that those skilled in the art can understand.

[0102] The series of detailed descriptions listed above are only specific descriptions of the feasible embodiments of the utility model, and are not used to limit the protection scope of the utility model, and equivalent embodiments or changes made without departing from the spirit of the utility model art should be included in the protection scope of the utility model.

Claims

1. A solar cell comprising a P-type diffusion layer and an N-type tunneling passivation contact structure on the backside of a silicon substrate, a first electrode on the backside of the P-type diffusion layer, a second electrode on the backside of the N-type tunneling passivation contact structure; the N-type tunneling passivation contact structure comprising a tunneling layer, an N-type doped crystalline silicon layer on the backside of the tunneling layer; characterized in that, The P-type diffusion layer comprises an electrode region and a non-electrode region, a surface of the electrode region is a rough surface, and a surface of the non-electrode region is a flat surface.

2. The solar cell of claim 1, wherein: The surface of the electrode region is a pyramid rough surface, and a base width of the pyramid is 0.1 μm to 1 μm.

3. The solar cell of claim 1, wherein: The front surface of the silicon substrate is a rough surface, and a roughness of the front surface is not less than a roughness of the electrode region; or The front surface of the silicon substrate is a pyramid rough surface, and a base width of the pyramid of the front surface is 1 μm to 5 μm; and / or the surface of the electrode region is a pyramid rough surface, and a base width of the pyramid is 0.1 μm to 1 μm.

4. The solar cell of claim 1, wherein: The non-electrode region is located around the electrode region; or The width of the electrode region is 5 μm to 25 μm; or In a width direction of the first electrode, the electrode region is wider than the first electrode by 5 μm to 50 μm.

5. The solar cell of claim 1, wherein: The thickness of the tunneling layer is 0.5 nm to 3 nm, and the thickness of the N-type doped crystalline silicon layer is 50 nm to 200 nm; or The tunneling layer is a silicon oxide layer or a silicon carbide layer, and the thickness of the tunneling layer is 0.5 nm to 3 nm; or The N-type doped crystalline silicon layer is one or a combination of N-type doped microcrystalline silicon layers and N-type doped polycrystalline silicon layers, and the thickness of the N-type doped crystalline silicon layer is 50 nm to 200 nm.

6. The solar cell of claim 1, wherein: The P-type diffusion layer is higher than the N-type tunneling passivation contact structure, and a height difference between the P-type diffusion layer and the N-type tunneling passivation contact structure is 2 μm to 10 μm.

7. The solar cell of claim 1, wherein: The solar cell further comprises a spacing region located between the P-type diffusion layer and the N-type tunneling passivation contact structure.

8. The solar cell of claim 7, wherein: The back surface of the spacing region is a flat structure; or The back surface of the spacing region is a rough surface, and a roughness of the back surface of the spacing region is greater than a roughness of the electrode region; or The back surface of the spacing region is a rough surface, the front surface of the silicon substrate is a rough surface, and a roughness of the back surface of the spacing region is consistent with a roughness of the front surface of the silicon substrate.

9. The solar cell of claim 7, wherein: The spacing region is recessed from the back surface to the front surface of the silicon substrate, and The depth of the spacing region is greater than a diffusion depth of the P-type diffusion layer, or the depth of the spacing region is 1 μm to 20 μm; and / or The width of the spacing region is 10 μm to 150 μm.

10. The solar cell of claim 7, wherein: The solar cell further comprises a back surface passivation layer and / or a back surface anti-reflection layer located on the back surface of the P-type diffusion layer, the N-type tunneling passivation contact structure, and the spacing region, the first electrode passes through the back surface passivation layer and / or the back surface anti-reflection layer to contact the electrode region, and the second electrode passes through the back surface passivation layer and / or the back surface anti-reflection layer to contact the N-type doped crystalline silicon layer. The bonding depth of the first electrode to the P-type diffusion layer is 1 / 2 to 1 / 3 of the depth of the P-type diffusion layer, and / or the bonding depth of the second electrode to the N-type doped crystalline silicon layer is 1 / 2 to 1 / 3 of the thickness of the N-type doped crystalline silicon layer.

Images