Semiconductor structure and semiconductor device
By designing JFET and IGBT cell structures in semiconductor structures and utilizing gate control of the PN junction depletion region, the problems of high conduction and turn-off losses in superjunction semiconductor devices are solved, realizing low-loss and high-performance semiconductor devices.
Patent Information
- Application Number
- CN202423032872.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-11-21
- Estimated Expiration
- 2034-12-09
AI Technical Summary
Existing superjunction semiconductor devices have low conductivity modulation levels in the on state, resulting in large saturation voltages. At the same time, they have large tail currents, long turn-off times, and high turn-off losses when turned off.
In semiconductor structures, JFET and IGBT cell structures are designed. By controlling the expansion and contraction of the depletion region of the PN junction through the gate, the turn-off and turn-on of the carrier channels can be achieved. Combined with trench gate design, the integration density can be improved and the leakage current can be reduced.
It achieves low conduction loss and low turn-off loss, improves switching speed and integration, reduces leakage current, and optimizes the performance of semiconductor structure.
Smart Images
Figure CN223571579U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a semiconductor device. BACKGROUND
[0002] In the current super junction semiconductor device, since the P column region provides a hole extraction channel directly connected to the P-type base region, the level of conductivity modulation of the super junction semiconductor device under forward conduction is affected, and the semiconductor device with medium doping concentration N column and P column shows a larger saturation voltage.
[0003] In order to suppress the extraction of holes from the P column to the P-type base region in the on state, enhance the conductivity modulation of the drift region, and set the super junction semiconductor device with floating P column, the P column and the P-type base region are separated, and the direct outflow of holes from the P column to the P-type base region is suppressed. However, since the P column is not used as a hole channel, the device has a larger tail current when turned off, a longer turn-off time, and a high turn-off loss. CONTENT OF THE INVENTION
[0004] The main purpose of the present application is to provide a semiconductor structure and a semiconductor device to at least solve the problem that the super junction semiconductor device in the prior art cannot achieve low conduction loss and low turn-off loss.
[0005] To achieve the above object, according to one aspect of the present application, a semiconductor structure is provided, comprising: an epitaxial layer having a first conductivity type, the epitaxial layer comprising opposite first and second surfaces; a JFET structure located in the epitaxial layer, comprising a first implantation region and two first well regions, the two first well regions being located on two sides of the first implantation region along a first direction and respectively contacting side edges of the first implantation region, the first implantation region having a second conductivity type, the first well regions having the first conductivity type, the first direction being parallel to the first and second surfaces; an IGBT cell structure comprising two second well regions, a second implantation region, two third well regions, two fourth well regions and a gate, wherein the two second well regions are spaced apart and located on a side of the first well regions away from the first implantation region, the second implantation region is located between the two second well regions, the epitaxial layer has a trench between the second well regions and the second implantation region, the third well regions and the fourth well regions are located in the second well regions one by one, the fourth well regions are located on a side of the third well regions away from the second implantation region and contact the third well regions, the gate is located in the trench, on a side of the second implantation region away from the second surface and on surfaces of the two first well regions away from the second surface, the third well regions have the first conductivity type, the second well regions, the second implantation region and the fourth well regions have the second conductivity type, and surfaces of the first well regions, the second well regions, the second implantation region, the third well regions and the fourth well regions away from the second surface are part of the first surface.
[0006] Optionally, the IGBT cell structure further comprises: a gate oxide layer located between the inner wall of the trench and the gate, on the surface of the second implantation region away from the second surface, between the second well regions and the first well regions and on the surface of the gate away from the first surface.
[0007] Optionally, the doping concentration of the second well regions is greater than or equal to the doping concentration of the first implantation region and the second implantation region, the doping concentration of the fourth well regions is greater than the doping concentration of the second well regions, and the doping concentration of the first well regions and the third well regions is greater than the doping concentration of the epitaxial layer.
[0008] Optionally, the semiconductor structure further comprises: a buffer layer located on the second surface, the buffer layer having the first conductivity type, and the doping concentration of the buffer layer being greater than the doping concentration of the epitaxial layer; and a substrate located on a surface of the buffer layer away from the second surface, the substrate having the second conductivity type.
[0009] Optionally, the semiconductor structure further comprises: a first metal layer located on a surface of the substrate away from the buffer layer.
[0010] Optionally, the surface of the first implant region away from the second surface is part of the first surface, and the surface of the first implant region away from the first surface is part of the second surface.
[0011] Optionally, the surface of the first implant region away from the second surface is part of the first surface, and the depth of the first implant region is less than the thickness of the epitaxial layer, and the thickness of the epitaxial layer is the distance between the first surface and the second surface.
[0012] Optionally, there are multiple JFET structures, and there are multiple IGBT cell structures, and the JFET structures and the IGBT cell structures are alternately and spacedly arranged.
[0013] Optionally, the semiconductor structure further comprises a second metal layer located on the part of the surface of the third well region and the fourth well region away from the second surface.
[0014] According to another aspect of the present application, a semiconductor device is provided, comprising any one of the semiconductor structures.
[0015] By applying the technical solution of the present application, the first well region of the JFET structure is connected with the gate, the first well region of the JFET structure is controlled by the gate, the PN junction depletion region in the JFET structure is enlarged when the semiconductor structure is turned on, the carrier channel of the first implant region is turned off, the carrier in the epitaxial layer is prevented from flowing out through the first implant region, and thus the conduction loss of the semiconductor structure is ensured to be low; and the first well region of the JFET structure is controlled by the gate, the PN junction depletion region in the JFET structure is reduced when the semiconductor structure is turned off, the carrier channel of the first implant region is turned on, the carrier in the epitaxial layer is allowed to flow out through the first implant region, and thus the turn-off loss of the semiconductor structure is ensured to be low, the problem that the super-junction semiconductor device in the prior art cannot realize low conduction loss and low turn-off loss is solved, and the technical effect that the semiconductor structure has low conduction loss and low turn-off loss is achieved. In addition, the switching function of the semiconductor structure can be realized by the IGBT cell structure, the trench gate design can allow more components to be integrated in a smaller area, the integration of the semiconductor structure is improved, the leakage current of the semiconductor structure in the turn-off state can be effectively reduced, the channel length and the parasitic capacitance can be reduced, and thus the switching speed of the semiconductor structure is improved, and the performance of the semiconductor structure is further ensured to be good. BRIEF DESCRIPTION OF DRAWINGS
[0016] The accompanying drawings, which form a part of the present application, are used to provide further understanding of the present application, and the illustrative embodiments of the present application and their description serve the purpose of explaining the present application. In the drawings:
[0017] Figure 1 A three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present application is shown;
[0018] Figure 2 A three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present application is shown; Figure 1 A side view of the semiconductor structure shown;
[0019] Figure 3 A front view of the semiconductor structure shown; Figure 1 A front view of the semiconductor structure shown;
[0020] Figure 4 A sectional view of the semiconductor structure along the dotted line AA' in Figure 2 and Figure 3 ;
[0021] Figure 5 (a) shows a front view of a structure obtained after step S1 in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;
[0022] Figure 5 (b) shows a side view of a structure obtained after step S1 in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;
[0023] Figure 6 (a) shows a front view of a structure obtained after step S2 in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;
[0024] Figure 6 (b) shows a side view of a structure obtained after step S2 in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;
[0025] Figure 7 (a) shows a front view of a structure obtained after step S3 in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;
[0026] Figure 7 (b) shows a front view of a structure obtained after step S3 in a method for manufacturing a semiconductor structure provided in an embodiment of the present application.
[0027] In the above drawings, the following reference signs are used:
[0028] 10, epitaxial layer; 11, JFET structure; 12, first implantation region; 13, first well region; 14, gate; 15, IGBT cell structure; 16, second well region; 17, second implantation region; 18, third well region; 19, fourth well region; 20, gate oxide layer; 21, buffer layer; 22, substrate; 23, metal layer; 25, initial gate oxide layer. DETAILED DESCRIPTION
[0029] It should be noted that the embodiments and features of the embodiments in the present application can be combined with each other without conflict. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.
[0030] In order for those skilled in the art to better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.
[0031] It should be noted that the terms "first", "second" and the like in the specification and claims of the present application and the drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.
[0032] As introduced in the background, there is a problem in the prior art that the super-junction semiconductor device cannot realize low on-state loss and low off-state loss. To solve the technical problem, the embodiments of the present application provide a semiconductor structure and a semiconductor device.
[0033] The technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application.
[0034] The embodiments of the present application provide a semiconductor structure, Figure 1 Exemplarily, a three-dimensional structure schematic diagram of a semiconductor structure is shown as follows, Figure 1 As shown in the figure, the semiconductor structure comprises:
[0035] An epitaxial layer 10 having a first conductivity type, the epitaxial layer 10 comprising opposite first and second surfaces;
[0036] Specifically, the first conductivity type can be P-type or N-type. The epitaxial layer 10 can play a voltage resistance role.
[0037] The JFET structure 11, located in the epitaxial layer 10, comprises a first implanted region 12 and two first well regions 13, the two first well regions 13 are located on two sides of the first implanted region 12 along a first direction and respectively contact the side edges of the first implanted region 12, the first implanted region 12 has a second conductivity type, the first well regions 13 have a first conductivity type, and the first direction is parallel to the first surface and the second surface.
[0038] Specifically, the first implanted region 12 and the first well regions 13 in the JFET structure 11 form PN junctions. The two first well regions 13 are located on two side edges of the first implanted region 12. The first conductivity type is different from the second conductivity type. In the case that the first conductivity type is P type, the first implanted region 12 is also called N pillar, and the epitaxial layer 10 is P-epitaxial layer; in the case that the first conductivity type is N type, the first implanted region 12 is also called P pillar, and the epitaxial layer 10 is N-epitaxial layer.
[0039] The IGBT cell structure 15 comprises two second well regions 16, a second implanted region 17, two third well regions 18, two fourth well regions 19 and a gate 14, wherein the two second well regions 16 are spaced apart and located on a side of the first well regions 13 away from the first implanted region 12, the second implanted region 17 is located between the two second well regions 16, the epitaxial layer 10 has a trench between the second well regions 16 and the second implanted region 17, the third well regions 18 and the fourth well regions 19 are one-to-one located in the second well regions 16, the fourth well regions 19 are located on a side of the third well regions 18 away from the second implanted region 17 and contact the third well regions 18, the gate 14 is located in the trench, on a side of the second implanted region 17 away from the second surface and on surfaces of the two first well regions 13 away from the second surface, the third well regions 18 have the first conductivity type, the second well regions 16, the second implanted region 17 and the fourth well regions 19 have the second conductivity type, and surfaces of the first well regions 13, the second well regions 16, the second implanted region 17, the third well regions 18 and the fourth well regions 19 away from the second surface are respectively part of the first surface.
[0040] Specifically, the two second well regions 16 are located on the side of the first well region 13 away from the first implant region 12. In the case that the first conductivity type is P-type, the second implant region 17 is also called N pillar, and the epitaxial layer 10 is P-epitaxial layer; in the case that the first conductivity type is N-type, the second implant region 17 is also called P pillar, and the epitaxial layer 10 is N-epitaxial layer. The trench separates the second implant region 17 from the second well region 16. The depth of the trench is greater than the depth of the second well region 16, the depth refers to the width in the direction perpendicular to the first direction. For the third well region 18 and the fourth well region 19 located in the same second well region 16, the fourth well region 19 is located on the surface of the third well region 18 away from the second implant region 17. The gate 14 of the IGBT cell structure 15 is located in the trench and on the surface of the second implant region 17, that is, the gate 14 is a trench gate structure.
[0041] By the embodiment, the first implant region of the second conductivity type and the first well region of the second conductivity type are formed in the epitaxial layer of the first conductivity type to obtain the JFET structure, and the IGBT cell structure including the second well region, the second implant region, the third well region, the fourth well region and the gate is formed in the epitaxial layer, wherein the first well region is located on two sides of the first implant region, the surface of the first well region away from the second surface of the epitaxial layer is part of the first surface of the epitaxial layer, and the gate is located on the first surface of the epitaxial layer and contacts the first well region to realize the connection of the gate and the first well region. In the present application, the first well region of the JFET structure is connected with the gate, the first well region of the JFET structure is controlled by the gate to expand the PN junction depletion region in the JFET structure when the semiconductor structure is turned on, to realize the turn-off of the carrier channel of the first implant region, to avoid the carrier in the epitaxial layer flowing out through the first implant region, thereby ensuring that the turn-on loss of the semiconductor structure is low; and the first well region of the JFET structure is controlled by the gate to shrink the PN junction depletion region in the JFET structure when the semiconductor structure is turned off, to realize the turn-on of the carrier channel of the first implant region, to realize the carrier in the epitaxial layer flowing out through the first implant region, thereby ensuring that the turn-off loss of the semiconductor structure is low, to solve the problem that the super-junction semiconductor device in the prior art cannot realize low turn-on loss and low turn-off loss, to achieve the technical effect that the turn-on loss and the turn-off loss of the semiconductor structure are low. In addition, the switching function of the semiconductor structure can be realized by the IGBT cell structure, the design of the trench gate can allow more components to be integrated in a smaller area, to improve the integration of the semiconductor structure, to effectively reduce the leakage current of the semiconductor structure in the off state, to also reduce the channel length and the parasitic capacitance, thereby improving the switching speed of the semiconductor structure, to further ensure that the performance of the semiconductor structure is good.
[0042] Specifically, when the gate 14 is connected to a turn-on voltage to turn on the semiconductor structure, the semiconductor structure enters a turn-on process, the PN junction depletion region in the JFET structure 11 expands to overlap, thereby clamping the first implanted region 12, so that the channel of the first implanted region 12 is turned off, the carriers in the epitaxial layer 10 cannot flow out through the first implanted region 12, ensuring a high carrier concentration in the epitaxial layer 10 and a low on-resistance of the semiconductor structure, thereby ensuring a low on-state loss of the semiconductor structure; when the gate 14 is connected to a voltage lower than the turn-on voltage, the semiconductor structure enters an off process, the PN junction depletion region in the JFET structure 11 shrinks, so that the channel of the first implanted region 12 is turned on, the carriers in the epitaxial layer 10 are extracted to the external circuit of the semiconductor structure through the first implanted region 12, so that the number and lifetime of the minority carriers in the epitaxial layer 10 are both low after the semiconductor structure is turned off, ensuring a fast turn-off of the semiconductor structure, a small tail current and a low off-state loss.
[0043] Further, when the turn-on voltage of the semiconductor structure is a positive voltage, the first conductivity type is N type and the second conductivity type is P type, i.e., the epitaxial layer 10 is an N-type epitaxial layer 10, the first well region 13 is an N-type well region, and the first implanted region 12 is a P-type drift region; when the gate 14 is connected to the positive voltage, the semiconductor structure is turned on, the PN junction depletion region in the JFET structure 11 expands to clamp the first implanted region 12, and the carrier channel is turned off; when the gate 14 is connected to a negative voltage or 0, the semiconductor structure is turned off, the PN junction depletion region in the JFET structure 11 shrinks, and the carrier channel is turned on. When the turn-on voltage is a negative voltage, by adjusting the specific types of the first conductivity type and the second conductivity type, the same effect as when the turn-on voltage is a positive voltage can be achieved.
[0044] In this application, the first implanted region 12 and the epitaxial layer 10, and the second implanted region 17 and the epitaxial layer 10 all constitute super-junction structures, which can form an electric field in the horizontal direction and the vertical direction, thereby improving the withstand voltage of the semiconductor structure and reducing the on-resistance of the semiconductor structure.
[0045] Figure 2 An exemplary side view of the semiconductor structure is shown, Figure 1 An exemplary front view of the semiconductor structure is shown, Figure 3 An exemplary side view of the semiconductor structure is shown, Figure 1 An exemplary front view of the semiconductor structure is shown, Figure 4 An exemplary sectional view of the semiconductor structure obtained along the dotted line AA' in Figure 2 and Figure 3 is shown. As Figure 2 , Figure 3 and Figure 4As shown, the IGBT cell structure 15 further comprises a gate oxide layer 20, which is located between the inner wall of the trench and the gate 14, on the surface of the second implantation region 17 away from the second surface, between the second well region 16 and the first well region 13, and on the surface of the gate 14 away from the first surface. That is, the gate oxide layer 20 is located between the third well region 18 and the gate 14, between the second implantation region 17 and the gate 14, on the surface of the second implantation region 17, between the second well region 16 and the first well region 13, and on the surface of the gate 14. The gate and the semiconductor region are isolated by the gate oxide layer, so that the gate voltage can control the conductivity of the semiconductor region, and the current is adjusted.
[0046] In some other optional embodiments, the doping concentration of the second well region 16 is greater than or equal to the doping concentration of the second implantation region 17, and the doping concentration of the fourth well region 19 is greater than the doping concentration of the second well region 16. By setting the doping concentration of the fourth well region, the doping concentration of the second well region, and the doping concentration of the second implantation region to be sequentially reduced, the flow direction of the carriers can be further controlled, and the formation of the conductive channel can be realized.
[0047] In addition, the doping concentration of the second well region 16 is greater than or equal to the doping concentration of the first implantation region 12. The doping concentration of the first well region 13 is greater than the doping concentration of the epitaxial layer 10, and the doping concentration of the third well region 18 is greater than the doping concentration of the epitaxial layer 10. In this embodiment, by setting the doping concentration of the first well region to be greater than the doping concentration of the epitaxial layer, the performance of the PN junction in the JFET structure can be further ensured to be good. By setting the doping concentration of the third well region to be greater than the doping concentration of the epitaxial layer, the charge density of the third well region can be further ensured to be high, so that the current driving capability of the IGBT cell structure is strong; the electric field intensity of the third well region can be further ensured to be strong, so that the withstand voltage capability of the IGBT cell structure is good; and the thermal conductivity of the third well region can be further ensured to be high, which is helpful for heat conduction and diffusion, so that the thermal effect of the device is low.
[0048] In addition, in order to simplify the manufacturing process of the semiconductor structure, the doping concentration of the first implantation region 12 and the doping concentration of the second implantation region 17 can be the same. The doping concentration of the first well region 13 and the doping concentration of the third well region 18 can be the same.
[0049] In a specific application process, the first well region 13, the third well region 18, and the fourth well region 19 are heavily doped regions, the second well region 16 is a medium doped region, and the epitaxial layer 10, the first implantation region 12, and the second implantation region 17 are lightly doped regions.
[0050] Specifically, the third well region 18 and the fourth well region 19 serve as the emitter of the IGBT cell structure 15, which controls the conduction channel between the emitter and the collector by changing the gate voltage, when the gate voltage reaches a certain threshold, the channel opens, and the current can flow from the collector to the emitter; when the gate voltage is below the threshold, the channel is closed, and the current is blocked.
[0051] In the case where the semiconductor structure of the present application is an IGBT device, as shown in Figures 1 to 4 The semiconductor structure further comprises: a buffer layer 21 on the second surface, the buffer layer 21 has the first conductivity type, and the doping concentration of the buffer layer 21 is greater than that of the epitaxial layer 10; a substrate 22 on the surface of the buffer layer 21 away from the second surface, the substrate 22 has the second conductivity type. In this embodiment, the substrate serves as the collector region of the semiconductor structure, and the buffer layer can form a low electric field region between the gate and the collector of the IGBT device, which helps to reduce the electric field concentration, reduce the risk of breakdown of the device under high voltage, reduce the carrier injection near the gate, reduce the on-state loss of the device, and improve the efficiency of the IGBT device; it can improve the withstand voltage capability of the IGBT device, make it work more stably and reliably under high voltage, and also help to improve the switching speed of the IGBT device and reduce the loss in the switching process.
[0052] In one embodiment, the surface of the first implant region away from the second surface is part of the first surface, and the surface of the first implant region away from the first surface is part of the second surface. That is, the depth of the first implant region is the same as the thickness of the substrate, and the first implant region divides the substrate into multiple regions, and the first implant region and these regions are arranged alternately, and the first implant region and the epitaxial layer constitute a super-junction type structure.
[0053] In another embodiment, as shown in Figures 1 to 4 The surface of the first implant region 12 away from the second surface is part of the first surface, the depth of the first implant region 12 is less than the thickness of the epitaxial layer 10, and the thickness of the epitaxial layer is the distance between the first surface and the second surface. That is, the depth of the first implant region is less than the thickness of the substrate, and the first implant region and the epitaxial layer constitute a semi-super junction type structure.
[0054] On this basis, the surface of the second implantation region away from the second surface can be part of the first surface, and the surface of the second implantation region away from the first surface can be part of the second surface, so that the second implantation region and the epitaxial layer constitute a super-junction type structure. In addition, the surface of the second implantation region away from the second surface can be part of the first surface, and the depth of the second implantation region can be less than the thickness of the epitaxial layer 10, the thickness of the epitaxial layer being the distance between the first surface and the second surface, so that the second implantation region and the epitaxial layer constitute a semi-super-junction structure.
[0055] The skilled person in the art can flexibly set the number of the JFET structure and the IGBT cell structure. In the embodiment, as shown in Figures 1 to 4 The JFET structure has multiple, the IGBT cell structure has multiple, and the JFET structure and the IGBT cell structure are alternately and spaced apart.
[0056] As shown in Figures 1 to 4 The semiconductor structure further includes a first metal layer 23 located on the surface of the substrate 22 away from the buffer layer 21. In addition, the semiconductor structure can further include a second metal layer (not shown in the figure) located on part of the surface of the third well region and the fourth well region away from the second surface.
[0057] The material of the epitaxial layer includes but is not limited to single crystal silicon material, epitaxial silicon material, and semiconductor materials such as silicon carbide material; the material of the gate includes but is not limited to polycrystalline silicon material; and the material of the gate oxide layer includes but is not limited to silicon oxide material.
[0058] The skilled person in the art can flexibly set the depth, width, and injection mode, injection depth, and injection width of each well region of the first implantation region and the second implantation region according to actual design needs.
[0059] Taking the first conductive type as N type and the second conductive type as P type as an example for description, as shown in Figures 1 to 4As shown, the P column (i.e. the first injection area 12) of the super junction is formed around the IGBT cell structure 15, and the N-type area (i.e. the first well area 13) is formed at both sides of the P column of the IGBT cell structure 15. The N-type area is completely separated from the front and rear P well areas (i.e. the second well area 16) by the gate oxide layer 20, so that the N-type area and the P column in the middle form a JFET structure 11. In the JFET structure 11, the upper end of the N-type area is connected to the gate 14, and the JFET structure 11 is controlled by the gate 14. When the gate 14 is connected to a positive voltage to turn on the IGBT device, the PN junction structure in the JFET structure 11 is connected to the positive voltage, the depletion region of the PN junction is expanded, the depletion regions at both ends of the P column are expanded to overlap, thereby clamping the P column in the middle, and the minority carriers at the bottom of the epitaxial layer 10 cannot flow out through the P column. The carrier concentration of the epitaxial layer 10 is increased, thereby reducing the on-resistance of the device and reducing the turn-on loss. When the gate voltage is zero or negative, the device enters the off process, the depletion region of the PN junction in the JFET structure 11 is reduced, thereby opening the hole channel of the P column, and the hole carriers in the epitaxial layer 10 are extracted through the hole channel of the P column. The hole carriers pass through the P column channel to enter the external circuit through the metal layer, reducing the number of minority carriers at the bottom of the device, thereby making the device turn off faster, the tail current is smaller, and the turn-off loss is reduced. The application solves the problem of high conduction loss of the traditional SJ IGBT, and solves the problem of large tail current, long turn-off time and high turn-off loss of the improved floating SJ IGBT during turn-off.
[0060] The application also provides a manufacturing method of the semiconductor structure, comprising the following steps:
[0061] Step S1, sequentially forming a buffer layer 21 and an N-type epitaxial layer 10 on a substrate 22, and performing ion implantation on the epitaxial layer 10 to obtain a P-type first injection area 12 and a second injection area 17, to obtain a structure as shown in Figure 5 , wherein Figure 5 (a) shows a front view of the structure, Figure 5 (b) shows a side view of the structure, and the epitaxial layer 10 can be an epitaxial layer formed by epitaxial technology;
[0062] Step S2, performing ion implantation on a P-type second well area 16, an N-type third well area 18 and a P-type fourth well area 19 to obtain a structure as shown in Figure 6 , wherein Figure 6 (a) shows a front view of the structure, Figure 6 (b) shows a side view of the structure;
[0063] Step S3, groove etching is performed, and growth of gate oxide material is performed, then part of the gate oxide material is removed, a groove is formed between the second well region and the first implanted region, a trench is formed between the third well region and the second implanted region, the remaining gate oxide material forms an initial gate oxide layer 25, and epitaxial layer material is backfilled in the groove and ion implantation is performed to form an N-type first well region, after completion, annealing treatment is performed on the structure to activate the implanted ions, after annealing, gate material is filled in the trench, and the gate material is deposited on the surface of the first well region to form a gate 14, to obtain a structure as shown in Figure 7 (a) shows a front view of the structure, Figure 7 (b) shows a side view of the structure. Figure 7
[0064] Step S4, the gate 14 is covered with gate oxide material to obtain a gate oxide layer 20, and a metal layer 23 is formed on the surface of the substrate 22 away from the buffer layer 21, to obtain a structure as shown in Figures 1 to 4 .
[0065] Embodiments of the present application also provide a semiconductor device, which comprises any of the semiconductor structures.
[0066] The semiconductor device comprises the semiconductor structure, the first well region of the JFET structure is connected with the gate, the first well region of the JFET structure is controlled by pressure through the gate, the PN junction depletion region in the JFET structure is enlarged when the semiconductor structure is turned on, the carrier channel of the first implanted region is turned off, so that the carriers in the epitaxial layer flow out through the first implanted region, thereby ensuring that the conduction loss of the semiconductor structure is low; and the first well region of the JFET structure is controlled by pressure through the gate, the PN junction depletion region in the JFET structure is reduced when the semiconductor structure is turned off, the carrier channel of the first implanted region is turned on, the carriers in the epitaxial layer flow out through the first implanted region, thereby ensuring that the turn-off loss of the semiconductor structure is low, solving the problem that the super-junction semiconductor device in the prior art cannot realize low conduction loss and low turn-off loss, achieving the technical effect that the semiconductor device has low conduction loss and low turn-off loss, and ensuring that the overall loss of the semiconductor device is low. In addition, the IGBT cell structure can realize the switching function of the semiconductor structure, the trench gate design can allow more components to be integrated in a smaller area, improve the integration of the semiconductor device, effectively reduce the leakage current of the semiconductor device in the off state, and also reduce the channel length and parasitic capacitance, thereby improving the switching speed of the semiconductor device, and further ensuring that the performance of the semiconductor device is good.
[0067] It should also be noted that the terms "comprising", "comprises", "including", "includes" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus including the element.
[0068] From the above description, it can be seen that the embodiments described in the present application achieve the following technical effects:
[0069] 1) The semiconductor structure of the present application forms a first injection region of a second conductive type and a first well region of a second conductive type in an epitaxial layer of a first conductive type, obtains a JFET structure, and forms an IGBT cell structure including the second well region, the second injection region, the third well region, the fourth well region and the gate in the epitaxial layer, wherein the first well region is located on two side edges of the first injection region, the surface of the first well region away from the second surface of the epitaxial layer is part of the first surface of the epitaxial layer, the gate is located on the first surface of the epitaxial layer and contacts the first well region, realizing the connection of the gate and the first well region. In the present application, the first well region of the JFET structure is connected with the gate, the first well region of the JFET structure is controlled by the gate, the PN junction depletion region in the JFET structure is controlled to expand when the semiconductor structure is turned on, the carrier channel of the first injection region is turned off, thereby avoiding the carrier in the epitaxial layer flowing out through the first injection region, so as to ensure that the semiconductor structure has low conduction loss; and the first well region of the JFET structure is controlled by the gate, the PN junction depletion region in the JFET structure is controlled to shrink when the semiconductor structure is turned off, the carrier channel of the first injection region is turned on, thereby realizing the carrier in the epitaxial layer flowing out through the first injection region, so as to ensure that the semiconductor structure has low turn-off loss, solving the problem that the super-junction semiconductor device in the prior art cannot realize low conduction loss and low turn-off loss, and achieving the technical effect that the semiconductor structure has low conduction loss and low turn-off loss. In addition, the switching function of the semiconductor structure can be realized through the IGBT cell structure, the design of the trench gate can allow more components to be integrated in a smaller area, improve the integration of the semiconductor structure, effectively reduce the leakage current of the semiconductor structure in the off state, and also reduce the channel length and parasitic capacitance, thereby improving the switching speed of the semiconductor structure, and further ensuring that the semiconductor structure has good performance.
[0070] 2) The semiconductor device of this application includes a semiconductor structure. In the semiconductor structure, the first well region of the JFET structure is connected to the gate. By applying voltage control to the first well region of the JFET structure through the gate, the depletion region of the PN junction in the JFET structure is controlled to expand when the semiconductor structure is turned on, thereby turning off the carrier channel of the first injection region and preventing the carriers in the epitaxial layer from flowing out through the first injection region, thus ensuring low conduction loss of the semiconductor structure. Conversely, by applying voltage control to the first well region of the JFET structure through the gate, the depletion region of the PN junction in the JFET structure is controlled to shrink when the semiconductor structure is turned off, thereby turning on the carrier channel of the first injection region and enabling the carriers in the epitaxial layer to flow out through the first injection region, thus ensuring low turn-off loss of the semiconductor structure. This solves the problem that existing superjunction semiconductor devices cannot achieve both low conduction and turn-off losses, achieving the technical effect of low conduction and turn-off losses in semiconductor devices and ensuring low overall loss of the semiconductor device. Furthermore, the switching function of semiconductor structures can be realized through the IGBT cell structure. The trench gate design allows more components to be integrated in a smaller area, improving the integration of semiconductor devices. It can effectively reduce the leakage current of semiconductor devices in the off state, and also reduce the channel length and parasitic capacitance, thereby improving the switching speed of semiconductor devices and further ensuring the better performance of semiconductor devices.
[0071] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A semiconductor structure, characterized in that, include: An epitaxial layer having a first conductivity type, the epitaxial layer comprising opposing first and second surfaces; The JFET structure, located in the epitaxial layer, includes a first injection region and two first well regions. The two first well regions are located on both sides of the first injection region along a first direction and are in contact with the side of the first injection region respectively. The first injection region has a second conductivity type, and the first well regions have the first conductivity type. The first direction is parallel to the first surface and the second surface. An IGBT cell structure includes two second well regions, a second implanted region, two third well regions, two fourth well regions, and a gate. The two second well regions are spaced apart and located on the side of the first well region away from the first implanted region. The second implanted region is located between the two second well regions. The epitaxial layer has a trench located between the second well regions and the second implanted region. The third and fourth well regions are each located in a corresponding position within the second well regions. The fourth well region is located on the side of the third well region away from the second implanted region and is in contact with the third well region. The gate is located in the trench, on the side of the second implanted region away from the second surface, and on the surfaces of the two first well regions away from the second surface. The third well region has a first conductivity type, and the second well region, the second implanted region, and the fourth well region have a second conductivity type. The surfaces of the first well region, the second well region, the second implanted region, the third well region, and the fourth well region away from the second surface are each portions of the first surface.
2. The semiconductor structure according to claim 1, characterized in that, The IGBT cell structure also includes: A gate oxide layer is located between the inner wall of the trench and the gate, on the surface of the second implantation region away from the second surface, between the second well region and the first well region, and on the surface of the gate away from the first surface.
3. The semiconductor structure according to claim 1, characterized in that, The doping concentration of the second well region is greater than or equal to the doping concentration of the first implanted region and the second implanted region, the doping concentration of the fourth well region is greater than the doping concentration of the second well region, and the doping concentration of the first well region and the third well region is greater than the doping concentration of the epitaxial layer.
4. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The semiconductor structure also includes: A buffer layer is located on the second surface, the buffer layer having the first conductivity type, and the doping concentration of the buffer layer is greater than the doping concentration of the epitaxial layer; A substrate, located on the surface of the buffer layer away from the second surface, having the second conductivity type.
5. The semiconductor structure according to claim 4, characterized in that, The semiconductor structure also includes: A first metal layer is located on the surface of the substrate away from the buffer layer.
6. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The surface of the first injection region that is away from the second surface is a portion of the first surface, and the surface of the first injection region that is away from the first surface is a portion of the second surface.
7. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The surface of the first injection region that is away from the second surface is a portion of the first surface. The depth of the first injection region is less than the thickness of the epitaxial layer. The thickness of the epitaxial layer is the distance between the first surface and the second surface.
8. The semiconductor structure according to any one of claims 1 to 3, characterized in that, There are multiple JFET structures and multiple IGBT cell structures, and the JFET structures and IGBT cell structures are arranged alternately at intervals.
9. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The semiconductor structure also includes: The second metal layer is located on the portion of the third and fourth well regions that is away from the second surface.
10. A semiconductor device, characterized in that, include: The semiconductor structure according to any one of claims 1 to 9.