Tandem type thin film transistor and display module
By using a series-connected thin-film transistor structure and voltage timing control, the leakage problem of thin-film transistors in cholesteric liquid crystal displays was solved, thus improving the display effect.
Patent Information
- Application Number
- CN202520000992.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-11-28
- Filing Date
- 2025-01-02
- Publication Date
- 2025-11-21
- Estimated Expiration
- 2035-01-02
AI Technical Summary
Existing thin-film transistors are prone to leakage in low-frequency driven cholesterol liquid crystal displays, resulting in poor display quality.
A series-connected thin-film transistor structure is adopted. By connecting the first and second thin-film transistors in series, the leakage path is extended, and the occurrence of leakage is controlled by setting different voltages and timings.
It effectively suppressed the leakage current phenomenon of thin-film transistors and improved the display effect of cholesterol liquid crystal displays.
Smart Images
Figure CN223582280U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a thin film transistor, in particular to a series connection type thin film transistor. BACKGROUND
[0002] In prior art, active matrix (AM) display adopts thin film transistor (TFT) technology to enhance, usually a thin film transistor is used to drive liquid crystal. For the display using cholesteric liquid crystal, it is low frequency driving, and the time of frequency update is longer than that of general liquid crystal display. Therefore, for amorphous silicon thin film transistor, it is easy to cause leakage, and voltage drop phenomenon occurs, thereby affecting the display effect of liquid crystal.
[0003] Therefore, how to inhibit the leakage of thin film transistor through the improvement of structure design has become one of the important topics to be solved in this industry. CONTENT OF THE UTILITY MODEL
[0004] Therefore, the utility model provides a series connection type thin film transistor, which is suitable for a display module with cholesteric liquid crystal. The series connection type thin film transistor is located in a pixel. The series connection type thin film transistor comprises a first thin film transistor and a second thin film transistor.
[0005] The first thin film transistor has a first source, a first drain and a first gate. The second thin film transistor has a second source, a second drain and a second gate. The second source of the second thin film transistor is electrically connected to the first drain of the first thin film transistor. The first source of the first thin film transistor is electrically connected to a signal line of the pixel. The first gate of the first thin film transistor and the second gate of the second thin film transistor are respectively electrically connected to a first gate line of the pixel.
[0006] According to a feasible embodiment, the series connection type thin film transistor further comprises a third thin film transistor. The third thin film transistor has a third source, a third drain and a third gate. The third source of the third thin film transistor is electrically connected to the second drain of the second thin film transistor. The third gate of the third thin film transistor is connected to the first gate line of the pixel.
[0007] According to a feasible embodiment, in the vertical direction, the projection area of the first thin film transistor is greater than that of the second thin film transistor.
[0008] The utility model discloses still provide a series connection formula thin film transistor, be applicable to the display module with cholesteric liquid crystal, series connection formula thin film transistor corresponds to be located in a pixel, series connection formula thin film transistor includes: first thin film transistor and second thin film transistor. First thin film transistor has first source, first drain and first gate. Second thin film transistor has second source, second drain and second gate, and the second source of second thin film transistor is electrically connected in series in the first drain of first thin film transistor. The first source of first thin film transistor is electrically connected to the signal line of pixel, and the first gate of first thin film transistor is electrically connected the first gate line of pixel. The second gate of second thin film transistor is electrically connected the second gate line of pixel.
[0009] According to a feasible embodiment, the first gate and the second gate are the same layer structure.
[0010] According to a feasible embodiment, the first thin film transistor further includes a first channel layer, and the second thin film transistor further includes a second channel layer, and the distance between the first channel layer and the second channel layer is greater than or equal to 1 µm.
[0011] According to a feasible embodiment, the distance between the first gate of the first thin film transistor and the second gate of the second thin film transistor is greater than or equal to 1 µm.
[0012] According to a feasible embodiment, in the first thin film transistor, the distance between the first drain and the first source defines a first distance, and the first distance is greater than or equal to 1 µm.
[0013] According to a feasible embodiment, in the first thin film transistor, the distance between the first drain and the first source defines a first distance. In the second thin film transistor, the distance between the second drain and the second source defines a second distance, and the second distance is different from the first distance.
[0014] According to a feasible embodiment, in the first thin film transistor, in a first direction, the distance between the first drain and the first source defines a first distance; in a second direction orthogonal to the first direction, the first drain and the first source are equal in length, defining a first length, and the ratio of the first distance to the first length is less than or equal to 50%.
[0015] The utility model discloses still provide a kind of display module, it includes series connection formula thin film transistor.
[0016] The utility model discloses still provide a kind of display module, it includes: series connection formula thin film transistor, organic layer and light-transmitting electrode layer. Organic layer is set on series connection formula thin film transistor. Light-transmitting electrode layer is set on organic layer.
[0017] The utility model discloses still provide a kind of display module, including series connection formula thin film transistor and black matrix layer. Black matrix layer is set on series connection formula thin film transistor.
[0018] One of the beneficial effects of the utility model lies in that the series connection type thin film transistor provided by the utility model can inhibit the leakage of the thin film transistor, prolong the leakage path and inhibit the problem of leakage by applying to the cholesterol liquid crystal through the technical scheme of "the second source electrode of the second thin film transistor is electrically connected to the first drain electrode of the first thin film transistor" and "the first source electrode of the first thin film transistor is electrically connected to the signal line of the pixel, and the first gate electrode of the first thin film transistor and the second gate electrode of the second thin film transistor are respectively electrically connected to the gate line of the pixel".
[0019] One of the beneficial effects of the utility model lies in that the display module provided by the utility model has the series connection type thin film transistor, thus having the technical effects mentioned above.
[0020] For further understanding of the features and technical contents of the utility model, please refer to the following detailed description and drawings of the utility model, however, the drawings provided are only used for providing reference and illustration, and are not used to limit the utility model. BRIEF DESCRIPTION OF DRAWINGS
[0021] FIG. 1A It is a schematic diagram of one embodiment of the series connection type thin film transistor of the utility model.
[0022] FIG. 1B It is a schematic diagram of one embodiment of the series connection type thin film transistor of the utility model. FIG. 1A
[0023] FIG. 2A It is a schematic diagram of one embodiment of the series connection type thin film transistor of the utility model.
[0024] FIG. 2B It is a schematic diagram of one embodiment of the series connection type thin film transistor of the utility model. FIG. 2A
[0025] It is a schematic diagram of one embodiment of the series connection type thin film transistor of the utility model. FIG. 3
[0026] It is a schematic diagram of one embodiment of the series connection type thin film transistor of the utility model. FIG. 4
[0027] It is a schematic diagram of one embodiment of the series connection type thin film transistor of the utility model. FIG. 5A
[0028] It is a schematic diagram of one embodiment of the series connection type thin film transistor of the utility model. FIG. 5B FIG. 5A It is a schematic diagram of one embodiment of the series connection type thin film transistor of the utility model.
[0029] FIG. 5C It is a voltage and timing relationship schematic diagram of the embodiment shown in the figure. FIG. 5A It is a voltage and timing relationship schematic diagram of the embodiment shown in the figure.
[0030] FIG. 5D For FIG. 5A The voltage and timing relationship schematic diagram of the embodiment.
[0031] FIG. 6A to FIG. 6G , respectively, the schematic diagram of an embodiment of the first thin film transistor of the utility model.
[0032] FIG. 7 to FIG. 10 , respectively, the schematic diagram of an embodiment of the first thin film transistor and the second thin film transistor in series of the utility model.
[0033] FIG. 11 The schematic diagram of an embodiment of the series connection type thin film transistor of the utility model.
[0034] FIG. 12 The schematic diagram of an embodiment of the series connection type thin film transistor of the utility model.
[0035] FIG. 13 The structural schematic diagram of an embodiment of the display module of the utility model.
[0036] FIG. 14 The structural schematic diagram of an embodiment of the display module of the utility model. DETAILED DESCRIPTION
[0037] The following is to illustrate the embodiment of the series connection type thin film transistor and the display module disclosed by the utility model through specific embodiments, and the advantages and effects of the utility model can be understood by the person skilled in the art from the disclosed content of the specification. The utility model can be implemented or applied through other different specific embodiments, and each detail in the specification can be modified and changed based on different viewpoints and applications without departing from the concept of the utility model. In addition, the drawings of the utility model are only simple schematic illustrations, not the depiction according to the actual size, and the prior declaration is made. The following embodiment will further illustrate the related technical content of the utility model, but the disclosed content is not used to limit the protection scope of the utility model.
[0038] It should be understood that although the terms such as "first", "second", "third" and the like can be used herein to describe various components or signals, these components or signals should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one signal from another signal. In addition, the term "or" used herein can include any one or more combinations of the associated listed items as the case may be.
[0039] Please refer to FIG. 1A and FIG. 1B , FIG. 1A The schematic diagram of an embodiment of the series connection type thin film transistor of the utility model.FIG. 1B For FIG. 1A A simple circuit diagram of the embodiment shown in FIG. 1. The series thin film transistor is suitable for a display module with cholesteric liquid crystal. The series thin film transistor is located in a pixel P (a region surrounded by the first gate line Ga1, the third gate line Ga2, the first signal line Da1 and the second signal line Da2). The series thin film transistor includes a first thin film transistor 1 and a second thin film transistor 2. The first thin film transistor 1 has a first source 11, a first drain 12 and a first gate 13. The second thin film transistor 2 has a second source 21, a second drain 22 and a second gate 23. The second source 21 of the second thin film transistor 2 is electrically connected to the first drain 12 of the first thin film transistor 1. The first source 11 of the first thin film transistor 1 is electrically connected to the signal line (the first signal line Da1) of the pixel P. The first gate 13 of the first thin film transistor 1 and the second gate 23 of the second thin film transistor 2 are respectively electrically connected to the first gate line Ga1 of the pixel P. By means of the series connection of the double thin film transistors, the leakage path can be extended, and the occurrence of leakage can be inhibited.
[0040] Please refer to FIG. 2A and FIG. 2B , FIG. 2A A schematic diagram of an embodiment of the series thin film transistor of the utility model. FIG. 2B For FIG. 2A A simple circuit diagram of the embodiment shown in FIG. 1. According to the embodiment, the series thin film transistor further includes a third thin film transistor 3 having a third source 31, a third drain 32, a third gate 33 and a third channel layer 34. The third source 31 of the third thin film transistor 3 is electrically connected to the second drain 22 of the second thin film transistor 2. The third gate 33 of the third thin film transistor 3 is connected to the first gate line Ga1 of the pixel P. With this structure, the leakage path of the thin film transistor can be further extended, and the occurrence of leakage can be further inhibited.
[0041] Please refer to FIG. 3 A schematic diagram of an embodiment of the series thin film transistor of the utility model. According to the embodiment, there are a vertical direction D1, a first direction D2 and a second direction D3, which are orthogonal to each other. In the vertical direction D1 projection, the projection area of the first thin film transistor 1 is greater than that of the second thin film transistor 2. The occurrence of leakage depends on the size of the thin film transistor. The user can set the first thin film transistor 1 and the second thin film transistor 2 with different sizes according to the specifications and actual needs. The utility model has no limitation (for details, see other embodiments described below).
[0042] Please refer to FIG. 4Figure 1 is a schematic diagram of a first embodiment of the series connection thin film transistor according to the present application. In this embodiment, the first distance L1 between the first drain 12 and the first source 11 of the first thin film transistor 1 is defined. The second distance L2 between the second drain 22 and the second source 21 of the second thin film transistor 2 is also defined. The second distance L2 is different from the first distance L1. In some embodiments, the first distance L1 is greater than or equal to 1 µm.
[0043] Figure 2 is a schematic diagram of a second embodiment of the series connection thin film transistor according to the present application. FIG. 5A to FIG. 5D , FIG. 5A Figure 3 is a schematic diagram of a third embodiment of the series connection thin film transistor according to the present application. FIG. 5B Figure 4 is a simple circuit diagram of the embodiment shown in Figure 1. FIG. 5A Figure 5 is a voltage and timing diagram of the embodiment shown in Figure 1. FIG. 5C Figure 6 is a voltage and timing diagram of the embodiment shown in Figure 2. FIG. 5A Figure 7 is a voltage and timing diagram of the embodiment shown in Figure 3. FIG. 5D Figure 8 is a voltage and timing diagram of the embodiment shown in Figure 4. FIG. 5A Figure 9 is a voltage and timing diagram of the embodiment shown in Figure 5. The first thin film transistor 1 has a first source 11, a first drain 12, and a first gate 13. The second thin film transistor 2 has a second source 21, a second drain 22, and a second gate 23. The second source 21 of the second thin film transistor 2 is electrically connected in series to the first drain 12 of the first thin film transistor 1. The first source 11 of the first thin film transistor 1 is electrically connected to a signal line of a pixel P. The first gate 13 of the first thin film transistor 1 is electrically connected to a first gate line Ga1 of the pixel P. The second gate 23 of the second thin film transistor 2 is electrically connected to a second gate line Ga3 of the pixel P. According to this embodiment, two gate lines (the first gate line Ga1 and the second gate line Ga3) are used. Different voltages and timings can be used to make it more difficult for leakage to occur. For example, in the case of FIG. 5C Figure 10 is a voltage and timing diagram of the embodiment shown in Figure 6. The voltage VH1 and the voltage VL1 are the highest voltage and the lowest voltage, respectively, for opening the first gate line Ga1. The opening time is T1. The voltage VH2 and the voltage VL2 are the highest voltage and the lowest voltage, respectively, for opening the second gate line Ga3. The opening time is T2. The voltage DV is the voltage of the first signal line Da1. In this embodiment, the voltage VH1 can be the same as or different from the voltage VH2. The voltage VL1 can be the same as or different from the voltage VL2. The opening time T1 can be the same as or different from the opening time T2. For example, in the case of FIG. 5DFor example, in this embodiment, the first gate line Ga1 and the second gate line Ga3 are opened more than twice for each frequency. In the first gate line Ga1, the first opening time is T1a, and the highest voltage and the lowest voltage of the opening are voltage VH1a and voltage VL1a, respectively. The second opening time is T1b, and the highest voltage and the lowest voltage of the opening are voltage VH1b and voltage VL1b, respectively. In the second gate line Ga3, the first opening time is T2a, and the highest voltage and the lowest voltage of the opening are voltage VH2a and voltage VL2a, respectively. The second opening time is T2b, and the highest voltage and the lowest voltage of the opening are voltage VH2b and voltage VL2b, respectively. Among them, voltage VH1a and voltage VH2a can be the same or different. Voltage VL1a and voltage VL1b can be the same or different. Voltage VH2a and voltage VH2b can be the same or different. Voltage VL1b and voltage VL2b can be the same or different. The opening time T1a and the opening time T2a can be the same or different. The opening time T1b and the opening time T2b can be the same or different. However, it should be noted that the opening time T1b and the opening time T2b cannot overlap in time, otherwise the first thin film transistor 1 and the second thin film transistor 2 can be fully opened, which may cause abnormal signal.
[0044] Please refer to FIG. 6A to FIG. 6G , respectively, are schematic diagrams of an embodiment of the first thin film transistor 1 of the utility model. It should be noted that although it is shown as the first thin film transistor 1, the second thin film transistor 2 can also be the architecture of these drawings. FIG. 6A to FIG. 6C The embodiment shown is generally referred to as the first type, in which the first drain 12 and the first source 11 can be T-shaped or straight (vertically or horizontally). FIG. 6D to FIG. 6E The embodiment shown is generally referred to as the second type, in which the first thin film transistor 1 has a U-shaped first drain 12 or a first source 11. FIG. 6F to FIG. 6G The embodiment shown is generally referred to as the third type, in which the first thin film transistor 1 has a J-shaped first drain 12 or a first source 11.
[0045] Please refer to FIG. 7 to FIG. 10 , respectively, are schematic diagrams of an embodiment of the first thin film transistor 1 and the second thin film transistor 2 in series of the utility model, and please refer again to FIG. 6A to FIG. 6G . As shown in FIG. 7 , the first thin film transistor 1 and the second thin film transistor 2 are each connected in series in the first type. As shown in FIG. 8 , the first thin film transistor 1 and the second thin film transistor 2 are each connected in series in the first type and the second type. As shown in FIG. 9 , the first thin film transistor 1 and the second thin film transistor 2 are each connected in series in the first type and the third type. As shown in FIG. 10As shown, the first thin film transistor 1 and the second thin film transistor 2 are each in series connection in a third mode. In other words, the utility model does not limit the mode in which the first thin film transistor 1 and the second thin film transistor 2 are connected in series, and the mode is set according to user requirements or specifications.
[0046] According to another embodiment FIG. 7 As shown in the embodiment, according to the embodiment, the distance between the first gate 13 of the first thin film transistor 1 and the second gate 23 of the second thin film transistor 2 is greater than or equal to 1 µm.
[0047] As shown in FIG. 11 and FIG. 12 are respectively schematic diagrams of a series connection type thin film transistor according to an embodiment of the utility model. According to FIG. 11 As shown in the embodiment, when the signals of the first gate 13 and the second gate 23 are the same, the first gate 13 and the second gate 23 can be integrated together (as the same layer structure), so that the use area can be saved and the area of the pixel P region can be increased. As shown in FIG. 12 As shown, if the signals of the first drain 12 and the second source 21 are the same, they can also be integrated together, so that the use area can be saved and the area of the pixel P region can be increased.
[0048] According to another embodiment FIG. 11 As shown, the first thin film transistor 1 is taken as an example, according to the embodiment, in the first thin film transistor 1, the distance between the first drain 12 and the first source 11 in the first direction D2 is a first distance L1; in the second direction D3 orthogonal to the first direction D2, the first drain 12 and the first source 11 are equal in length, the length is defined as a first length W1, and the ratio of the first distance L1 to the first length W1 is less than or equal to 50%. Since the greater the first length W1, the stronger the charging capacity, and the smaller the first distance L1, the weaker the charging capacity. Therefore, the ratio of the first distance L1 to the first length W1 is designed to be less than or equal to 50%, which has a better effect on suppressing leakage. According to some embodiments (such as FIG. 11 ), the first thin film transistor 1 further includes a first channel layer 14 (a-Si), the second thin film transistor 2 further includes a second channel layer 24 (a-Si), and the distance between the first channel layer 14 and the second channel layer 24 is greater than or equal to 1 µm.
[0049] The series connection type thin film transistor of the utility model can be used in a display module, in particular a display module with cholesteric liquid crystal.
[0050] As shown in FIG. 13, the structure schematic diagram of one embodiment of the display module of the utility model. The display module includes substrate 10 (for example glass), series connection type thin film transistor (including first passivation layer 4 and second passivation layer 5), organic layer OG and light-transmitting electrode layer 6. Organic layer OG is arranged on series connection type thin film transistor, and organic layer OG is provided with contact hole CH. Light-transmitting electrode layer 6 is arranged on organic layer OG. According to this embodiment, since the display module has organic layer OG, light-transmitting electrode layer 6 can be effectively prevented from contacting other conductors (for example metal material).
[0051] Please refer to FIG. 14 , the structure schematic diagram of one embodiment of the display module of the utility model. The display module includes series connection type thin film transistor and black matrix layer BM. Black matrix layer BM is arranged on series connection type thin film transistor. By the arrangement of black matrix layer BM, liquid crystal arranged near the unstable edge of circuit (the edge of pixel P) is shielded, and optional visual effect is obtained.
[0052] [Advantages of the embodiment]
[0053] One of the advantages of the utility model lies in that the series connection type thin film transistor provided by the utility model can be applied to cholesteric liquid crystal, can inhibit thin film transistor leakage, prolong the leakage path and inhibit the problem of leakage by the technical scheme of "the second source electrode of the second thin film transistor is electrically connected with the first drain electrode of the first thin film transistor" and "the first source electrode of the first thin film transistor is electrically connected with the signal line of the pixel, and the first gate electrode of the first thin film transistor and the second gate electrode of the second thin film transistor are respectively electrically connected with the gate line of the pixel".
[0054] One of the advantages of the utility model lies in that the display module provided by the utility model has series connection type thin film transistor, so the foregoing technical effects are obtained.
[0055] The above disclosed content is only the preferred feasible embodiment of the utility model, and does not limit the protection scope of the claims of the utility model, so equivalent technical changes made by applying the content of the utility model specification and drawings are included in the protection scope of the claims of the utility model.
Claims
1. A series-connected thin-film transistor, suitable for a display module with cholesteric liquid crystal, wherein the series-connected thin-film transistor is located within a pixel, characterized in that, The series connection thin film transistor comprises: a first thin film transistor having a first source, a first drain and a first gate; and a second thin film transistor having a second source, a second drain and a second gate, the second source of the second thin film transistor being electrically connected in series with the first drain of the first thin film transistor; wherein the first source of the first thin film transistor is electrically connected to a signal line of the pixel, and the first gate of the first thin film transistor and the second gate of the second thin film transistor are respectively electrically connected to a first gate line of the pixel.
2. The tandem thin film transistor according to claim 1, wherein The series connection thin film transistor further comprises a third thin film transistor having a third source, a third drain and a third gate, the third source of the third thin film transistor being electrically connected in series with the second drain of the second thin film transistor, and the third gate of the third thin film transistor being electrically connected to the first gate line of the pixel.
3. The tandem thin film transistor according to claim 1, wherein In a vertical direction, the projection area of the first thin film transistor is greater than the projection area of the second thin film transistor.
4. A series-connected thin-film transistor, suitable for a display module with cholesteric liquid crystal, wherein the series-connected thin-film transistor is located within a pixel, characterized in that, The series connection thin film transistor comprises: a first thin film transistor having a first source, a first drain and a first gate; and a second thin film transistor having a second source, a second drain and a second gate, the second source of the second thin film transistor being electrically connected in series with the first drain of the first thin film transistor; wherein the first source of the first thin film transistor is electrically connected to a signal line of the pixel, and the first gate of the first thin film transistor is electrically connected to a first gate line of the pixel; and wherein the second gate of the second thin film transistor is electrically connected to a second gate line of the pixel.
5. The tandem thin film transistor according to claim 1 or 4, wherein The first gate and the second gate are in the same layer structure.
6. The series thin film transistor according to claim 5, wherein The first thin film transistor further comprises a first channel layer, and the second thin film transistor further comprises a second channel layer, and the distance between the first channel layer and the second channel layer is greater than or equal to 1 µm.
7. The tandem thin film transistor according to claim 1 or 4, wherein The distance between the first gate of the first thin film transistor and the second gate of the second thin film transistor is greater than or equal to 1 µm.
8. The tandem thin film transistor according to claim 1 or 4, wherein In the first thin film transistor, the distance between the first drain and the first source defines a first distance, and the first distance is greater than or equal to 1 µm.
9. The tandem thin film transistor according to claim 1 or 4, wherein In the first thin film transistor, the distance between the first drain and the first source defines a first distance; in the second thin film transistor, the distance between the second drain and the second source defines a second distance, and the second distance is different from the first distance.
10. The tandem thin film transistor according to claim 1 or 4, wherein In the first thin film transistor, in a first direction, the distance between the first drain and the first source defines a first distance; in a second direction orthogonal to the first direction, the first drain and the first source are equal in length, defining a first length, and the ratio of the first distance to the first length is less than or equal to 50%.
11. A display module, characterized by The display module comprises the series connection thin film transistor according to claim 1 or 4.
12. A display module, characterized by The display module comprises: The tandem thin film transistor according to claim 1 or 4; an organic layer disposed on the tandem thin film transistor; and a light-transmitting electrode layer disposed on the organic layer.
13. A display module characterized by comprising: The display module comprises: the tandem thin film transistor according to claim 1 or 4; and a black matrix layer disposed on the tandem thin film transistor.