Capacitance simulation module and test system based on PXI bus
By using a PXI bus-based capacitance simulation module, the problems of high cost and complex operation in testing capacitive sensor systems are solved, achieving efficient and low-cost capacitance simulation testing.
Patent Information
- Application Number
- CN202520059212.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-10
- Publication Date
- 2025-11-21
- Estimated Expiration
- 2035-01-10
AI Technical Summary
Existing systems for testing capacitive sensors require actual physical sensors, resulting in high testing costs and complex operation.
Design a capacitance simulation module based on PXI bus, including signal acquisition circuit, signal output circuit and processor. It is connected to power supply circuit through PXI bus. The processor outputs simulation signal according to excitation signal to simulate the sensor's induction output signal.
It improves testing efficiency, simplifies the testing process, and reduces testing costs, while also offering the advantages of wide range and high precision.
Smart Images
Figure CN223582350U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a capacitive sensor technical field especially relates to a capacitive simulation module and test system based on PXI bus. BACKGROUND
[0002] PXI (PCI eXtensions for Instrumentation, peripheral component interconnect extensions for instrumentation) bus is a kind of high-performance, modular instrument standard, is widely used in each test system;In addition, the sensor based on the principle of capacitance is widely used in aerospace, automobile manufacturing and other fields, but the system for testing capacitive sensor needs real entity sensor, leading to high test cost, complex operation. UTILITY MODEL CONTENT
[0003] The utility model discloses a capacitive simulation module based on PXI bus to solve the above-mentioned problems.
[0004] The utility model discloses the following technical scheme to realize the above-mentioned purpose:
[0005] Capacitive simulation module based on PXI bus, it includes:
[0006] N signal acquisition circuits and N signal output circuits, each signal acquisition circuit is used to gather the excitation signal of the output of the equipment under test;
[0007] Processor, the input of the processor is connected with a signal acquisition circuit, the output of the processor is connected with a signal output circuit, the processor is also connected with power supply circuit through PXI bus, the processor is used to access the excitation signal, and according to the excitation signal, corresponding simulation signal is output to the corresponding signal output circuit.
[0008] The utility model further proposes a test system, the test system includes the capacitive simulation module based on PXI bus described above.
[0009] The utility model has the advantages of:
[0010] Capacitive simulation module based on PXI bus gathers the excitation signal of the output of the equipment under test through N signal acquisition circuits;Processor according to excitation signal output corresponding simulation signal to corresponding signal output circuit, and multi-channel capacitive simulation output channel is used to simulate the inductive output signal of sensor, to improve test efficiency, simplify test procedure, and reduce test cost, and it has the advantages such as wide range, high precision. BRIEF DESCRIPTION OF DRAWINGS
[0011] Figure 1The utility model discloses a whole block diagram of capacitor simulation module based on PXI bus.
[0012] Figure 2 The utility model discloses a simulation schematic diagram of capacitor simulation module based on PXI bus.
[0013] Figure 3 The utility model discloses a module schematic diagram of capacitor simulation module based on PXI bus.
[0014] Figure 4 The utility model discloses another module schematic diagram of capacitor simulation module based on PXI bus.
[0015] Figure 5 The utility model discloses a fault simulation schematic diagram of capacitor simulation module based on PXI bus.
[0016] Figure 6 The utility model discloses another fault simulation schematic diagram of capacitor simulation module based on PXI bus.
[0017] In the drawing: 11 - first connector, 12 - input signal conditioning network, 13 - analog-digital conversion circuit, 20 - processor, 31 - digital-analog conversion circuit, 32 - output signal conditioning circuit, 33 - second connector, 40 - PXI bus, 50 - power supply circuit. DETAILED DESCRIPTION
[0018] In order to make the purpose, technical scheme and advantage of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be described clearly and completely below in combination with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, rather than all the embodiments. The components of the embodiments of the utility model described and shown in the drawings can be arranged and designed in various different configurations.
[0019] Therefore, the following detailed description of the embodiments of the utility model provided in the drawings is not intended to limit the scope of the claimed utility model, but only represents selected embodiments of the utility model. Based on the embodiments in the utility model, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the utility model.
[0020] It should be noted that: similar signs and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.
[0021] In the description of the utility model, need understanding is, the term "upper", "lower", "internal", "external", "left", "right" and so on indicate the orientation or position relation is based on the orientation or position relation shown in the drawing, or it is the orientation or position relation of the utility model product when using usually put, or it is the orientation or position relation that the person skilled in the art usually understands, just is for the convenience of describing the utility model and simplifying the description, and not indicate or imply the device or element indicated must have a particular orientation, with a particular orientation configuration and operation, therefore can not be understood as the restriction of the utility model.
[0022] In addition, the term "first", "second" and so on are only used to distinguish the description, and can not be understood as indicating or implying relative importance.
[0023] In the description of the utility model, it is still necessary to explain that, unless otherwise explicitly provided and limited, the terms "set", "connect" and so on should be understood broadly, for example, "connect" can be fixedly connected, can also be detachably connected, or integrally connected, can be mechanically connected, can also be electrically connected, can be directly connected, can also be indirectly connected through intermediate medium, can be the communication inside two elements. For the person skilled in the art, the specific meaning of the above-mentioned terms in the utility model can be understood according to the specific circumstances.
[0024] The specific embodiment of the utility model is described in detail below in conjunction with the drawings.
[0025] As Figures 1-6 The capacitor simulation module based on PXI bus includes:
[0026] N signal acquisition circuits and N signal output circuits, each signal acquisition circuit is used to acquire the excitation signal output by the measured device;
[0027] The input end of the processor 20 is connected with a signal acquisition circuit, and the output end of the processor 20 is connected with a signal output circuit, and the processor 20 is further connected with a power supply circuit 50 through a PXI bus 40, and the processor 20 is used to access the excitation signal, and the corresponding simulation signal is output to the corresponding signal output circuit according to the excitation signal.
[0028] In the embodiment, the number of N is 16, that is, a plurality of excitation signals output by the measured device are collected through 16 signal collection circuits, and corresponding simulation signals are output through corresponding signal output circuits, so that multi-channel capacitance simulation is realized, the test efficiency is improved, and the test cost is reduced; the PXI bus 40 is arranged between the processor 20 and the power supply circuit 50, and the power supply circuit 50 provides working power for the processor 20. In the embodiment, the processor 20 can be implemented by using an FPGA (Field-Programmable Gate Array, field programmable gate array). It can be understood that the FPGA generates corresponding capacitance simulation output according to the excitation signal, that is, the waveform data of the output signal corresponding to the simulated capacitance value is calculated according to the excitation signal, and then the simulation signal corresponding to the simulated capacitance value is output according to the waveform data setting. The maximum range of the voltage of the simulation signal is ±10V, so the simulation capacitance range is related to the capacitance configuration of the signal collection circuit and the excitation voltage, and can be configured as follows: 1. When the collection capacitance is 100pF and the excitation signal is an alternating signal with Vp=10V, the capacitance output in the range of 5-100pF can be simulated; 2. When the collection capacitance is 100pF and the excitation signal is an alternating signal with Vp=2V, the capacitance output in the range of 5-500pF can be simulated.
[0029] The capacitance simulation module based on the PXI bus collects the excitation signals output by the measured device through N signal collection circuits; the processor 20 outputs corresponding simulation signals to corresponding signal output circuits according to the excitation signals, and the multi-channel capacitance simulation output channel is used to simulate the sensing output signal of the sensor, so that the test efficiency is improved, the test process is simplified, and the test cost is reduced, and the capacitance simulation module has the advantages of wide range and high precision.
[0030] In an embodiment, the signal collection circuit comprises:
[0031] The first connector 11 is connected with the measured device, and the first connector 11 is used for accessing the excitation signal;
[0032] The input signal conditioning network 12 is connected with the first connector 11, and the input signal conditioning network 12 is used for outputting after operational amplifier conditioning of the excitation signal;
[0033] The analog-to-digital conversion circuit 13 is connected with the input signal conditioning network 12, and the output end of the analog-to-digital conversion circuit 13 is connected with the processor 20, and the analog-to-digital conversion circuit 13 is used for outputting to the processor 20 after analog-to-digital conversion of the excitation signal.
[0034] In an embodiment, the PXI bus-based capacitance simulation module further comprises a single-core shielded wire arranged between the device under test and the first connector 11, and the single-core shielded wire is used to transmit the excitation signal of the device under test to the first connector 11.
[0035] In the embodiment, each signal acquisition circuit can support input of a 7Vrms (-10V~+10V) excitation signal at 0Hz~50KHz and can measure the frequency of the input excitation signal. The signal acquisition circuit in the embodiment comprises a first connector 11, an input signal conditioning network 12 and an analog-to-digital conversion circuit 13, wherein the input signal conditioning network 12 can be implemented by an operational amplifier to perform operational conditioning on the acquired excitation signal.
[0036] In the embodiment, a single-core shielded wire is arranged between the device under test and the first connector 11, that is, the signal input is implemented by using a radio frequency shielded cable to reduce the on-line capacitance and thus improve the anti-interference capability to ensure the simulation accuracy.
[0037] In an embodiment, the signal output circuit comprises a digital-to-analog conversion circuit 31, an output signal conditioning network 32 and a second connector 33, the input end of the digital-to-analog conversion circuit 31 is connected with the processor 20, the output end of the digital-to-analog conversion circuit 31 is connected with the output signal conditioning network 32, and the second connector 33 is connected with the output signal conditioning network 32.
[0038] The digital-to-analog conversion circuit 31 is used to perform digital-to-analog conversion on the simulation signal and then output the simulation signal.
[0039] The output signal conditioning network 32 is used to perform operational conditioning on the simulation signal and then output the simulation signal through the second connector 33.
[0040] In an embodiment, the PXI bus-based capacitance simulation module further comprises a double-core shielded wire arranged between the second connector 33 and the device under test, and the double-core shielded wire is used to transmit the simulation signal to the device under test.
[0041] In the embodiment, the processor 20 can generate a corresponding capacitive simulation signal output according to the input excitation signal, that is, the analog-to-digital conversion circuit 13 converts the simulation signal into an analog-to-digital signal and inputs the analog-to-digital signal to the output signal conditioning network 32 for operational amplifier conditioning, and then outputs the analog-to-digital signal through the second connector 33; wherein the maximum voltage range of the simulation signal is ±10V, so the simulation capacitive range is related to the capacitive configuration of the signal acquisition circuit and the excitation voltage, and can be configured as follows: one, when the acquisition capacitor is 100pF and the excitation signal is an alternating signal with Vp=10V, a capacitive output in the range of 5-100pF can be simulated; two, when the acquisition capacitor is 100pF and the excitation signal is an alternating signal with Vp=2V, a capacitive output in the range of 5-500pF can be simulated.
[0042] Since the simulation signal output by the processor 20 is weak, in the embodiment, a double-core shielded wire is arranged between the device under test and the second connector 33, that is, a radio frequency shielded cable is used for signal output, so as to reduce the capacitive resistance on the wire and improve the anti-interference ability to ensure the simulation accuracy.
[0043] In an embodiment, the PXI bus-based capacitive simulation module further comprises a fault injection unit configured to simulate faults of short circuit of the excitation signal to ground and short circuit of the excitation signal to the signal output circuit.
[0044] In the embodiment, the PXI bus-based capacitive simulation module can simulate the two faults of short circuit of the excitation to ground and short circuit of the excitation to the simulation output through the fault injection unit, so as to perform fault injection testing on the device under test.
[0045] The utility model discloses still propose a kind of test system, and the test system includes the capacitive simulation module based on PXI bus described above;The specific structure of the capacitive simulation module based on PXI bus refers to the above embodiment, since the test system of the present application uses all technical solutions of the above all embodiments, at least has all beneficial effects brought by the technical solutions of the above embodiments, which will not be described here.
[0046] In the capacitive simulation module based on PXI bus, each channel can generate a corresponding capacitive simulation signal under the input excitation signal, and can simulate the two faults of short circuit of the excitation to ground and short circuit of the excitation to the simulation output to perform fault injection testing on the device under test, so as to realize the simulation of real capacitors, simplify the test process and reduce the test cost.
[0047] The above is only the preferred embodiment of the utility model, and it should be pointed out that for ordinary skilled persons in the technical field, without departing from the technical principles of the utility model, a number of improvements and refinements can be made, which should also be considered as the protection scope of the utility model.
Claims
1. A capacitive simulation module based on PXI bus, characterized in that, The PXI bus-based capacitance simulation module comprises: N signal acquisition circuits and N signal output circuits, each of the signal acquisition circuits being configured to acquire an excitation signal output by a device under test; a processor, an input end of the processor being connected with one of the signal acquisition circuits, an output end of the processor being connected with one of the signal output circuits, the processor being further connected with a power supply circuit through a PXI bus, the processor being configured to access the excitation signal and output a corresponding simulation signal to the corresponding signal output circuit according to the excitation signal.
2. The PXI bus-based capacitance emulation module of claim 1, wherein, The signal acquisition circuit comprises: a first connector, the first connector being connected with the device under test, the first connector being configured to access the excitation signal; an input signal conditioning network, the input signal conditioning network being connected with the first connector, the input signal conditioning network being configured to output the excitation signal after operational amplifier conditioning; an analog-to-digital conversion circuit, an input end of the analog-to-digital conversion circuit being connected with the input signal conditioning network, an output end of the analog-to-digital conversion circuit being connected with the processor, the analog-to-digital conversion circuit being configured to output the excitation signal to the processor after analog-to-digital conversion.
3. The PXI bus based capacitance emulation module of claim 2, wherein, The PXI bus-based capacitance simulation module further comprises a single-core shielded wire, the single-core shielded wire being arranged between the device under test and the first connector, the single-core shielded wire being configured to output the excitation signal of the device under test to the first connector.
4. The PXI bus-based capacitance emulation module of claim 1, wherein, The signal output circuit comprises a digital-to-analog conversion circuit, an output signal conditioning network and a second connector, an input end of the digital-to-analog conversion circuit being connected with the processor, an output end of the digital-to-analog conversion circuit being connected with the output signal conditioning network, the second connector being connected with the output signal conditioning network; the digital-to-analog conversion circuit being configured to output the simulation signal after digital-to-analog conversion; the output signal conditioning network being configured to output the simulation signal after operational amplifier conditioning through the second connector.
5. The PXI bus based capacitance emulation module of claim 4, wherein, The PXI bus-based capacitance simulation module further comprises a double-core shielded wire, the double-core shielded wire being arranged between the second connector and the device under test, the double-core shielded wire being configured to output the simulation signal to the device under test.
6. The PXI bus based capacitance emulation module of claim 1, wherein, The PXI bus-based capacitance simulation module further comprises a fault injection unit, the fault injection unit being configured to simulate faults of short circuit of the excitation signal to ground and short circuit of the excitation signal to the signal output circuit.
7. A test system, characterized by The test system comprises the PXI bus-based capacitance simulation module according to any one of claims 1-6.