Packaging structure with built-in discrete device and isolator chip
By setting pads on the frame base island and encapsulating discrete devices in the first plastic package, combined with the redistribution layer (RDL), the problem that discrete devices cannot be built into the traditional packaging structure is solved, realizing highly integrated chip packaging, suitable for multi-chip co-packaging scenarios, and simplifying the package size and complex wire bonding issues.
Patent Information
- Application Number
- CN202422987219.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-02
- Publication Date
- 2025-11-21
- Estimated Expiration
- 2034-12-02
AI Technical Summary
Traditional frame-type packaging structures cannot achieve complex circuit connections, making it difficult to integrate discrete components. This results in large package size, high complexity and redundancy, and difficulties in wire bonding, especially in multi-core co-packaging scenarios.
The packaging structure with built-in discrete components is adopted. By setting pads on the frame base island and encapsulating discrete components in the first plastic package, and combining the redistribution layer (RDL) to realize complex wire bonding and multi-core encapsulation, the pads are formed by flip-chip or hole plating, simplifying the manufacturing process.
It achieves built-in packaging of discrete components, improves chip integration, simplifies the number of external pins, controls package size, is suitable for multi-core encapsulation scenarios, solves complex wire bonding crossover problems, and significantly improves multi-core encapsulation capabilities.
Smart Images
Figure CN223582983U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the field of packaging technology, specifically to built-in discrete device's packaging structure, isolation chip. BACKGROUND
[0002] Traditional frame type packaging, since it has only one layer of metal frame, thus the internal complex circuit connection function cannot be borne, and it is difficult to realize the internal multi-core plastic package scheme. In addition, the traditional sealing multi-chip packaging structure needs external capacitor and pull-down resistor when power supply, which requires increasing the external pin on the packaging structure, such as Figure 1 As shown, only the necessary discrete device can be set outside the frame. But doing so not only needs to increase the size of single package, but also increases the complexity of the application end. In addition, the existing packaging process is difficult to deal with complex wire bonding, almost no cross-wire bonding is allowed, especially when using sealing projects, many wire bonding problems and risks will lead to the project cannot be implemented. UTILITY MODEL CONTENT
[0003] The utility model solves the technical problem that: provide built-in discrete device's packaging structure, isolation chip, can realize discrete device built-in packaging, improve the chip integration.
[0004] In order to solve the above technical problem, the first technical scheme adopted by the utility model is:
[0005] The packaging structure of built-in discrete device includes: frame base island, chip, discrete device, solder pad and first plastic package body.
[0006] The frame base island and the chip are plastic packaged in the first plastic package body; the chip is arranged on the base island frame; the first plastic package body is provided with the solder pad connected with the chip at the position corresponding to the chip; the discrete device is arranged on the solder pad.
[0007] Optionally, the solder pad is led out by punching and plating at the position corresponding to the chip on the first plastic package body.
[0008] Optionally, it further includes a redistribution layer RDL; the redistribution layer RDL is arranged on the position corresponding to the solder pad on the first plastic package body and connected with the solder pad.
[0009] Optionally, the chip is a flip chip; the solder pad is a solder pad obtained by grinding the solder point on the flip chip.
[0010] Optionally, it further includes a redistribution layer RDL; the redistribution layer RDL is arranged on the position corresponding to the solder pad on the first plastic package body and connected with the solder pad.
[0011] Optionally, the frame base islands include a first frame base island and a second frame base island separated by an isolation; the chips include a first chip and a second chip; the discrete devices include a first discrete device and a second discrete device; the pads include a first pad and a second pad;
[0012] The first chip is arranged on the first frame base island, and the second chip is arranged on the second frame base island; the first pad is arranged on the first plastic package at a position corresponding to the first chip, and the second pad is arranged on the first plastic package at a position corresponding to the second chip; the first discrete device is connected to the first chip through the first pad, and the second discrete device is connected to the second chip through the second pad.
[0013] Optionally, the first redistribution layer (RDL) and the second redistribution layer (RDL) are further included; the first redistribution layer (RDL) is arranged on the first plastic package at a position corresponding to the first pad and is connected to the first pad; and the second redistribution layer (RDL) is arranged on the first plastic package at a position corresponding to the second pad and is connected to the second pad.
[0014] Optionally, the discrete devices include resistors and capacitors.
[0015] Optionally, the second plastic package is further included; the first plastic package, the pads, and the discrete devices are all encapsulated in the second plastic package.
[0016] Another technical solution provided by the utility model discloses a packaging structure of an isolator chip.
[0017] The utility model discloses a packaging structure of an isolator chip.
[0018] The utility model discloses the beneficial effect lies in: the utility model discloses a first plastic package corresponding chip's position is equipped with the pad that communicates chip, and this pad can form through the punching electroplating mode, also can utilize flip chip to form the solder point of self -bearing, then the discrete device is arranged on the pad, and all components are encapsulated in the second plastic package. BRIEF DESCRIPTION OF DRAWINGS
[0019] Figure 1 It is the structural schematic diagram of traditional chip.
[0020] Figure 2 A schematic diagram of a package structure for a built-in discrete device provided in Embodiment 1 of this utility model;
[0021] Figure 3 A schematic diagram of the second packaging structure for the built-in discrete device provided in Embodiment 1 of this utility model;
[0022] Figure 4 A schematic diagram of the packaging structure of the built-in discrete device provided in Embodiment 2 of this utility model;
[0023] Figure 5 A schematic diagram of the second packaging structure for the built-in discrete device provided in Embodiment 2 of this utility model;
[0024] Figure 6 A schematic diagram of a multi-core encapsulation structure with built-in discrete components provided in Embodiment 3 of this utility model;
[0025] Figure 7 A schematic diagram of the second multi-core encapsulation structure with built-in discrete components provided in Embodiment 3 of this utility model;
[0026] Figure 8 A schematic diagram of the multi-core encapsulation structure with built-in discrete components provided in Embodiment 3 of this utility model;
[0027] Figure 9 A schematic diagram of the multi-core encapsulation structure four with built-in discrete components provided in Embodiment 3 of this utility model;
[0028] Figure 10 for Figure 6 A schematic diagram of the process flow for a multi-core encapsulation structure;
[0029] Figure 11 for Figure 7 A schematic diagram of the process flow for the second multi-core encapsulation structure;
[0030] Figure 12 for Figure 8 A schematic diagram of the process flow for the multi-core encapsulation structure 3;
[0031] Figure 13 for Figure 9 A schematic diagram of the process flow for the multi-core encapsulation structure four.
[0032] Label Explanation:
[0033] 1. Frame base island; 2. Chip; 3. Discrete device; 4. Pad; 5. First molding compound; 6. Second molding compound; 7. Solder joint; 8. Redistribution layer (RDL);
[0034] 11. First frame base island; 12. Second frame base island;
[0035] 21. First chip; 22. Second chip;
[0036] 31. First discrete device; 32. Second discrete device;
[0037] 41. First pad; 42. Second pad;
[0038] 81. First redistribution layer RDL; 82. Second redistribution layer RDL. Detailed Implementation
[0039] To explain in detail the technical content, objectives, and effects of this utility model, the following description is provided in conjunction with the embodiments and accompanying drawings.
[0040] Example 1
[0041] Please refer to Figure 2 This embodiment provides a packaging structure with built-in discrete components.
[0042] The packaging structure for the built-in discrete components provided in this embodiment is as follows: Figure 2 As shown, it includes: a frame base island 1, a chip 2, discrete devices 3, pads 4, and a first molding compound 5;
[0043] The frame island 1 and the chip 2 are encapsulated within the first encapsulation body 5; the chip 2 is disposed on the frame island 1; the first encapsulation body 1 has a pad 4 connected to the chip at a position corresponding to the chip 2; the discrete device 3 is disposed on the pad 4.
[0044] In this embodiment, the pads can be obtained in at least two of the following ways:
[0045] In some specific implementations, such as Figure 2 As shown, the pad 4 can be brought out by a drilling electroplating method. Specifically, the pad 4, which is perpendicularly connected to the chip 2, is brought out by a drilling circuit above the first molding compound 5 at a position corresponding to the chip 2.
[0046] In some specific implementations, such as Figure 3 As shown, the pad 4 can also be obtained by grinding down the top-facing solder joint 7 on the flip chip. That is, the chip 2 is a flip chip, and the solder joint 7 on the flip chip is directly ground down to serve as the pad 4. This method eliminates the need for laser-drilled holes and electroplating steps; the pad can be obtained simply by grinding down the surface, greatly simplifying the manufacturing process.
[0047] In the embodiment, the discrete device can be a resistor, a capacitor, a diode, a triode, a thyristor, a MOS tube, or an electronic device for realizing rectification, voltage stabilization, switching, and the like.
[0048] In some specific embodiments, the discrete device is fixedly arranged on the pad in a surface mounting manner.
[0049] In yet some specific embodiments, as shown in Figure 2 the discrete device 3 includes a resistor R and a capacitor C; the mounting position of the capacitor C on the pad 4 is connected to the chip 2 and the frame base island 1 respectively. That is, the capacitor is connected to the frame base island (ground connection) and the chip respectively through the pad.
[0050] In the embodiment, as shown in Figure 2 preferably, the solder joints of the pad 4 are all vertical solder joints, that is, the solder joints on the pad are vertically connected to the chip and the frame base island. In this embodiment, the packaging structure has the characteristics of vertical stacking and vertical connection, which can not only compress the structure size, but also shorten the signal transmission path, so that the transmission matching performance is more guaranteed.
[0051] In the embodiment, as shown in Figure 2 and Figure 3 the packaging structure further includes a second plastic package 6; the first plastic package 5, the pad 4, and the discrete device 3 are all plastic packaged in the second plastic package 6. That is, after the discrete device is fixedly arranged on the pad position of the first plastic package, the whole is encapsulated again to obtain the second plastic package. In this embodiment, the second plastic package plays a role of fixing the discrete device and the first plastic package.
[0052] The packaging structure with the built-in discrete device provided by the embodiment can realize the built-in packaging of the discrete device and improve the packaging integration; at the same time, the chip volume can be reduced, and the design complexity of the application end can be reduced; in addition, the length of the connection line can be shortened, and the corresponding parasitic parameters can also be obviously improved.
[0053] Embodiment two
[0054] As shown in Figure 4 , the embodiment is further extended based on the embodiment one, and the packaging and re-wiring can be further realized.
[0055] The packaging structure with the built-in discrete device provided by the embodiment, as shown in Figure 4 further includes a redistribution layer RDL 8; the redistribution layer RDL 8 is arranged on the first plastic package 5 at a position corresponding to the pad 4 and is connected to the pad 4.
[0056] The redistribution layer RDL refers to a metal layer capable of realizing the redistribution of electrical connection.
[0057] In the embodiment, the redistribution layer RDL 8 is additionally arranged at the position of the pad 4 on the first plastic package 5 to realize the package surface redistribution function, which can reduce the risk of wire crossing and solve the problem that complex wire bonding cannot be put into production due to the problem of short circuit caused by crossing. Meanwhile, the chip size can be reduced by optimizing the wire bonding in the complex wire bonding scene, and the parasitic parameters can also be improved. In addition, the redistribution layer RDL can also be used to integrate multiple chips into a single package to improve the package function.
[0058] In particular, the redistribution layer RDL provided in the embodiment is also applicable to the application scenario of the chip being a flip chip. As shown in Figure 5 For the flip chip package structure of the chip 2, the redistribution layer RDL 8 is arranged on the first plastic package 6 at a position corresponding to the flip chip and is connected to the pad 4 obtained by the flip chip.
[0059] In the embodiment, corresponding to the two implementation forms of the pad, the redistribution layer RDL also has two implementation modes:
[0060] In some specific embodiments, that is, in the case of using a non-flip chip, the signal port, that is, the pad, to be connected can be first introduced on the first plastic package in a punching and plating manner. Then, the wire bonding signal is formed by copper plating, that is, the redistribution layer RDL.
[0061] In some other specific embodiments, that is, in the case of using a flip chip, the soldering point of the flip chip facing upward can be first ground flat to serve as a pad. Then, the plating wire bonding signal is formed by copper plating, that is, the redistribution layer RDL. It can be understood that compared with the previous specific embodiment, the laser hole and the plating step of the laser hole are omitted, and the redistribution layer RDL can be directly manufactured on the pad formed by the flip chip, which can greatly simplify the manufacturing process.
[0062] The embodiment is particularly applicable to the packaging of MPW chips. Through redistribution within the package, multi-chip package can be more easily realized without delaying sample development.
[0063] Embodiment Three
[0064] Please refer to Figure 6 The embodiment is based on Embodiment One and Embodiment Two and provides a multi-chip package structure with built-in discrete devices.
[0065] First, the embodiment provides a multi-chip package structure with built-in discrete devices based on Embodiment One, as shown in Figure 6As shown, the frame base island 1 specifically comprises a first frame base island 11 and a second frame base island 12 which are isolated (and can also be understood as independent of each other, without a connection relationship); the chip 2 specifically comprises a first chip 21 and a second chip 22; the discrete device 3 specifically comprises a first discrete device 31 and a second discrete device 32; the pad 4 comprises a first pad 41 and a second pad 42;
[0066] The first chip 21 is arranged on the first frame base island 11, and the second chip 22 is arranged on the second frame base island 12; the first pad 41 is arranged on the first plastic package 5 at a position corresponding to the first chip 21, and the second pad 42 is arranged on the first plastic package 5 at a position corresponding to the second chip 22; the first discrete device 31 is connected to the first chip 21 through the first pad 41, and the second discrete device 32 is connected to the second chip 22 through the second pad 42.
[0067] In some specific embodiments of the present embodiment, as shown in Figure 7 The first chip 21 and the second chip 22 can adopt flip chips, and the first pad 41 and the second pad 42 are directly obtained by grinding the solder points 7 on the corresponding first chip 21 and the second chip 22. It can be understood that the first chip and the second chip are a multi-core package structure of flip chips, which has the advantage of simplifying the manufacturing process compared to other specific embodiments of the present embodiment.
[0068] Secondly, in still some specific embodiments of the present embodiment, based on the above-mentioned embodiment two, the redistribution layer RDL can also be added to further realize the packaging surface rewiring function of the multi-core package structure, so as to better adapt to the complex wire bonding scene and improve the package function.
[0069] Specifically, as shown in Figure 8 The redistribution layer RDL 8 comprises a first redistribution layer RDL 81 and a second redistribution layer RDL 82; the first redistribution layer RDL 81 is arranged on the first plastic package 5 at a position corresponding to the first pad 41 and is connected to the first pad 41; the second redistribution layer RDL 82 is arranged on the first plastic package 5 at a position corresponding to the second pad 42 and is connected to the second pad 42.
[0070] In some preferred embodiments of the above-mentioned specific embodiments, the flip chip scheme can also be used. That is, the redistribution layer RDL is added on the basis of the flip chip, so as to simplify the manufacturing process and have the packaging surface rewiring function.
[0071] Specifically, as shown in Figure 9As shown, the first chip 21 and the second chip 22 are both flip chips; the first redistribution layer RDL 81 and the second redistribution layer RDL 82 are respectively arranged above the first chip 21 and the second chip 22, and are respectively connected with the pads of the corresponding flip chips, i.e. the first pad 41 and the second pad 42.
[0072] The multi-core packaging structure provided by the embodiment simultaneously contains two chip base island structures which are independent of each other and have consistent structures and functions. By utilizing the isolation property between them, wireless isolation communication transmission can be realized, such as high and low voltage wireless isolation devices in power systems and other scenarios which have the demand of wireless isolation transmission.
[0073] Embodiment Four
[0074] The embodiment further extends the above-mentioned embodiment three, and provides corresponding process manufacturing procedures for the above-mentioned four kinds of multi-core packaging structures.
[0075] (1) Figure 6 The process procedure of the first multi-core packaging structure (discrete device built-in) is as shown in Figure 10
[0076] S1: manufacturing a frame base island;
[0077] S2: mounting a chip on the frame base island;
[0078] S3: wire connecting a pin;
[0079] S4: first plastic packaging, obtaining a first plastic packaging body;
[0080] S5: laser hole + electroplating + surface treatment, setting a pad on the first plastic packaging body;
[0081] S6: mounting a discrete device on the surface of the pad;
[0082] S7: second plastic packaging, obtaining a second plastic packaging body;
[0083] S8: cutting a rib to form a finished chip.
[0084] The process procedure of the first multi-core packaging structure (discrete device built-in) described above, on the basis of the first plastic packaging body, leads out the signals which need to be connected and externally hung discrete devices through laser holes, electroplating fills and performs surface treatment on the laser holes to form a surface-mounted pad; after configuring the discrete device through reflow soldering, the second packaging is performed to obtain a finished chip. The built-in discrete device packaging can be realized, the packaging integration is improved; meanwhile, the chip volume can be reduced, and the parasitic parameters are optimized.
[0085] (II) Figure 7 The second multi-core sealing structure (flip chip + built-in discrete device) is shown in the process flow as Figure 11
[0086] S1: frame base island manufacturing;
[0087] S2: flip chip is attached to the frame base island with the face up (i.e. the soldering point is facing up);
[0088] S3: first plastic sealing, to obtain a first plastic sealing body;
[0089] S4: polishing the soldering point of the flip chip + surface treatment, to form a soldering pad on the first plastic sealing body;
[0090] S5: attaching a discrete device on the soldering pad;
[0091] S6: wire connection pin;
[0092] S7: second plastic sealing, to obtain a second plastic sealing body;
[0093] S8: cutting rib forming, to obtain a finished chip.
[0094] The process flow of the second multi-core sealing structure (flip chip + built-in discrete device) described above, since the flip chip is used, the flip chip has a face-up soldering point, so on the basis of the first plastic sealing body, without electroplating, the soldering point is directly polished and treated to obtain a soldering pad; then after attaching a discrete device on the soldering pad, the second sealing is performed to obtain a finished chip. Not only can the built-in discrete device be sealed to improve the packaging integration, but also the chip size can be reduced and the parasitic parameters can be optimized; more importantly, the manufacturing process can be greatly simplified.
[0095] (Three) Figure 8 The second multi-core sealing structure (discrete device built-in + packaging redistribution) is shown in the process flow as Figure 12
[0096] S1: frame base island manufacturing;
[0097] S2: attaching a chip to the frame base island;
[0098] S3: wire connection pin;
[0099] S4: first plastic sealing, to obtain a first plastic sealing body;
[0100] S5: laser hole + electroplating + surface treatment, to form a soldering pad on the first plastic sealing body;
[0101] S6: electroplating redistribution on the soldering pad, to obtain a redistribution layer RDL;
[0102] S7: attaching a discrete device on the redistribution layer RDL;
[0103] S8: Second plastic sealing, to obtain a second plastic sealing body;
[0104] S9: Cutting rib forming, to obtain a finished chip.
[0105] The process flow of the third multi-core sealing structure (built-in discrete device + packaging redistribution) is as follows: based on the first plastic sealing body, the signals required to be connected and externally hung discrete devices are led out through the laser hole, the laser hole is electroplated and filled and surface treated to form a surface mount pad; the electroplated circuit is deposited on the pad position, and the redistribution layer is formed by pattern transfer to realize the connection of the signals on the first plastic sealing body; finally, the discrete devices are configured and the second packaging is performed to obtain a finished chip. Not only can the built-in discrete device packaging be realized to improve the packaging integration, but also the chip volume can be reduced and the parasitic parameters can be optimized; moreover, the internal redistribution at the packaging level can be realized, the problem of complex wire bonding being unable to be landed due to cross short circuit can be solved, and the sealing function can be improved.
[0106] (Four) Figure 9 The fourth multi-core sealing structure (flip chip + built-in discrete device + packaging redistribution) is shown in the process flow as shown in Figure 13
[0107] S1: Frame base island manufacturing;
[0108] S2: The flip chip with the face upward (i.e., the soldering point is upward) is attached to the frame base island;
[0109] S3: First plastic sealing, to obtain a first plastic sealing body;
[0110] S4: Polishing the soldering point of the flip chip + surface treatment, to form a pad on the first plastic sealing body;
[0111] S5: Electroplating redistribution on the pad, to obtain a redistribution layer RDL;
[0112] S6: Attaching a discrete device to the pad;
[0113] S7: Wire bonding connection pin;
[0114] S8: Second plastic sealing, to obtain a second plastic sealing body;
[0115] S9: Cutting rib forming, to obtain a finished chip.
[0116] The process flow of the fourth multi-core sealing structure (flip chip + built-in discrete device + package redistribution) is as follows: since the flip chip is used, the solder joint is directly ground and processed on the basis of the first plastic package body to obtain the pad; then the redistribution layer RDL is formed by electroplating the wire on the pad; finally, the discrete device is attached to obtain the finished chip by the second packaging. Not only can the built-in discrete device packaging be realized to improve the packaging integration, but also the chip volume can be reduced and the parasitic parameters can be optimized; moreover, the internal redistribution at the package level can be realized to solve the problem that the complex wire bonding cannot be landed in production due to cross short circuit, improve the sealing function, and more importantly, greatly simplify the manufacturing process.
[0117] Embodiment five
[0118] The embodiment is based on any one of the above-mentioned embodiments one to four, and provides an isolator chip, which comprises the packaging structure of the built-in discrete device in any one of the above-mentioned embodiments one to four; and further comprises a second plastic package body; the first plastic package body, the pad and the discrete device are all plastic-sealed in the second plastic package body.
[0119] The embodiment simultaneously comprises two chip base islands which are independent of each other and have consistent structures and functions, and wireless isolation communication transmission can be realized by using the isolation property between the two chip base islands, such as the high-low voltage wireless isolator in a power system and other scenes requiring wireless isolation transmission.
[0120] In summary, the packaging structure of the built-in discrete device and the isolation chip can realize the built-in discrete device and improve the chip integration. Not only the number of external pins is simplified and the chip packaging size is controlled, but also the frame processing difficulty is not increased. In addition, the packaging structure is particularly suitable for multi-chip sealing scenes, solves the complex wire crossing, and significantly improves the multi-chip sealing capability.
[0121] The above-mentioned embodiments are only examples of the utility model, and do not limit the patent range of the utility model, and any equivalent transformation or direct or indirect application in the related technical field based on the content of the utility model specification and drawings is also included in the patent protection range of the utility model.
Claims
1. A package structure with built-in discrete devices, characterized by, The package structure comprises a frame base island, a chip, a discrete device, a pad and a first plastic package body. The frame base island and the chip are plastic packaged in the first plastic package body; the chip is arranged on the frame base island; the first plastic package body is provided with the pad connected with the chip at a position corresponding to the chip; and the discrete device is arranged on the pad. The pad is led out by punching and plating at a position corresponding to the chip on the first plastic package body.
2. The packaging structure for the built-in discrete device as described in claim 1, characterized in that, The package structure further comprises a redistribution layer (RDL); the redistribution layer (RDL) is arranged at a position corresponding to the pad on the first plastic package body and is connected with the pad.
3. The packaging structure with built-in discrete components as described in claim 1, characterized in that, The chip is a flip chip; and the pad is a pad obtained by grinding a soldering point provided on the flip chip.
4. The packaging structure for built-in discrete devices as described in claim 1, characterized in that, The package structure further comprises a redistribution layer (RDL); the redistribution layer (RDL) is arranged at a position corresponding to the pad on the first plastic package body and is connected with the pad.
5. The packaging structure for the built-in discrete device as described in claim 4, characterized in that, The frame base island comprises a first frame base island and a second frame base island which are isolated; the chip comprises a first chip and a second chip; the discrete device comprises a first discrete device and a second discrete device; and the pad comprises a first pad and a second pad.
6. The packaging structure for built-in discrete devices as described in claim 1, characterized in that, The first chip is arranged on the first frame base island, and the second chip is arranged on the second frame base island; the first plastic package body is provided with the first pad at a position corresponding to the first chip, and is provided with the second pad at a position corresponding to the second chip; the first discrete device is connected with the first chip through the first pad, and the second discrete device is connected with the second chip through the second pad. The package structure further comprises a first redistribution layer (RDL) and a second redistribution layer (RDL); the first redistribution layer (RDL) is arranged at a position corresponding to the first pad on the first plastic package body and is connected with the first pad; and the second redistribution layer (RDL) is arranged at a position corresponding to the second pad on the first plastic package body and is connected with the second pad.
7. The packaging structure for built-in discrete devices as described in claim 6, characterized in that, The discrete device comprises a resistor and a capacitor.
8. The packaging structure with built-in discrete components as described in claim 1, characterized in that, The package structure further comprises a second plastic package body; the first plastic package body, the pad and the discrete device are plastic packaged in the second plastic package body.
9. The package structure of claim 1 to 8, wherein, The package structure comprises the package structure with the built-in discrete device according to any one of claims 6-8; and further comprises a second plastic package body; the first plastic package body, the pad and the discrete device are plastic packaged in the second plastic package body.
10. An isolator chip, characterized by