Semiconductor structure
By introducing an oxide dielectric layer into the UTSV etching process, the problems of substrate damage and process cost caused by HM layer thickness are solved, achieving the stability and efficient production of semiconductor structures.
Patent Information
- Application Number
- CN202423106902.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2025-11-21
- Estimated Expiration
- 2034-12-16
AI Technical Summary
During UTSV etching, a thinner HM layer can cause damage to the top of the substrate, increasing the risk of copper ion diffusion, while a thicker HM layer increases wafer warpage and process cost, affecting the stability and efficiency of the process.
By introducing an oxide dielectric layer in the UTSV etching process, the thickness of the oxide dielectric layer on the substrate sidewall is increased. The oxide dielectric layer is formed by thermal oxidation to protect the substrate. The etching stops at the oxide dielectric layer to avoid substrate damage.
It effectively protects the integrity of the substrate structure, reduces substrate damage, lowers process costs and risks, and improves the stability and efficiency of the process.
Smart Images
Figure CN223582986U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to the field of semiconductor chip and manufacturing, specifically, relate to a kind of semiconductor structure. BACKGROUND
[0002] In 3D packaging technology, the etching process of UTSV (Ultra-Thin Through Silicon Via) is one of the key technologies to realize high-density and high-speed interconnection between chips. Among them, HM (hard mask layer) plays a crucial role in the formation process of UTSV. It not only serves as a seed layer for copper electroplating, but also acts as a barrier to prevent copper ions from diffusing into the silicon substrate.
[0003] Thinner HM thickness has significant advantages in process flow and process cost, as it can reduce material consumption, shorten processing time, and reduce wear and maintenance costs of related equipment. However, thinner HM thickness poses a huge technical challenge to etching sites. During the etching process of UTSV, due to the high precision and uniformity requirements of etching, the etching interface often inevitably extends to the substrate interface, and even further etches the protective layer of the sidewall, causing damage to the top of the substrate. This damage not only destroys the integrity of the UTSV structure, but also causes the substrate area of the sidewall to lose the protection of the sidewall cover layer, thereby increasing the risk of copper ion diffusion, ultimately leading to increased current leakage problems.
[0004] To solve the problem of substrate top damage caused by etching, one common approach currently is to increase the thickness of the HM layer. However, this approach also brings new problems. On the one hand, thicker HM layers can increase the degree of wafer warping, which not only increases the risk during the process, but also can affect the accuracy and stability of subsequent process steps. On the other hand, thicker HM layers can reduce the working efficiency (WPH, i.e. the number of processed wafers per hour) of sites such as chemical vapor deposition (CVD), etching (ETCH), and chemical mechanical polishing (CMP), thereby significantly increasing process costs.
[0005] Therefore, how to optimize the thickness of the HM layer while ensuring the quality and performance of UTSV etching, reduce substrate top damage, and reduce process costs and risks has become a key problem that needs to be solved in current 3D advanced packaging technology. UTILITY MODEL CONTENTS
[0006] In view of the problems existing in the prior art described above, the utility model provides a semiconductor structure, specifically comprising:
[0007] The first substrate includes a first metal interconnection layer and a first device layer above the first metal interconnection layer;
[0008] a second substrate above the first substrate;
[0009] a through hole penetrating through the second substrate, the first device layer and exposing the first metal interconnection layer;
[0010] an oxidation medium layer on the sidewall of the through hole and the surface of the substrate on both sides of the through hole.
[0011] Optionally, the second substrate comprises a substrate, and a second device layer and a second metal interconnection layer formed in the substrate.
[0012] Optionally, further comprising a hard mask layer above the second substrate.
[0013] Optionally, further comprising a sidewall covering layer covering the sidewall of the through hole.
[0014] Optionally, the first metal interconnection layer and the second metal interconnection layer comprise a medium layer and a conductive circuit.
[0015] Optionally, the thickness of the oxidation medium layer between the first substrate and the sidewall covering layer is greater than the thickness of the oxidation medium layer between the first substrate and the hard mask layer.
[0016] Optionally, the thickness of the oxidation medium layer between the first substrate and the sidewall covering layer is between 200nm and 250nm, and the thickness of the oxidation medium layer between the first substrate and the hard mask layer is between 100nm and 125nm.
[0017] Optionally, the through hole is formed with a flared mouth structure away from one side of the first substrate, the narrow end of the flared mouth structure is connected with the sidewall covering layer, and the wide end of the flared mouth is located at the hard mask layer.
[0018] Optionally, the side edge of the flared mouth structure is formed in the oxidation medium layer, the sidewall covering layer and the hard mask layer.
[0019] As described above, the semiconductor structure provided by the utility model has at least the following beneficial technical effects:
[0020] In the semiconductor structure of the utility model, the substrate sidewall surface is changed into an oxidation medium layer through a thermal oxidation process, the thickness of the substrate sidewall oxidation medium layer is increased, the damage to the top of the substrate caused by subsequent etching is avoided, the substrate is effectively protected, the integrity of the structure is protected, and the stability of the entire semiconductor structure is maintained. BRIEF DESCRIPTION OF DRAWINGS
[0021] Figure 1 The structure schematic diagram of the semiconductor structure provided by the utility model is shown.
[0022] Figures 2a-2f The step of forming a semiconductor structure is shown schematically.
[0023] Reference numerals
[0024] 100, first substrate; 101, first metal interconnection layer; 102, conductive circuit; 103, first device layer; 200, second substrate; 201, second metal interconnection layer; 202, second device layer; 300, oxidation medium layer; 400, hard mask layer; 500, sidewall covering layer; 600, via hole; 601, trumpet structure. DETAILED DESCRIPTION
[0025] The embodiments of the present application will be described in detail with specific examples. Other advantages and effects of the present application can be easily understood by those skilled in the art from the content disclosed in the specification. The present application can also be implemented or applied in other different embodiments, and the details in the specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.
[0026] It should be noted that the diagrams provided in the embodiments only schematically illustrate the basic concept of the present application, and although the diagrams only show the components related to the present application, they are not drawn according to the number, shape and size of the components in actual implementation. The shape, number, position relationship and proportion of each component in actual implementation can be changed at will under the premise of realizing the technical solutions of the present application, and the component layout form can also be more complex.
[0027] The embodiments provide a semiconductor structure, as shown in the drawings. Figure 1 The semiconductor structure provided by the embodiments includes a first substrate 100, which includes a first metal interconnection layer 101 and a first device layer 103 located above the first metal interconnection layer 101. A second substrate 200 is located above the first substrate 100, and part of the surface of the second substrate 200 is subjected to oxidation treatment. A via hole 600 penetrates the second substrate 200, the first device layer 103 from top to bottom and exposes the first metal interconnection layer 101. An oxidation medium layer 300 is formed by heat oxidation of the second substrate 200, and the oxidation medium layer 300 is located on the sidewall of the via hole 600 and the surface of the second substrate 200 on both sides of the via hole 600.
[0028] Specifically, the semiconductor structure provided by the embodiments further includes a hard mask layer 400 located on the navigation side of the second substrate 200, and a sidewall covering layer 500 covering the sidewall of the via hole and having part of the sidewall covering layer 500 above the hard mask layer 400. Figure 1 As can be seen, the semiconductor structure provided by the embodiments further includes a hard mask layer 400 located on the navigation side of the second substrate 200, and a sidewall covering layer 500 covering the sidewall of the via hole and having part of the sidewall covering layer 500 above the hard mask layer 400. Figure 1It can be seen that the through hole 600 has a trumpet mouth structure 601 away from the first substrate, the narrow end of the trumpet mouth structure 601 is connected with the side wall covering layer 500, and the wide end of the trumpet mouth structure 601 is located in the hard mask layer 400. The trumpet mouth structure 601 is formed due to etching. Due to the presence of the oxidation medium layer 300, in the UTSV etching process, the hard mask layer 400 is etched first, and then the etching is further performed and stopped at the oxidation medium layer 300. Specifically, the side of the trumpet mouth structure 601 is formed in the oxidation medium layer 300, the side wall covering layer 500 and the hard mask layer 400, and only contacts the side wall covering layer 500, the oxidation medium layer 300 and the hard mask layer 400, and does not contact the second substrate 200. The presence of the oxidation medium layer 300 not only protects the integrity of the UTSV structure, but also enables the second substrate 200 to be protected by the side wall covering layer 500, and does not cause damage to the top of the second substrate 200.
[0029] Generally, the second substrate 200 can be a substrate layer without a device layer and / or an interconnection layer, or can contain a substrate layer with a device layer and / or an interconnection layer. Specifically, it can be designed according to actual needs. Specifically, the semiconductor structure provided in the embodiment, the second substrate 200 is similar to the first substrate 100, and the second substrate 200 includes a substrate, and a second device layer 202 and a second metal interconnection layer 201 formed in the substrate. Generally, the first metal interconnection layer 101 and the second metal interconnection layer include a dielectric layer and a conductive circuit. Specifically, in the embodiment, the first metal interconnection layer 101 includes a conductive circuit 102, and the conductive circuit 102 is exposed in the through hole 600.
[0030] Generally, the thickness of the oxidation medium layer 300 between the second substrate 200 and the side wall covering layer 500 is greater than the thickness of the oxidation medium layer 300 between the second substrate 200 and the hard mask layer 400. Specifically, the thickness of the oxidation medium layer 300 between the second substrate 200 and the side wall covering layer 500 is between 150nm and 250nm, and the thickness of the oxidation medium layer 300 between the second substrate 200 and the hard mask layer 400 is between 50nm and 150nm. Further, the thickness of the oxidation medium layer 300 between the second substrate 200 and the side wall covering layer 500 is between 200nm and 250nm, and the thickness of the oxidation medium layer 300 between the second substrate 200 and the hard mask layer 400 is between 100nm and 125nm.
[0031] Specifically, as Figures 2a-2fAs shown, the formation steps of the semiconductor structure provided by the embodiment are shown, and specifically include: forming a first substrate 100, the first substrate 100 including a first metal interconnection layer 101 and a first device layer 103 above the first metal interconnection layer; forming a second substrate 200 above the first device layer 103, and generally, the second substrate 200 further includes a second metal interconnection layer and a second metal layer (not shown in the figure); forming a hard mask layer 400 on the second substrate 200; obtaining a through-hole 600 from top to bottom through a through-hole etching process, the through-hole 600 penetrating the hard mask layer 400, the second substrate 200 and the first device layer 103; forming an oxidation medium layer 300, introducing oxygen into the junction between the second substrate 200 and the hard mask layer 400 and the through-hole 600, and then heating and oxidizing to form the oxidation medium layer 300, the oxidation medium layer 300 including between the second substrate 200 and the hard mask 400 and on the sidewall of the second substrate 200 in the through-hole; forming a sidewall covering layer 500, the sidewall covering layer 500 covering the surface of the hard mask layer 400 and the inner wall of the through-hole covering the oxidation medium layer 300 and the first metal interconnection layer 101; exposing the first metal interconnection layer 101, removing the sidewall covering layer 500 covering the surface of the hard mask layer 400 by etching process, and exposing the conductive circuit 102 in the first metal interconnection layer 101 at the bottom of the through-hole 600.
[0032] Generally, the material of the first substrate 100 includes silicon, germanium, silicon-germanium alloy, gallium arsenide or other semiconductor materials. Generally, the first metal interconnection layer 101 is used for electrical connection. The material of the first metal interconnection layer 101 includes copper, aluminum, tungsten, nickel, cobalt, gold, silver, alloy and other metal materials with good electrical conductivity and good mechanical properties. Specifically, it can be selected according to the actual application requirements, cost and compatibility with other materials. In the embodiment, the material of the first substrate 100 is silicon, and the material of the first metal interconnection layer 101 is copper.
[0033] Generally, the material of the second substrate 200 includes silicon, germanium, silicon-germanium alloy, gallium arsenide or other semiconductor materials. Specifically, Si is selected as the substrate in the embodiment. Therefore, the material of the oxidation medium layer 300 is SiO2. Generally, the heating temperature is between 800-1200℃. The thickness of SiO2 can be accurately controlled by accurately controlling the oxidation time and temperature. Generally, the thickness of the oxidation medium layer 300 between the second substrate 200 and the sidewall covering layer 500 is greater than the thickness of the oxidation medium layer 300 between the second substrate 200 and the hard mask layer 400.
[0034] Generally, the hard mask layer 400 mainly functions as a mask layer in the etching process to protect the underlying material from being etched away. Generally, the material of the hard mask layer 400 includes silicon nitride (Si3N4), silicon dioxide (SiO2), silicon carbide (SiC), polysilicon or other materials with high hardness and etching resistance.
[0035] The semiconductor structure provided by the embodiment can effectively protect the substrate due to the presence of the oxidation medium layer 300. In the UTSV (through silicon via) etching process, the etching stops at the oxidation medium layer 300, avoiding over-etching of the second substrate 200. Moreover, due to the presence of the oxidation medium layer 300, the second substrate 200 can be protected by the sidewall covering layer 500, effectively preventing damage to the top of the second substrate 200, thereby ensuring the integrity of the substrate structure and helping to maintain the stable performance of the entire semiconductor structure.
[0036] The above embodiment only exemplarily illustrates the principle and effect of the present application, and is not intended to limit the present application. Any person skilled in the art can modify or change the above embodiment without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical concept disclosed by the present application shall be covered by the claims of the present application.
Claims
1. A semiconductor structure, characterized by, The application relates to a semiconductor device, comprising: a first substrate, which comprises a first metal interconnection layer and a first device layer above the first metal interconnection layer; a second substrate above the first substrate; a through hole, which penetrates the second substrate, the first device layer and exposes the first metal interconnection layer; an oxidation medium layer on the sidewall of the through hole and the surface of the second substrate on both sides of the through hole.
2. The semiconductor structure of claim 1, wherein, The second substrate comprises a substrate, and a second device layer and a second metal interconnection layer formed in the substrate.
3. The semiconductor structure of claim 1, wherein, Further comprising a hard mask layer above the second substrate.
4. The semiconductor structure of claim 3, wherein, Further comprising a sidewall covering layer covering the sidewall of the through hole.
5. The semiconductor structure of claim 2, wherein, The first metal interconnection layer and the second metal interconnection layer comprise a medium layer and a conductive circuit.
6. The semiconductor structure of claim 4, wherein, The thickness of the oxidation medium layer between the second substrate and the sidewall covering layer is greater than the thickness of the oxidation medium layer between the second substrate and the hard mask layer.
7. The semiconductor structure of claim 6, wherein, The thickness of the oxidation medium layer between the second substrate and the sidewall covering layer is between 200nm and 250nm, and the thickness of the oxidation medium layer between the second substrate and the hard mask layer is between 100nm and 125nm.
8. The semiconductor structure of claim 4, wherein, The through hole is formed with a flared mouth structure away from one side of the first substrate, the narrow end of the flared mouth structure is connected with the sidewall covering layer, and the wide end of the flared mouth structure is located on the hard mask layer.
9. The semiconductor structure of claim 8, wherein, The side edge of the flared mouth structure is formed in the oxidation medium layer, the sidewall covering layer and the hard mask layer.