Semiconductor structure

Abstract

The embodiment of the utility model provides a semiconductor structure, which comprises a substrate, a joint structure and a filling layer, wherein the joint structure and the filling layer are arranged on the substrate. The substrate includes an optically active region and an optical surface in the optically active region. The bonding structure includes a bonding dielectric layer and a conductive feature in the bonding dielectric layer and arranged outside an inhibiting region of the bonding structure, where in a first view, the inhibiting region is located within the optically active region and a first feature of the conductive feature is disposed between the optically active region and the inhibiting region. The fill layer is interposed between the bonding structure and the optically active region of the substrate. In a second view, the first feature is separated from the fill layer by bonding the dielectric layer. The semiconductor structure is provided with a prohibited region within which the optical surface is contained to ensure that the optical surface is not occluded when transmitting radiation.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor structure, and more particularly, to a semiconductor structure with optical components. BACKGROUND

[0002] Semiconductor structures that include both photonic integrated circuit (PIC) dies and electronic integrated circuit (EIC) dies are becoming increasingly popular due to their compactness. In addition, optical signals and processing have been used in more applications as fiber optic related applications are widely used for signal transmission. While existing methods of fabricating semiconductor structures with optical components are generally adequate for their intended purpose, they are not entirely satisfactory in all respects. For example, it is challenging to develop robust processes for coupling PIC dies and EIC dies while increasing the pitch and density of the bonding features. SUMMARY

[0003] Embodiments of the present application provide a semiconductor structure including a substrate, a bonding structure disposed over the substrate, and a fill layer. The substrate includes an optically active region and an optical surface in the optically active region, the bonding structure includes a bonding dielectric layer and a conductive feature in the bonding dielectric layer and disposed outside a forbidden region of the bonding structure, wherein in a first view, the forbidden region is located within the optically active region, and a first feature of the conductive feature is disposed between the optically active region and the forbidden region. The fill layer is interposed between the bonding structure and the optically active region of the substrate, wherein in a second view, the first feature is separated from the fill layer by the bonding dielectric layer.

[0004] Embodiments of the present application provide a semiconductor structure including a substrate, a dielectric layer, a fill layer, and a first bonding structure disposed over the dielectric layer and the fill layer. The substrate includes a first side, a second side opposite the first side, and a pattern at the first side, a portion of the pattern serving as an optical component. The dielectric layer is disposed at the first side of the substrate and includes a via corresponding to the pattern of the substrate, the fill layer is disposed in the via of the dielectric layer and over the pattern of the substrate. The first bonding structure includes a first bonding dielectric layer and a first conductive feature damascene in the first bonding dielectric layer, the first conductive feature is disposed over the dielectric layer and the fill layer and disposed outside a forbidden region, the optical component is disposed below the forbidden region, wherein the first conductive feature includes a dummy feature isolated from the fill layer by the first bonding dielectric layer.

[0005] Based on the above, the semiconductor structure of the embodiments of the present application is provided with a forbidden area, and the protruding part (for example, an optical component) of the substrate can be contained in the forbidden area to ensure that the protruding part will not be blocked when transmitting radiation. By configuring the first dummy feature on the first area, uniform pattern density in the entire first area can be achieved, thereby facilitating subsequent bonding processes. The dummy feature of the semiconductor structure includes a second feature disposed on the second area and outside the forbidden area. By configuring the second feature on the second area and outside the forbidden area, the bonding feature of the semiconductor structure can have more uniform pattern density and more uniform spacing in the first and second areas and both, while keeping the optical path unshielded.

[0006] In order to make the above-mentioned features and advantages of the embodiments of the present application more obvious and easy to understand, the following embodiments are specifically described, and the detailed description is made below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figures 1A-1G A schematic cross-sectional view showing an intermediate step during a process for forming a first device according to some embodiments is shown.

[0008] Figure 1H A schematic partial top plan view of a first device according to some embodiments is shown.

[0009] Figure 2 A schematic cross-sectional view of a semiconductor structure formed with a first die bonded to a second die according to some embodiments is shown.

[0010] Figure 3A And 3B A schematic cross-sectional view of a semiconductor structure optically coupled to an optical signal port according to some embodiments is shown.

[0011] Figure 4 A schematic cross-sectional view of a semiconductor structure optically coupled to an optical signal port according to some embodiments is shown.

[0012] REFERENCE NUMERALS

[0013] 10, 20: semiconductor structure; 10E: first device / first die; 10P, 20P: second die; 10Pw, 20Ew, 1062, 1092s: sidewall; 101, 101', 111, 201, 211: substrate; 101a: front surface; 101b: back surface; 102: device; 103: interconnect structure; 104: contact pad; 105: passivation layer; 105t, 107t, 108t, 1091t, 1092t: top surface; 105': passivation material layer; 106: pattern; 106W, 108W, 1063W, WK2: maximum lateral dimension; 107: protection layer; 108: fill layer; 108H, 1063H: maximum height; 109, 119: junction structure; 109t, 119t: junction surface; 113: optoelectronic circuit structure; 115: light guide assembly; 120: optical signal port; 1031: metallization pattern; 1032: patterned dielectric layer; 1032': dielectric layer; 1055: mask layer; 1055H: thickness; 1055': mask material layer; 1061: bottommost surface; 1063: protrusion / optical member; 1063a: convex top surface; 1091, 1191: junction dielectric layer; 1092, 1192: junction feature; 1092A, 1192A: active feature; 1092A1: pad portion; 1092A2: via portion; 1092D, 1192D: dummy feature; 1092D1: first feature; 1092D2: second feature; 1092D3: third feature; 1092m, 1092n: bottom surface; 1191t, 1192t: outermost surface; 20E: first die; 220: insulating layer; IF1: junction interface; R1: first region; R2: second region / optically active region; RK2, RK2': exclusion region; TH1: through hole; VD1: vertical distance. DETAILED DESCRIPTION

[0014] The following disclosure provides different embodiments or examples for implementing various features of the present disclosure. Specific examples of structures and arrangements are set forth in the following description for the purpose of simplicity and clarity. These are, of course, merely examples and are not intended to limit the scope of the present disclosure. For example, in the following description, a first feature formed "on" or "over" a second feature can include embodiments where the first feature is formed directly on the second feature or where additional features are formed between the first and second features such that the first feature is not directly on the second feature. Additionally, the present disclosure can repeat component or

[0015] Moreover, spatial or directional terms, such as "below", "under", "lower", "above", "upper" and the like, can be used herein for ease of describing the exemplary embodiments of the present disclosure with reference to the drawings. The spatial or directional terms are used with respect to the orientation of the figure(s) as drawn. However, an apparatus can assume various alternative orientations and, accordingly, the spatial or directional terms can be interpreted in the context of whatever particular orientation is assumed in use or operation by the apparatus.

[0016] Embodiments of the present disclosure are discussed in the context of semiconductor manufacturing and in particular in the context of forming a semiconductor structure comprising a photonic integrated circuit (PIC) die and an electronic integrated circuit (EIC) die. Some variations of embodiments are discussed and intermediate stages of forming a semiconductor structure are shown in accordance with some embodiments. It is to be understood that the drawings in all of the Figures are schematic and not drawn to scale.

[0017] Figures 1A-1G Schematic cross-sectional views of intermediate steps during a process for forming a first apparatus in accordance with some embodiments are shown. Figure 1H A schematic partial top plan view of a first apparatus in accordance with some embodiments is shown. It is noted that the first apparatus in Figure 1H The number of bonding features shown in Figure 1G does not correspond to the number of bonding features shown in Figure 1H The first apparatus in Figure 1G is similar to the first apparatus in Although method embodiments can be discussed as being performed in a particular order, other method embodiments can be performed in any logical order.

[0018] Figure 1A Referring to Figure 1G , a substrate 101'having a front surface 101a and a back surface 101b can be provided. In some embodiments, the substrate 101'comprises a first region R1 and a second region R2 connected to the first region R1. For example, the first region R1 is an electrically active region and the second region R2 is an optically active region in which one or more optical components are to be formed. One or more electrical components for transmitting electrical signals can be formed in / over the first region R1 and one or more optical components for transmitting optical signals can be formed in / over the second region R2. It is noted that the first region R1 can also represent the first region R1 of the first apparatus 10E (see

[0019] The material of the substrate 101' is not particularly limited. For example, the substrate 101' includes a material capable of transmitting radiation of at least one wavelength of interest. The wavelength of interest can fall in any useful region of the electromagnetic spectrum, such as in the ultraviolet range, in the visible range, or in the infrared range. In some embodiments, the wavelength of interest is not a single wavelength only, and such multiple individual wavelengths can fall within one or more of the above-mentioned ranges. In some embodiments, the material of the substrate 101' is selected according to its refractive index at the wavelength(s) of interest. In some embodiments, the substrate 101' is a semiconductor substrate. For example, the material of the substrate 101' includes one or more semiconductor materials, which can be elemental semiconductor materials (e.g., Si, Ge, or the like), compound semiconductor materials (e.g., SiC, SiGeC, or the like), or alloy semiconductor materials (e.g., SiGe, GaAsP, AlInAs, or the like). In some embodiments, the substrate 101' is an inorganic substrate including one or more dielectric materials (e.g., silicon oxide, silicon nitride, silicon carbide, or the like). In some embodiments, the substrate 101' includes one or more organic dielectrics (e.g., epoxy, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or the like).

[0020] In some embodiments, one or more devices 102 are formed in / on the front surface 101a of the substrate 101'. The devices 102 can be or include active devices (e.g., transistors, diodes, etc.), capacitors, resistors, or the like. The devices 102 can be formed by front-end-of-line (FEOL) and can be referred to as FEOL devices. Although the devices 102 are represented by a single transistor, it is understood that the disclosure is not limited to the type and number of devices 102. In some embodiments, interconnect structures 103 are formed over the substrate 101' and are interconnected with the devices 102 to form an integrated circuit. The interconnect structures 103 can include metallization patterns 1031 formed in one or more dielectric layers 1032'. The dielectric layers 1032' can include one or more low-k dielectric materials or any suitable dielectric material. The metallization patterns 1031 can include wires, conductive pads, vias, etc. For example, when the devices 102 are transistors, the bottommost vias (or conductive plugs) 1031V of the metallization patterns 1031 are coupled with the gates and source / drain regions of the transistors. The interconnect structures 103 are formed by back-end-of-line (BEOL) and can be referred to as BEOL structures, for example.

[0021] With continued reference to Figure 1AOne or more contact pads 104 (e.g., aluminum pads, aluminum-copper pads, or the like) can be formed on one of the topmost ones of the metallization patterns 1031. In some embodiments, the contact pads 104 are embedded in a dielectric layer 1032'. In some embodiments, a passivation material layer 105' is formed on the dielectric layer 1032' and over the contact pads 104. In some embodiments, the passivation material layer 105' includes one or more layers of silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof. In some embodiments, the passivation material layer 105' acts as a stop layer to stop an etch / removal process thereon.

[0022] Referring to Figure 1B and referring to Figure 1A , a mask material layer 1055' can be formed on the passivation material layer 105'. In some embodiments, the mask material layer 1055' acts as a hard shield for patterning the substrate 101' (see Figure 1D ). The mask material layer 1055' can include a silicon-containing material (e.g., silicon oxide, silicon nitride, etc.), a metal-containing material (e.g., titanium nitride, titanium oxide, etc.), combinations thereof, and / or the like. The material of the mask material layer 1055' can be different from the material of the underlying passivation material layer 105'. In some embodiments, the mask material layer 1055' includes a positive photoresist or a negative photoresist. In some embodiments, the mask material layer 1055' is formed by depositing a layer of mask material by any suitable deposition process (e.g., spin coating, chemical vapor deposition (CVD), etc.) and planarizing the layer of mask material by any suitable process (e.g., chemical mechanical polishing (CMP), etching, combinations thereof, etc.). For example, the mask material layer 1055' is polished to form a substantially planar surface. In some embodiments, after the planarization (e.g., polishing) process, the mask material layer 1055' is thinned to have a thickness 1055H (e.g., about 1 pm or less, although the present disclosure is not limited thereto). The thinner mask material layer 1055' can allow the creation of perforations (see Figure 1C ) with improved aspect ratios.

[0023] Referring to Figure 1C and referring to Figure 1Bportions of the dielectric layer 1032' to form a mask layer 1055, a passivation layer 105, and a patterned dielectric layer 1032, respectively. For example, one or more through holes TH1 are formed through the mask layer 1055, the passivation layer 105, and the patterned dielectric layer 1032. In some embodiments, the through holes TH1 are formed by a photolithography and etching process or any suitable removal process. The front surface 101a of the substrate 101' can be exposed in an accessible manner by the through holes TH1, and the through holes TH1 can be formed over and corresponding to the second region R2. Although only a single through hole TH1 is shown in the cross-sectional view of FIG. 10B, it is understood that the size and number of the through holes can vary depending on product requirements and do not constitute a limitation to the present disclosure. Figure 1C

[0024] Referring to FIG. 10A, Figure 1D and referring to FIG. 10B, Figure 1C The substrate 101' exposed in an accessible manner by the through holes TH1 can be patterned to form a substrate 101 including a pattern 106. For example, one or more etching processes are performed on the front surface 101a' of the substrate 101' using the mask layer 1055 as an etching mask to form the pattern 106. The pattern 106 can be recessed and located within the second region R2. The etching conditions can be selected such that the height level of the pattern 106 is lower than the height level of the device 102 with respect to the back surface 101b of the substrate 101. The etching can be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. In some embodiments, the etching is anisotropic. Depending on the material properties of the mask layer 1055 and the process recipe of the removal process, the mask layer 1055 can be removed to expose the top surface 105t of the passivation layer 105 during or after the patterning process of the substrate 101'. In other embodiments, the mask layer 1055 is removed by ashing, peeling, or the like after the patterning of the substrate. In some embodiments, the passivation layer 105 acts as an etching stop layer during the removal of the mask layer 1055.

[0025] ​In some embodiments, the pattern 106 has a bottommost surface 1061 under the front surface 101a of the substrate 101, a sidewall 1062 connected to the bottommost surface 1061, and one or more protrusions (or raised structures) 1063 protruding from the bottommost surface 1061. The sidewall 1062 can be substantially perpendicular or can be tilted with respect to the bottommost surface 1061, where the tilt angle of the sidewall 1062 is not particularly limited. In some embodiments, the protrusions 1063 act as lenses that include a convex top surface 1063a connected to the bottommost surface 1061. For example, the convex top surface 1063a is circular (e.g., curved outwardly from the bottommost surface 1061). In some embodiments, the topmost point of the convex top surface 1063a is between the highest point of the front surface 101a and the bottommost surface 1061. The convex top surface 1063a can be considered an optical surface. In some embodiments, the protrusions 1063 have a maximum lateral size 1063W that is smaller than the maximum lateral size 106W of the pattern 106. In some embodiments, the protrusions 1063 have a maximum height 1063H measured between the highest point of the protrusions 1063 and a virtual plane extending from the bottommost surface 1061. The maximum height 1063H of the protrusions 1063 can be smaller than a vertical distance VD1 measured between the highest point of the front surface 101a and the bottommost surface 1061.

[0026] The protrusions 1063 can have any suitable cross-sectional profile (e.g., semi-circular profile, rectangular profile, trapezoidal profile, triangular profile, bell-shaped profile, combinations thereof, the like, etc.). In some embodiments, the plurality of protrusions 1063 formed in the second region R2 have the same cross-sectional shape and can be arranged in an array. In some embodiments, more than one protrusion 1063 formed in the second region R2 has a cross-sectional shape that is different from one another. The shape and size of the protrusions 1063 can be selected according to application requirements. In some embodiments, the pattern 106 in the second region R2 is configured to have a lens effect on incident radiation of a selected wavelength, and acts as a lens of a particular focal length for the incident radiation. Although lenses have been described as an example, the present disclosure is not limited thereto. For example, the substrate 101’ is patterned to form an optical component, such as a grating coupler, a waveguide pattern, a modulator, a multiplexer, combinations thereof, and / or the like. It should be understood that other optical effects can be achieved by adjusting the formation conditions of the pattern 106.

[0027] Referring to Figure 1E and referring to Figure 1DA protective layer 107 can be formed on the passivation layer 105 and in the through-hole TH1 using any suitable method such as CVD, ALD, sputtering, evaporation, or the like. For example, the protective layer 107 is a conformal film overlying the top surface 105t of the passivation layer 105, lining the inner sidewalls of the passivation layer 105 and the patterned dielectric layer 1032, and overlying the pattern 106. The protective layer 107 can be a liner, and the through-hole TH1 can be lined with the protective layer 107. In some embodiments, the protective layer 107 blanketly covers the bottommost surface 1061, the sidewalls 1062, and the convex top surface 1063a of the protrusion 1063. The protective layer 107 can be a single layer or a composite layer including multiple sub-layers of different materials. The protective layer 107 can be or include one or more dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, titanium nitride, or other suitable materials. In some embodiments, the protective layer 107 is or includes a film of light-absorbing material such as an anti-reflective coating (ARC) or the like. For example, the protective layer 107 is transparent to the target light wavelength (e.g., the light wavelength for infrared radiation). The protective layer 107 can be configured to minimize the reflection of light emitted from the light source into / out of the optical member 1063 (e.g., a lens), thereby reducing optical loss. In some embodiments, the protective layer 107 is or includes a stop layer to stop a polishing / etching / removing process thereon. It should be noted that the material, refractive index, and thickness of the protective layer 107 can be selected according to the application needs. Alternatively, the protective layer 107 can be omitted.

[0028] Referring to Figure 1F and referring to Figure 1E A fill layer 108 can be formed in the remaining space of the through-hole TH1. The fill layer 108 can be formed according to any suitable process such as CVD, PVD, ALD, or the like. In some embodiments, a planarization process (e.g., polishing, CMP, etching, a combination thereof, or the like) is performed after the material of the fill layer 108 is disposed in the through-hole TH1. After planarization, the top surface 108t of the fill layer 108 and the top surface 107t of the protective layer 107 can be substantially flush (or coplanar) within process variation. The material of the fill layer 108 is not particularly limited and can be selected according to the refractive index thereof and the refractive index of the material of the protective layer 107 (if present). The fill layer 108 can be transparent to light radiation in the target wavelength range. For example, the fill layer 108 includes an inorganic material such as an oxide (e.g., silicon oxide), a nitride, a carbide, or the like. The fill layer 108 and the protective layer 107 can include the same material. In some embodiments, the fill layer 108 and the protective layer 107 include different materials, optionally with matching refractive indices to achieve a desired optical effect on the incident radiation.

[0029] Since the mask layer 1055 is removed before the protective layer 107 is formed, the protective layer 107 can be formed directly on the top surface 105t of the passivation layer 105. The fill layer 108 can be formed directly on the protective layer 107 within the via TH1. It should be understood that if the mask layer 1055 is not removed before the fill layer is formed, the presence of the mask layer 1055 will result in the fill layer 108 having a high aspect ratio. By removing the mask layer 1055 before the fill layer 108 is formed, the maximum height 108H of the fill layer 108 in the via TH1 can be reduced. Figures 1D-1F The process allows for a reduction in the aspect ratio of the filler layer 108 (e.g., maximum height 108H / maximum lateral size 108W). The improved aspect ratio of the filler layer 108 can contribute to better optical performance.

[0030] Reference Figure 1G And refer to Figure 1F The bonding structure 109 may be formed on the protective layer 107 (if present) and the filler layer 108. For example, the bonding structure 109 includes a bonding dielectric layer 1091 and a bonding feature 1092 covered by the bonding dielectric layer 1091. The bonding dielectric layer 1091 may be a single layer or may include multiple stacked dielectric layers. The material of the bonding dielectric layer 1091 may include inorganic materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or combinations thereof. The bonding dielectric layer 1091 may be formed by suitable manufacturing techniques (e.g., spin coating, CVD, ALD, PVD, or similar). The bonding feature 1092 may include one or more conductive materials, such as copper, cobalt, tungsten, titanium, tantalum, aluminum, zirconium, hafnium, alloys, combinations thereof, or other suitable metallic materials. The bonding feature 1092 may be formed by a damascene process (e.g., single damascene and / or dual damascene). For example, the bonding feature 1092 is formed by forming a trench in the bonding dielectric layer 1091 and filling the trench with conductive material by means of PVD, CVD, plating, combinations thereof, and / or the like. In some embodiments, a planarization process (e.g., polishing, CMP, etching, combinations thereof, or the like) is performed on the bonding structure 109. After planarization, the top surface 1091t of the bonding dielectric layer 1091 and the top surface 1092t of the bonding feature 1092 may be substantially flush (or coplanar) within a range of process variations. The top surfaces (1091t and 1092t) can be collectively considered as the bonding surface 109t of the bonding structure 109. Figure 1G The structure shown can be considered as a first device 10E having an optical active region R2. In some embodiments, the first device 10E is provided in wafer form. In some embodiments, the wafer-form first device 10E is monomerized to form a plurality of first dies (e.g., ...) prior to the bonding process. Figure 2 (As shown). In some embodiments, the first die / device is considered an electronic (or electronic integrated circuit (EIC)) die / device.

[0031] Referring to Figure 1H and referring to Figure 1G , except that the number of bonding features 1092 does not correspond to Figure 1H the number of bonding features 1092 shown, Figure 1G the top view of the first device 10E in Figure 1G may be similar to the top view shown in Figure 1H . In some embodiments, the bonding features 1092 are distributed in an array on the bonding dielectric layer 1091, except for a keep-out zone RK2. The keep-out zone RK2 can be used to define an area in which bonding features (or other features / devices) cannot be placed. In some embodiments, the keep-out zone RK2 is located within the second region R2 and can have a maximum lateral size WK2 that is less than the maximum lateral size 108W of the fill layer 108. The maximum lateral size WK2 of the keep-out zone RK2 can be greater than or substantially equal to the maximum lateral size 1063W of the protrusion 1063 (indicated in Figure 1D ). In the top view, the boundaries of the protrusion 1063 (e.g., optical member) can be contained within the keep-out zone RK2 to ensure that the protrusion 1063 is not obstructed when transmitting radiation. In the illustrated embodiment, the top view shape of the keep-out zone RK2 is rectangular (or square) and the top view shape of the protrusion 1063 is circular (or elliptical). Other shapes and sizes can also be had, and the keep-out zone RK2 and the protrusion 1063 can have different numbers and arrangements than shown.

[0032] With continued reference to Figures 1G-1HIn some embodiments, the bonding features 1092 include one or more active features 1092A electrically and physically connected to the contact pads 104 (and / or the metallization pattern 1031 of the interconnect structure 103). For example, a respective active feature 1092A includes a pad portion 1092A1 and a via portion 1092A2 connected to the pad portion 1092A1 and the contact pad 104, where the pad portion 1092A1 is embedded in the bonding dielectric layer 1091. A respective via portion 1092A2 can pass through the bonding dielectric layer 1091, the protection layer 107, the passivation layer 105, and the patterned dielectric layer 1032. A bottom surface 1092m of a respective via portion 1092A2 can be connected to the contact pad 104. The via portion 1092A2 can be tapered in the same direction as the taper direction of the via of the metallization pattern 1031 of the interconnect structure 103. In alternative embodiments, a respective active feature 1092A is a via having a wider top portion exposed by the bonding dielectric layer 1091 and a narrower bottom portion landing on the contact pad 104. In the illustrated embodiment, the active features 1092A have a circular (or elliptical) top-down shape, and all (or substantially all) of the active features 1092A can have the same top-down shape, the same top-down size, and / or the same pitch to have a uniform pattern density throughout the first device 10E. Other shapes can also be possible, and the active features 1092A can have different numbers and arrangements than illustrated.

[0033] Continuing to refer to FIG. 10A, Figures 1G-1H In some embodiments, a respective dummy feature 1092D is a conductive pad (or a bonding pad) having a top surface 1092t exposed by the bonding dielectric layer 1091, and a bottom surface 1092n and sidewalls 1092s of the dummy feature 1092D are physically covered by the bonding dielectric layer 1091. By configuring the dummy features 1092D, the pattern-loading effect and the dishing effect can be reduced, and the bonding surface 109t can be more planar to facilitate subsequent bonding processes (see, e.g., FIG. 10B). Figure 2). In the illustrated embodiment, the dummy features 1092D have a circular (or elliptical) top-down shape, and the dummy features 1092D and the active features 1092A can all (or substantially all) have the same top-down shape, the same top-down size, and / or the same pitch. By configuring the dummy features 1092D to have substantially the same top-down shape / size / pitch as the active features 1092A, a more uniform pattern density can be achieved on the bonding surface 109t of the first device 10E to facilitate subsequent bonding processes. Other shapes, sizes, and pitches can also be possible, and the dummy features 1092D can have different numbers and arrangements than illustrated.

[0034] In some embodiments, the dummy features 1092D include one or more first features 1092D1 disposed directly above the first region Rl, and can be disposed alongside (or around) the active features 1092A to increase the metal density within the first region Rl. The first features 1092D1 can be separated from the passivation layer 107 by the bonding dielectric layer 1091. By configuring the first features 1092D1 over the first region Rl, a uniform pattern density can be achieved throughout the first region Rl, facilitating subsequent bonding processes. In some embodiments, the dummy features 1092D include one or more second features 1092D2 disposed over the second region R2 and outside the exclusion region RK2. By configuring the second features 1092D2 over the second region R2 and outside the exclusion region RK2, the bonding features 1092 can have a more uniform pattern density and a more uniform pitch in both the first and second regions Rl and R2, while maintaining the optical path unshielded.

[0035] Still referring to Figure 1G-1HDummy features 1092D can include one or more third features 1092D disposed directly above the interface of first region Rl and second region R2. For example, in a top view, a vertical projection of third feature 1092D3 overlies directly the boundary of fill layer 108 and the interface of fill layer 108 and passivation layer 107. In a cross-sectional view, third feature 1092D3 can be spatially separated from fill layer 108 and passivation layer 107 by bonding dielectric layer 1091. It should be understood that the materials in bonding dielectric layer 1091, fill layer 108, and passivation layer 107 can be different, differing in etch rate of bonding dielectric layer 1091, etch rate of fill layer 108, and etch rate of passivation layer 107. When etching an opening at the interface of bonding dielectric layer 1091, fill layer 108, and passivation layer 107, it is difficult to control etch uniformity, where third feature 1092D3 is to be formed in the opening. Since dummy feature 1092D is formed in the opening of bonding dielectric layer 1091 without extending into direct contact with fill layer 108 and passivation layer 107, a more uniform profile of dummy feature 1092D, particularly third feature 1092D3, can be achieved.

[0036] Figure 2 A schematic cross-sectional view of a semiconductor structure formed with a first die bonded to a second die is shown in accordance with some embodiments. Unless otherwise noted, the materials of the components in these embodiments are substantially the same as the similar components in the embodiments shown in Figures 1A-1H and are denoted by similar reference numbers.

[0037] Referring to Figure 2 and to Figure 1G , semiconductor structure 10 includes a second die 10P stacked on and bonded to a first die 10E. Semiconductor structure 10 can have EIC-PIC integration with electrical interfaces designed to minimize coupling losses. For example, first die 10E is an electronic (or EIC) die, while second die 10P is a photonic (or photonic integrated circuit, PIC) die. First die 10E can be similar to Figures 1G-1HThe second die 10P can include any semiconductor photonic integrated circuit. For example, the second die 10P includes a substrate 111 and a photonic circuit structure 113 formed above the substrate 111. The material of the substrate 111 can be similar to the substrate 101 of the first die 10E. The photonic circuit structure 113 can be configured to integrate a plurality of photonic functions for optical information signals received via, for example, optical fibers. The photonic circuit structure 113 can be configured to convert optical signals to electrical signals, or vice versa. In some embodiments, the second die 10P includes one or more active and / or passive optical devices (not shown separately) responsible for the input / output (I / O) of optical signals to / from the optical signal ports. The active and / or passive optical devices can include couplers, lasers, optical modulators, detectors, waveguides, splitters, transducers, switches, etc. In some embodiments, the optical devices are formed in the photonic circuit structure 113 to guide light / signal from the optical signal ports coupled thereto.

[0038] In some embodiments, the second die 10P includes a bonding structure 119 formed above the photonic circuit structure 113. The bonding structure 119 can be similar to the bonding structure 109 of the first die 10E. For example, the bonding structure 119 includes a bonding dielectric layer 1191 and bonding features 1192 covered by the bonding dielectric layer 1191. The materials and formation methods of the bonding dielectric layer 1191 and the bonding features 1192 can be similar to the bonding dielectric layer 1091 and the bonding features 1092, respectively. The bonding features 1192 can include active features 1192A and dummy features 1192D. The active features 1192A can be similar to the active features 1092A and the dummy features 1192D can be similar to the dummy features 1092D. In some embodiments, the first die 10E and the second die 10P are electrically connected through the active features (1192A and 1092A). For example, the first die 10E receives and processes electrical signals generated by the second die 10P upon detecting incident radiation. In some embodiments, the distribution layout of the bonding features 1192 of the second die 10P corresponds to the distribution layout of the bonding features 1092 of the first die 10E. For example, the second die 10P includes a forbidden region RK2’ in which no conductive features are formed to ensure that conductive features in the second die 10P do not block optical paths. The first die 10E and the second die 10P can be optically coupled to each other in the second region R2 (e.g., an optical active region). For example, the second die 10P converts optical signals from the optical signal ports to electrical signals and transmits the electrical signals to the first die 10E.

[0039] The outermost surfaces 1191t of the bonding dielectric layers 1191 and the outermost surfaces 1192t of the bonding features 1192 can be substantially flush (or coplanar) to facilitate the bonding process. The outermost surfaces (1191t and 1192t) can be collectively considered as a bonding surface 119t of the bonding structure 119. For example, the bonding involves wafer-to-wafer bonding. In such embodiments, the EIC wafer and the PIC wafer are bonded together, and then a singulation process is performed to form individual semiconductor structures 10 in which the lateral size of the first die 10E is substantially equal to the lateral size of the second die 10P. In some other embodiments, the bonding involves die-to-wafer bonding, one of the EIC wafer and the PIC wafer is singulated into an individual die having a desired size, and then the singulated die is bonded with the other one of the EIC wafer and the PIC wafer, in which the singulated die is smaller in lateral size than the wafer.

[0040] With continued reference to Figure 2 and Figure 1G According to some embodiments, the bonding process can include the following steps. For example, a surface treatment (e.g., cleaning, activation, a combination thereof, etc.) can be performed on the bonding surfaces (119t and 109t) to be bonded. After the surface treatment, the second die (or wafer) 10P can be substantially aligned with the first die (or wafer) 10E. For example, each bonding feature 1192 of the second die (or wafer) 10P can be substantially aligned with a corresponding bonding feature 1091 of the first die (or wafer) 10E. The keep-out region RK2’ of the second die (or wafer) 10P can be substantially aligned with the keep-out region RK2 of the first die (or wafer) 10E. Next, the bonding surface 119t of the bonding structure 119 can be brought into contact with the bonding surface 109t of the bonding structure 109. After bringing the second die (or wafer) 10P into contact with the first die (or wafer) 10E, a bonding process can be performed. For example, the bonding process includes a thermal treatment for dielectric bonding and a thermal anneal for conductor bonding. After the thermal anneal, the bonding dielectric layers (1191 and 1091) can be fused together, and the bonding features (1192 and 1092) can be bonded together. When the keep-out region RK2’ is aligned and bonded together with the keep-out region RK2, the bonding yield of the first and second dies (or wafers) can be improved while keeping the optical path in the semiconductor structure 10 unblocked.

[0041] The bond at the junction interface IF1 of the first die (or wafer) 10E and the second die (or wafer) 10P can include a dielectric-to-dielectric bond (e.g., oxide-to-oxide bond), a metal-to-metal bond (e.g., copper-to-copper bond), a metal-to-dielectric bond (e.g., copper-to-oxide bond), any combination thereof, and / or the like. The junction interface IF1 can be substantially planar and / or flat. It should be noted that the pad-to-pad junction shown here is merely an example, and via-to-via or via-to-pad junctions can be employed according to some embodiments. It should be understood that while a junction connecting the second die (or wafer) 10P to the first die (or wafer) 10E has been described, alternative connection schemes are possible and the junction interface would be adjusted accordingly.

[0042] Figure 3A and 3B A schematic cross-sectional view of a semiconductor structure optically coupled to an optical signal port is shown, in accordance with some embodiments. The materials of the components in these embodiments are substantially the same as those in the embodiments shown in Figure 1H and Figure 2 , which are represented by like reference numbers.

[0043] Referring to Figure 3A and to Figure 2 , the optical signal port 120 can be optically coupled to the semiconductor structure 10. The semiconductor structure 10 can be similar to the semiconductor structure described in Figure 2 . The optical signal port 120 can be an optical input / output (I / O) port through which optical signals can enter and / or exit. For example, the optical signal port 120 includes at least one optical fiber facing an optical component in the semiconductor structure 10. In some embodiments, the optical signal port 120 includes a plurality of optical fibers arranged in an array, and the array of optical components 1063 can be optically coupled to the array of optical fibers in a one-to-one correspondence. In some embodiments, the optical signal port 120 is affixed to the backside of the substrate 101 of the first die 10E by, for example, an optical adhesive or the like (not shown). Other affixing mechanisms can be employed depending on product requirements.

[0044] In some embodiments, the light beam carrying the optical signal from the optical signal port 120 passes through the substrate 101, the protection layer 107 (if present), the fill layer 108, the bonding structure 109, and towards the second die 10P in sequence. In some embodiments, the optically active region R2 has a lensing effect on the incident radiation of the selected wavelength. For example, the protrusion 1063 in the optically active region R2 acts as an optical member (e.g., a lens) with a specific focal length for the incident radiation. In some embodiments, the optical signal port 120 is disposed directly below the optically active region R2 and optically aligned with the optical member 1063 in the first die 10E. The optical member 1063 as a lens (or focusing component) can be used to direct the light from the optical signal port 120 to the second die 10P. The optical member 1063 can have a predetermined focal length that can focus the light rays onto the second die 10P. The second die 10P can convert the optical signal from the optical signal port 120 into an electrical signal and transmit the electrical signal to the first die 10E. In some other embodiments, the optical signal port 120 is disposed directly above the second die 10P and optically aligned with the optical member 1063. It should be noted that the transmission path is shown in dashed arrows as an example and can be adjusted according to the position / shape / configuration of the optical member 1063 and the application requirements. Moreover, the optical signal port 120 can have a different configuration than shown.

[0045] Referring to Figure 3B and referring to Figure 3A , Figure 3B The structure shown is similar to the structure shown in Figure 3A . The difference between the two is that the optical signal port 120 is optically aligned with the sidewall 10Pw of the second die 10P. For example, a light guiding assembly 115 (e.g., an edge coupler, a waveguide, a grating coupler, a reflector, the like, a combination thereof, or any appropriate optical assembly) is disposed at the sidewall 10Pw that is optically aligned with the optical signal port 120. The light guiding assembly 115 can be embedded in the optoelectronic circuit structure 113 or can be integrated into the substrate 111. In some embodiments, the light beam carrying the optical signal from the optical signal port 120 enters the second die 10P, guided by the light guiding assembly 115, and passes through the optoelectronic circuit structure 113, the bonding structures (119 and 109), the fill layer 108, and the protection layer 107 (if present) in sequence. The optical input is shown in dashed arrows as an example. Although in Figures 3A-3BThe lens effect has been described as an example, but the disclosure is not limited thereto, and other optical effects or combinations thereof can be achieved by adjusting the shape of the protrusions 1063 to define the pattern 106 in the optically active region R2. For example, the optically active region R2 has a lens effect, a polarization effect, a filtering effect, a combination thereof, or the like. The semiconductor structure 10 including the second die 10P bonded to the first die 10E can have flexibility to integrate with a packaging member to form a semiconductor package. For example, the semiconductor structure 10 is part of a photonic processing system that combines photonic components into a single compact unit.

[0046] Figure 4 A schematic cross-sectional view of a semiconductor structure optically coupled to an optical signal port is shown in accordance with some embodiments. The materials of the components in these embodiments are substantially the same as the similar components in the embodiments shown in Figure 1H , 2 and 3A-3B, which are indicated by similar reference numbers.

[0047] Referring to Figure 4 and to Figure 1H , Figure 2 and Figures 3A-3B , a semiconductor structure 20 including a first die 20E bonded to a second die 20P is provided. The first die 20E can be similar to the first die 10E. In some embodiments, the first die 20E is an electronic (or EIC) die. For example, the first die 20E includes a substrate 201, one or more devices 102 formed in / on the substrate, an interconnect structure 103 formed over the substrate 201 and electrically connected to the devices 102, a passivation layer 105 formed over the interconnect structure 103, and a bonding structure 109 formed over the passivation layer 105 and electrically connected to the interconnect structure 103. The substrate 201 of the first die 20E can be similar to the substrate 101 of the first die 10E, except that the substrate 201 can not have the pattern 106. In some embodiments, the first die 20E does not have the pattern 106, the protection layer 107, and the fill layer 108. The second die 20P can be similar to the second die 10P. In some embodiments, the second die 20P is a photonic (or PIC) die. In some embodiments, the second die 20P includes a substrate 211 having the pattern 106, a protection layer 107 overlying the pattern 106, a fill layer 108 overlying the protection layer 107 and directly over the pattern 106, and a bonding structure 119 bonded to the bonding structure 109 of the first die 20E. The substrate 211 can be similar to the substrate 101 described earlier. The second die 20P can be electrically coupled to the first die 20E through the bonding features (1192 and 1092). The formation methods and materials of the pattern 106, the protection layer 107, and the fill layer 108 can be similar to those of the pattern 106, the protection layer 107, and the fill layer 108, respectively, described earlier. Figures 1D-1FMethods of forming and materials for the pattern 106, the protective layer 107, and the fill layer 108 described herein.

[0048] In some embodiments, the protrusions 1063 of the pattern 106 serve as optical components (e.g., lenses or any suitable optical components). The second die 20P can include a keep-out region RK2’ in which the protrusions 1063 are formed. The fill layer 108, the optical components 1063, and the protective layer 107 (if present) can be collectively considered as an optical module, and the optical module can be implemented as part of an integrated photonics engine on the first die and / or the second die, depending on application needs. In some embodiments, the lateral size of the first die 20E is smaller than the second die 20P, and an insulating layer 220 is formed on the second die 20P and covers the sidewall 20Ew of the first die 20E. The insulating layer 220 can be or include one or more insulating materials (e.g., oxide, nitride, carbide, combinations thereof, etc.). For example, the insulating layer 220 includes a material such as a polymer that allows light transmission. The insulating layer 220 can be fused to the bonding dielectric layer 1191 and disposed directly above the fill layer 108. For example, the interface of the sidewall 20Ew of the first die 20E and the insulating layer 220 is laterally offset from the boundary of the fill layer 108 (or at least the keep-out region RK2’) to ensure that the optical path is not shielded or blocked.

[0049] In some embodiments, the optical signal port 120 is optically coupled to the semiconductor structure 20. For example, the optical signal port 120 is optically aligned with the optical components (e.g., lenses) 1063 in the second die 20P. In some embodiments, a light beam carrying an optical signal from the optical signal port 120 sequentially passes through the insulating layer 220, the bonding structure 119, the fill layer 108, and the protective layer 107 (if present). The transmission path is shown as an example with dashed arrows. For example, the light beam from the optical signal port 120 passing through the optical components 1063 can be desirably incident on one or more optical devices in the second die 20P (or the first die 20E). The second die 20P can convert the optical signal from the optical signal port 120 into an electrical signal and transmit the electrical signal to the first die 20E. It should be noted that the optical signal port 120, the transmission path, and the semiconductor structure 20 can have different arrangements than shown.

[0050] Other features and processes can also be included. For example, test structures can be included to facilitate verification testing of the 3D package or 3DIC device. The test structures can include, for example, test pads formed on a redistribution layer or a substrate that allow testing of the 3D package or 3DIC using probes and / or probe cards, etc. Verification testing can be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein can be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce cost.

[0051] According to some embodiments, a semiconductor structure includes a substrate, a bonding structure disposed over the substrate, and a fill layer. The substrate includes an optically active region and an optical surface in the optically active region. The bonding structure includes a bonding dielectric layer and a conductive feature in the bonding dielectric layer and disposed outside a forbidden region of the bonding structure, where in a first view, the forbidden region is located within the optically active region and a first feature of the conductive feature is disposed between the optical active region and the forbidden region. The fill layer is interposed between the bonding structure and the optically active region of the substrate. In a second view, the first feature is separated from the fill layer by the bonding dielectric layer.

[0052] In some embodiments, the semiconductor structure further includes an electrical device disposed on the same side as the optical surface of the substrate and an interconnect structure disposed between the substrate and the bonding structure and electrically coupled to the electrical device and the bonding structure, where the fill layer traverses the interconnect structure. In some embodiments, the conductive feature includes a second feature that traverses the bonding dielectric layer and lands on a metal pattern of the interconnect structure. In some embodiments, the semiconductor structure further includes a protective layer conformally covering the optical surface of the substrate to separate the fill layer from the optical surface of the substrate. In some embodiments, the protective layer is an anti-reflective coating. In some embodiments, in the first view, the first feature overlaps a boundary of the fill layer. In some embodiments, the first feature of the conductive feature is a dummy pad that is electrically floating. In some embodiments, a highest point of the optical surface is between a highest point of the substrate and a lowest point of the substrate. In some embodiments, the optical surface includes a lens shape in the second view. In some embodiments, the bonding dielectric layer and a bonding surface of the conductive feature facing away from the substrate are substantially flush.

[0053] According to some alternative embodiments, a semiconductor structure includes a substrate, a dielectric layer, a fill layer, and a first bonding structure disposed over the dielectric layer and the fill layer. The substrate includes a first side, a second side opposite the first side, and a pattern on the first side, and portions of the pattern serve as optical members. The dielectric layer is disposed on the first side of the substrate and includes perforations corresponding to the pattern of the substrate. The fill layer is disposed in the perforations of the dielectric layer and over the pattern of the substrate. The first bonding structure includes a first bonding dielectric layer and a first conductive feature embedded in the first bonding dielectric layer, the first conductive feature being disposed over the dielectric layer and the fill layer and arranged outside a forbidden region, the optical members being disposed under the forbidden region. The first conductive feature includes a dummy feature isolated from the fill layer by the first bonding dielectric layer.

[0054] In some embodiments, the semiconductor structure further includes an antireflection coating conformally covering the pattern of the substrate to separate the pattern of the substrate from the fill layer. In some embodiments, the semiconductor structure further includes an interconnect trace embedded in the dielectric layer and electrically coupled to the first conductive feature. In some embodiments, the pattern of the substrate includes a protrusion having a convex surface and acting as a lens. In some embodiments, the substrate, the dielectric layer, the fill layer, and the first bonding structure are part of a first die, and the semiconductor structure further includes a second die stacked on the first die and including a second bonding structure, the second bonding structure including a second bonding dielectric layer bonded to the first bonding dielectric layer and a second conductive feature bonded to the first conductive feature. In some embodiments, the first die is an electronic die and the second die is a photonic die.

[0055] According to some alternative embodiments, a method of manufacturing a semiconductor structure includes forming a dielectric layer on a substrate; forming a via in the dielectric layer to expose a portion of the substrate; patterning the portion of the substrate to form an optical surface; forming a fill layer in the via of the dielectric layer and over the optical surface of the substrate; and forming a bonding structure over the dielectric layer and the fill layer, wherein the bonding structure includes a bonding dielectric layer and a conductive feature in the bonding dielectric layer, the conductive feature is disposed outside a forbidden zone, the optical surface of the substrate is formed below the forbidden zone, and the conductive feature includes a dummy feature isolated from the fill layer by the bonding dielectric layer.

[0056] In some embodiments, the method of manufacturing further includes, prior to forming the fill layer, lining the via of the dielectric layer and the optical surface of the substrate with a protective layer. In some embodiments, the method of manufacturing further includes, prior to forming the bonding structure, planarizing the fill layer. In some embodiments, the method of manufacturing further includes planarizing the bonding dielectric layer and the conductive feature to level the bonding surfaces of the bonding dielectric layer and the conductive feature.

[0057] Finally, it should be noted that the above-mentioned embodiments are merely used to describe the technical solutions of the present application, rather than limiting them; although the above-mentioned embodiments of the present application have been described in detail, those skilled in the art should understand that they can still modify the technical solutions recorded in the above-mentioned embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes an optical active region and an optical surface within the optical active region; A bonding structure is disposed on the substrate, the bonding structure including a bonding dielectric layer and a conductive feature disposed in the bonding dielectric layer and outside a forbidden region of the bonding structure, wherein, in a first view, the forbidden region is located within the optical active region, and a first feature of the conductive feature is disposed between the optical active region and the forbidden region. as well as A filler layer is interposed between the optically active region of the bonding structure and the substrate, wherein, in a second view, the first feature is separated from the filler layer by the bonding dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: An electrical device is disposed on the same side as the optical surface of the substrate; as well as An interconnect structure is disposed between the substrate and the bonding structure and electrically coupled to the electrical device and the bonding structure, wherein the filler layer penetrates the interconnect structure.

3. The semiconductor structure according to claim 1, characterized in that, Also includes: A protective layer conformally covers the optical surface of the substrate to separate the filler layer from the optical surface of the substrate.

4. The semiconductor structure according to claim 1, characterized in that, In the first view, the first feature overlaps with the boundary of the filling layer.

5. The semiconductor structure according to claim 1, characterized in that, The first feature of the conductive feature is an electrically floating dummy pad.

6. The semiconductor structure according to claim 1, characterized in that, The highest point of the optical surface is between the highest point and the lowest point of the substrate.

7. The semiconductor structure according to claim 1, characterized in that, The optical surface described therein is a lens shape in the second view.

8. The semiconductor structure according to claim 1, characterized in that, The bonding surface of the bonding dielectric layer and the bonding surface of the conductive feature away from the substrate are substantially flush.

9. A semiconductor structure, characterized in that, include: The substrate includes a first side, a second side opposite to the first side, and a pattern on the first side, a portion of which serves as an optical component; A dielectric layer disposed on the first side of the substrate and including through holes corresponding to the pattern of the substrate; A filler layer is disposed in the through-holes of the dielectric layer and on the pattern of the substrate; as well as A first bonding structure is disposed on the dielectric layer and the filler layer. The first bonding structure includes a first bonding dielectric layer and a first conductive feature embedded in the first bonding dielectric layer. The first conductive feature is disposed on the dielectric layer and the filler layer and arranged outside the forbidden region. The optical component is disposed below the forbidden region. The first conductive feature includes a dummy feature that is isolated from the filler layer by the first bonding dielectric layer.

10. The semiconductor structure according to claim 9, characterized in that, The pattern of the substrate includes a protrusion having a convex surface and serving as a lens.

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