Power supply module easy for fully integrated voltage reduction

Abstract

The utility model relates to the technical field of power supply modules, and discloses a power supply module easy for fully integrated voltage reduction, which comprises a module voltage VOUT output node, a power supply (output) normal indication pin PGOOD which is an open leakage signal, if the output voltage is in a normal regulation range, a pull-up resistor (connected to a DC voltage) is needed to indicate a high level, and if the output voltage is not in a normal regulation range, the power supply (output) normal indication pin PGOOD is not in the normal regulation range, the power supply (output) normal indication pin PGOOD is not in the normal regulation range. When the Vo Sense + is greater than or equal to 92.5% until the PGOOD is pulled up, delay of about 1ms exists, and the input voltage pin VIN supplies power to the internal MOSFET and the regulator. The VIN needs an input capacitor to decouple an input power supply. Wide PCB (Printed Circuit Board) wiring connection is adopted, a system grounding pin PGND is a reference ground for adjusting output voltage, rapid load transient response can be realized by adopting a constant on-time (COT) control mode through a module, the design of loop stability is simplified, and a frequency hopping mode can be entered under light load so as to optimize efficiency.

Description

Technical Field

[0001] This utility model relates to the field of power module technology, and more specifically, to a power module that is easy to fully integrate and step down. Background Technology

[0002] A power supply module is a power supply that can be directly mounted on a printed circuit board. It is available in both buck and boost versions and can provide power to application-specific integrated circuits (ASICs), digital signal processors (DSPs), microprocessors, memory, field-programmable gate arrays (FPGAs), and other digital or analog loads. Existing DC / DC power supply modules are mostly single-function, so I propose an easy-to-use fully integrated buck DC / DC converter. Utility Model Content

[0003] To address the problems mentioned in the background section, this invention provides a power module that is easy to fully integrate and step down.

[0004] The present invention provides a power supply module that is easy to fully integrate and step down, using the following technical solution: A power supply module that is easy to fully integrate and step down, comprising:

[0005] Module voltage VOUT output node;

[0006] The power output normal indicator pin PGOOD is an open-drain signal. If the output voltage is within the normal adjustment range, a pull-up resistor is required to connect to the DC voltage to indicate a high level. There is approximately a 1ms delay from VoSense+ being greater than or equal to 92.5% until PGOOD is pulled high.

[0007] The input voltage pin VIN powers the internal MOSFET and regulator. VIN requires an input capacitor to decouple the input power supply. Use wide PCB traces for the connection.

[0008] The system ground pin PGND is the reference ground for adjusting the output voltage;

[0009] The output pin VCC powers the driver and control circuitry. The module integrates an LDO output capacitor, eliminating the need for additional external capacitors.

[0010] The switch output pin SW is copper-plated at the SW pin;

[0011] The bootstrap pin BST integrates a bootstrap capacitor.

[0012] Analog ground AGND serves as a reference point for the control circuit.

[0013] The current-limiting pin CS is connected to a resistor to ground to set the current-limiting jump point;

[0014] The external tracking voltage input pin TRK / REF outputs a voltage that tracks the TRK / REF input signal. A ceramic capacitor is used as close as possible to the TRK / REF pin to decouple TRK / REF.

[0015] Preferably, it also includes a working mode selection pin MODE, which can be programmed to select CCM, frequency hopping mode and working switching frequency.

[0016] Preferably, it also includes VoSense - without using remote sampling, directly connecting VoSense - to the negative voltage side of the capacitor sampling point;

[0017] Connect a resistor between VoSense+ and GND to set the output voltage.

[0018] Preferably, it also includes an enable pin EN. Under normal operation, the EN pin must not be floating. The EN pin can be enabled or disabled by an analog or digital control logic signal.

[0019] Preferably, the module has current sampling and overcurrent protection functions.

[0020] In summary, this utility model has the following beneficial technical effects:

[0021] 1. This utility model achieves rapid load transient response by adopting constant on-time (COT) control mode in the module, and simplifies the design of loop stability. Under light load, it will enter frequency hopping mode to optimize efficiency.

[0022] 2. The operating frequency of the module can be selected between 600kHz, 800kHz or 1000kHz, which helps to optimize efficiency and reduce output ripple.

[0023] 3. This utility model improves the reliability and safety of the system by providing overcurrent protection (OCP), overvoltage protection (OVP), undervoltage protection (UVP), and overtemperature protection (OTP) to the module. Attached Figure Description

[0024] Figure 1 This is the application circuit 12 in the embodiment of this utility model. Schematic diagram of 5V / 8A output structure;

[0025] Figure 2 This is the application circuit 12 in the embodiment of this utility model. 3.3V / 8A output structure schematic diagram;

[0026] Figure 3 This is the application circuit 12 in the embodiment of this utility model. Schematic diagram of 1.8V / 10A output structure;

[0027] Figure 4 This is the application circuit 12 in the embodiment of this utility model. Schematic diagram of 1.2V / 10A output structure;

[0028] Figure 5 This is the application circuit 12 in the embodiment of this utility model. Schematic diagram of 1V / 10A output structure;

[0029] Figure 6 This is a schematic diagram of COT control in an embodiment of this utility model;

[0030] Figure 7 This is a schematic diagram of PWM overload operation in an embodiment of this utility model;

[0031] Figure 8 This is a schematic diagram of the light-load frequency hopping mode in an embodiment of this utility model;

[0032] Figure 9 This is a schematic diagram of the PGOOD clamping voltage vs. pull-up current in an embodiment of this utility model. Detailed Implementation

[0033] The following is in conjunction with the appendix Figure 1-9 The present invention will be described in further detail below.

[0034] It should be noted that the accompanying drawings are schematic and not to scale. For clarity and convenience, the relative dimensions and proportions of the parts shown are exaggerated or reduced in size; all dimensions are merely illustrative and not limiting. Furthermore, the same reference numerals are used for the same structures, elements, or fittings appearing in more than two drawings to indicate similar features.

[0035] This utility model discloses an easy-to-use, fully integrated step-down DC / DC converter. (See also...) Figure 1-9 This is an easy-to-use, fully integrated step-down DC / DC converter. This module has a continuous current of 8A and a peak current of 10A, making it suitable for applications requiring higher current. It can output current over a wide input voltage range of 2.7V to 16V and has excellent load and line regulation.

[0036] The module uses a QFN-28 (7mm x 7mm x 4mm) package, which saves space.

[0037] This module includes:

[0038] Module voltage VOUT output node;

[0039] The power (output) normal indicator pin PGOOD is an open-drain signal. If the output voltage is within the normal adjustment range, a pull-up resistor (connected to the DC voltage) is required to indicate a high level.

[0040] PGOOD is also an open-drain MOSFET structure. PGOOD is connected to VCC or another voltage source (less than 3.6V) through a pull-up resistor (usually 10kΩ). When the input voltage is applied, the MOSFET turns on, so PGOOD is pulled to GND before TRK / REF is ready. After the VoSense+ voltage reaches 92.5% of the REF voltage, PGOOD is pulled high after a delay of 0.9ms.

[0041] When the VoSense+ voltage drops to 80% of the REF voltage or exceeds 116% of the normal REF voltage, PGOOD is locked at a low level, and PGOOD can only be pulled high after a new soft start.

[0042] If the input power supply cannot power the module, even if PGOOD is connected to an external DC source through a pull-up resistor, PGOOD will still be clamped at a low level; the relationship between PGOOD voltage and pull-up current (e.g.) Figure 9 );

[0043] The input voltage pin VIN powers the internal MOSFET and regulator. VIN requires an input capacitor to decouple the input power supply and is connected using wide PCB traces.

[0044] The system ground pin PGND is the reference ground for adjusting the output voltage;

[0045] The output pin VCC powers the driver and control circuitry. The module integrates an LDO output capacitor, eliminating the need for additional external capacitors.

[0046] The switch output pin SW has copper plating at it to improve the module's heat dissipation performance.

[0047] The bootstrap pin BST integrates a bootstrap capacitor.

[0048] Analog ground AGND serves as a reference point for the control circuit.

[0049] The current-limiting pin CS is connected to a resistor to ground to set the current-limiting jump point;

[0050] The external tracking voltage input pin TRK / REF tracks the output voltage of the TRK / REF input signal. A ceramic capacitor is used as close as possible to the TRK / REF pin to decouple TRK / REF. X7R or X5R ceramic capacitors are used because they have stable temperature. The capacitance value of this capacitor determines the soft-start time.

[0051] VoSense - without using remote sampling, directly connect VoSense to the negative voltage side of the capacitor sampling point;

[0052] Connect a resistor between VoSense+ and GND to set the output voltage;

[0053] The enable pin EN enables the module when it is high and disables it when it is low. Under normal operation, the EN pin must not be floating. The EN pin can be enabled or disabled by an analog or digital control logic signal.

[0054] The module provides a precise EN threshold, so the input voltage is programmed using a resistor divider between VIN and AGND when the module is enabled;

[0055] This is ideal for applications that do not have a dedicated EN control logic signal, and can prevent undervoltage lockout (UVLO) transitions during power-on and power-off.

[0056] The value of the resistor divider can be determined using the following formula:

[0057]

[0058] It is 1.22V;

[0059] Should choose and This is to ensure that the EN voltage does not exceed 36V when VIN reaches its maximum value;

[0060] EN can also be connected via a pull-up resistor ( Connect directly to VIN. The maximum current entering EN should be 50μA;

[0061] RUP can be calculated using the formula:

[0062]

[0063] When the EN disable module is used, the output voltage discharge mode is enabled, which causes both the HS-FET and LS-FET to be locked. At this time, the discharge MOSFET connected between SW and GND turns on, and the output voltage begins to discharge. The typical switching on impedance of this MOSFET is about 80Ω. Once the VoSense+ voltage drops to 10%*REF, the MOSFET turns off to discharge.

[0064] Through the above structural design, the module can actively discharge the output capacitor when the power is off, ensuring safety;

[0065] When the LS-FET detects a current of -9A (typical), the module will turn off the LS-FET for 200ns to limit the negative current.

[0066] The operating mode selection pin MODE allows you to select CCM, frequency hopping mode, and operating switching frequency by programming the MODE pin.

[0067] The module features current sampling and overcurrent protection (OCP), with on-chip current sampling and a programmable positive current limit threshold.

[0068] When the module is powered on, current limiting is effective. During the LS-FET's conduction period, the SW current (inductor current) is sampled and... The ratio is mirrored to CS by using the resistance between CS and AGND ( ), The voltage and SW current are proportional cycle by cycle, only when... Voltage below the internal overcurrent protection (OCP) voltage threshold ( When the LS-FE is on, the HS-FET can be turned on to limit the valley current of SW cycle by cycle. The module integrates a 10kΩ resistor to GND.

[0069] Calculate the RCS current limiting threshold setting:

[0070]

[0071] It is 1.2V. 20µA / A, where ILIM is the desired output current limit (A);

[0072] After enabling, OCP hiccup protection is activated for 3ms. Once OCP hiccup is activated, if the module detects an overcurrent condition for 31 consecutive cycles or the VoSense+ is below the undervoltage protection (UVP) threshold, the device enters hiccup mode. Once in hiccup protection mode, the module immediately locks the HS-FET and locks the LS-FET after detecting zero current (ZCD). At the same time, the TRK / REF capacitor also begins to discharge. After about 11ms, the module attempts to automatically soft-start. If an overcurrent condition still exists after 3ms, the module will repeat this cycle until the overcurrent condition disappears and the output voltage stabilizes and rises back to the regulation level.

[0073] The module uses Output Suck Mode (OSM) to regulate the output voltage. When the VoSense+ voltage is higher than 104%*REF but lower than the OVP threshold, OSM is triggered. During OSM, the LS-FET remains on until the negative current limit of -5.5A is reached. Then, the LS-FET is immediately turned off (200ns) and then turned on again. The module repeats this operation until VoSense+ drops below 102%*REF. The module then exits OSM after 15 consecutive CCM cycles.

[0074] The module monitors the output voltage by connecting VoSense+ to the junction of the output voltage feedback resistor divider, thereby detecting overvoltage conditions. It provides an overvoltage protection (OVP) mode with hiccup protection.

[0075] If the VoSense+ voltage exceeds 116% of the REF voltage, OVP will be triggered. PGOOD will be pulled low until it reaches the negative current limit value (NOCP) of the lower transistor. Then, the LS-FET will be turned off immediately for 200ns. During this period, the HS-FET will be turned on. After 200ns, the LS-FET will be turned on again. The module repeats this operation until the overvoltage on the discharge output is reached. When the feedback voltage drops below 105%*REF, the module exits the OVP discharge mode, thus achieving overvoltage protection (OVP) for the module.

[0076] The module has an over-temperature protection (OTP) function, which can monitor the junction temperature internally. If the junction temperature exceeds the threshold (usually 160°C), the converter shuts down and discharges the TRK / REF capacitor. This over-temperature protection is not a lockout protection mode and has a thermal hysteresis of about 30°C. Once the junction temperature drops to about 130°C, soft start is enabled, realizing the over-temperature protection function of the module.

[0077] The module provides an analog input pin (TRK / REF) to track another power / receive external reference. When an external voltage signal is connected to TRK / REF, it will serve as a reference for the module's output voltage. The VoSense+ voltage will completely follow this external voltage signal and will ignore soft-start settings. The TRK / REF input signal range is 0.3V to 1.4V. During initial startup, TRK / REF must first reach 600mV or higher to ensure proper chip operation. After that, it can be any value between 0.3V and 1.4V.

[0078] The test conditions are VIN=12V, VOUT=1.2V, TJ=-55°C to 125°C, and the typical numerical test conditions are TJ=25°C.

[0079]

[0080] The module connects a 100nF internal capacitor between TRK / REF and VoSense- via soft-start (SS) to limit the soft-start time to a minimum of 1.6ms. An external soft-start (SS) capacitor can be added between the TRK / REF and VoSense- pins to increase this time value.

[0081] The total SS capacitance value can be determined using the following formula:

[0082]

[0083] With the above structural design, the module has an internal soft-start time of approximately 1.6ms, which can be adjusted by an external soft-start capacitor, helping to control the surge current during the startup process.

[0084] The module enables monotonic linear startup under pre-biased load conditions through its output pre-biased voltage startup function. If a fixed pre-biased voltage is applied at startup, the IC will disable the switching of the HS-FET and LS-FET until the voltage on the TRK / REF capacitor exceeds the VoSense+ sampling output voltage value. Before the TRK / REF voltage reaches the pre-biased VoSense+ value, if the BST voltage (between the BST and SW pins) is below 2.3V, the LS-FET will turn on to allow VCC to charge to BST. Since the LS-FET only conducts for very narrow pulses, the drop in pre-bias is negligible.

[0085] (Reference Figure 6 The module employs a constant on-time (COT) control mode to achieve rapid load transient response;

[0086] The operational amplifier (AMP) can correct the erroneous voltage between VoSense+ and VREF. Thanks to the AMP's correction capability, it can provide excellent load regulation across the entire load range, whether the module is in forced continuous conduction mode (FCCM) or frequency hopping mode. The dedicated VoSense- pin helps to provide feedback to the remote GND sampling.

[0087] The module employs internal ramp compensation to provide a low ESRMLCC output capacitance solution by using an optimized adaptive internal ramp and appropriate output L / C filtering design.

[0088] When the LS-FET detects a current of -9A (typical), the module will turn off the LS-FET for 200ns to limit the negative current. The module achieves stable operation across the entire input and output voltage range.

[0089] Pulse Width Modulation (PWM) Operating Mode

[0090] Reference Figure 7 The diagram shows the generation of pulse width modulation (PWM). An AMP is used to correct erroneous voltages between VoSense+ and REF, generating a relatively stable DC voltage (COMP). An internal ramp is superimposed on COMP, and the superimposed COMP is compared with the VoSense+ signal. Whenever VoSense+ drops below the superimposed COMP, the integrated upper MOSFET (HSFET) turns on. The HSFET remains on for a fixed time, determined by the input voltage, output voltage, and selected switching frequency. After the on-cycle ends, the HSFET turns off and turns on again when VoSense+ drops below the superimposed COMP value. The module regulates the output voltage by repeating this operation. The integrated lower MOSFET (LSFET) only turns on when the HSFET is off, minimizing conduction losses. If both the HSFET and LSFET are on simultaneously, a short circuit will form between VIN and PGND, a situation known as shoot-through. To avoid shoot-through, an internal dead time is generated during the period when the HSFET is off and the LSFET is on, or vice versa.

[0091] When the output current is high and the inductor current is always higher than zero AMP, it enters CCM mode. When the output current is low, the module can also be configured to force continuous conduction mode (CCM mode). In continuous conduction mode (CCM mode), the switching frequency is quite constant (PWM mode), so the output ripple can remain constant almost throughout the full load range.

[0092] Under light load, it will enter frequency hopping mode to optimize efficiency. When the load decreases, the inductor current will also decrease. Once the inductor current is zero, the module will switch from CCM mode to frequency hopping mode.

[0093] Referring to Figure 8, which is a schematic diagram of the light-load frequency hopping operation mode, when VoSense+ drops below the superimposed COMP value, the HS-FET will turn on at fixed intervals. When the HS-FET turns off, the LS-FET turns on until the current is zero. In frequency hopping mode, when the inductor current is zero, VoSense+ cannot reach the superimposed COMP current value. When the inductor current is zero, the LS-FET is driven into a tri-state (Hi-Z). The current modulator controls the LS-FET and limits the inductor current to below -1mA. Therefore, the output capacitor can slowly discharge to PGND through the LS-FET. Under light load, the HS-FET will not turn on as frequently in frequency hopping mode as it does in forced CCM mode. This makes the efficiency of frequency hopping mode much higher than that of forced CCM mode.

[0094] As the output current under light load continues to increase, the adjustment cycle of the current modulator will become shorter and shorter, and the HS-FET will be turned on more frequently. Therefore, the switching frequency will also increase accordingly. When the current modulation time is zero, the output current reaches the critical value.

[0095] The critical value of the output current can be determined using the formula:

[0096]

[0097] Where is the switching frequency, and L is the internal integrated inductor (typically 0.68μH).

[0098] When the output current exceeds the critical value, the module enters PWM mode, and thereafter the switching frequency remains relatively constant within the output current range.

[0099] The module can even be configured to forced CCM mode under light load conditions;

[0100] The mode selection module can provide both forced CCM mode and frequency hopping mode under light load conditions. The module has three switching frequency options (600kHz, 800kHz, and 1000kHz). The operating mode and switching frequency under light load are selected by choosing the resistance value between the MODE and AGND / VCC pins, as shown in the table below.

[0101]

[0102] Through the above structural design, the module can be selected between 600kHz, 800kHz or 1000kHz, which helps to optimize efficiency and reduce output ripple;

[0103] The module provides an analog input pin (TRK / REF) to track another power / receive external reference. When an external voltage signal is connected to TRK / REF, it will serve as a reference for the module's output voltage. The VoSense+ voltage will completely follow this external voltage signal and will ignore soft-start settings. The TRK / REF input signal range is 0.3V to 1.4V. During initial startup, TRK / REF must first reach 600mV or higher to ensure proper chip operation. After that, it can be any value between 0.3V and 1.4V.

[0104] Through the above structural design, this control mode provides a fast transient response and simplifies the design of loop stability.

[0105] Finally, the following points should be noted: First, in the description of this utility model, it should be noted that, unless otherwise specified and limited, the terms "installation", "connection" and "connection" should be interpreted broadly, and can be mechanical connection or electrical connection, or internal connection between two components, or direct connection. "Up", "down", "left", "right", etc. are only used to indicate relative positional relationship. When the absolute position of the described object changes, the relative positional relationship may change.

[0106] Secondly: The accompanying drawings of the embodiments disclosed in this utility model only involve the structures involved in the embodiments disclosed in this utility model. Other structures can refer to the general design. In the absence of conflict, the same embodiment and different embodiments of this utility model can be combined with each other.

[0107] Finally: The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A power supply module that is easy to fully integrate and step down, characterized in that, include: Module voltage VOUT output node; The power output normal indicator pin PGOOD is an open-drain signal. If the output voltage is within the normal adjustment range, a pull-up resistor is required to connect to the DC voltage to indicate a high level. There is approximately a 1ms delay from VoSense+ being greater than or equal to 92.5% until PGOOD is pulled high. The input voltage pin VIN powers the internal MOSFET and regulator. VIN requires an input capacitor to decouple the input power supply and is connected using wide PCB traces. The system ground pin PGND is the reference ground for adjusting the output voltage; The output pin VCC powers the driver and control circuitry. The module integrates an LDO output capacitor, eliminating the need for additional external capacitors. The switch output pin SW is copper-plated at the SW pin; The bootstrap pin BST integrates a bootstrap capacitor. Analog ground AGND serves as a reference point for the control circuit. The current-limiting pin CS is connected to a resistor to ground to set the current-limiting jump point; The external tracking voltage input pin TRK / REF outputs a voltage that tracks the TRK / REF input signal. A ceramic capacitor is used as close as possible to the TRK / REF pin to decouple TRK / REF.

2. The power supply module for easy full integration and voltage reduction according to claim 1, characterized in that: It also includes a MODE pin for selecting the operating mode, which can be programmed to select CCM, frequency hopping mode, and operating switching frequency.

3. The power supply module for easy full integration and step-down as described in claim 2, characterized in that: It also includes VoSense - which does not use remote sampling and directly connects VoSense to the negative voltage side of the capacitor sampling point; Connect a resistor between VoSense+ and GND to set the output voltage.

4. The power supply module for easy full integration and step-down as described in claim 1, characterized in that: It also includes the enable pin EN. Under normal operation, the EN pin must not be floating. The EN pin can be enabled or disabled by an analog or digital control logic signal.

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