Instant acceleration type high-voltage driving circuit

Abstract

The utility model discloses an instant acceleration type high-voltage driving circuit, which belongs to the technical field of driving circuits and comprises a capacitive coupling acceleration module, the input end of the capacitive coupling acceleration module is electrically connected with a low-voltage power rail VDD2, and the output end of the capacitive coupling acceleration module is coupled with a current bias mirror image module. The output end of the current bias mirror image module is coupled with a voltage clamping circuit and a driving stage circuit, the capacitance coupling acceleration module comprises a low-voltage NMOS NM1, a low-voltage NMOS NM1 S electrode electrically connected with a low-voltage NMOS NM3 S electrode, one end of a capacitor C2, a low-voltage NMOS NM4 S electrode, a low-voltage NMOS NM1 D electrode electrically connected with a low-voltage NMOS NM2 S electrode, one end of a capacitor C1, a low-voltage NMOS NM3 D electrode, the other end of the capacitor C1 and a low-voltage NMOS NM4 G electrode.

Description

TECHNICAL FIELD

[0001] The utility model relates to a drive circuit especially to a momentary acceleration formula high voltage drive circuit belongs to drive circuit technical field. BACKGROUND

[0002] In the FLYBACK architecture of ACDC, the power tube samples thick gate oxide MOS, the conventional drive voltage is about 12V, the control chip adopts the auxiliary winding power supply, generates the high voltage power rail about 15V~30V, so needs to convert the power supply voltage to 12V around drive power tube. The conventional design needs to design a high voltage LDO output 12V power supply, then adopts multistage high voltage drive circuit output final drive signal, to guarantee the drive speed, the transient response speed and current capacity of LDO are higher, and the size of the last stage drive circuit is also larger, and the cost is also higher, therefore designs a momentary acceleration formula high voltage drive circuit to solve above -mentioned problem. UTILITY MODEL CONTENTS

[0003] The main purpose of the utility model is to provide a momentary acceleration formula high voltage drive circuit.

[0004] The purpose of the utility model can be achieved by adopting the following technical scheme:

[0005] A momentary acceleration formula high voltage drive circuit, including the capacitor coupling acceleration module, the input end electric connection low voltage power rail VDD2 of capacitor coupling acceleration module;

[0006] The output end of capacitor coupling acceleration module is coupled current bias mirror image module, and the output end of current bias mirror image module is coupled voltage clamping circuit and drive stage circuit.

[0007] Preferably, the capacitor coupling acceleration module includes the S pole electric connection of low voltage NMOS NM1 S pole, one end of capacitor C2, low voltage NMOS NM4 S pole of low voltage NMOS NM3;

[0008] The D pole of low voltage NMOS NM1 is electrically connected with the S pole of low voltage NMOS NM2, one end of capacitor C1, the D pole of low voltage NMOS NM3, the other end of capacitor C1 and the G pole of low voltage NMOS NM4.

[0009] Preferably, the G pole of low voltage NMOS NM1 is electrically connected with the G pole of low voltage NMOS NM2, the G pole of low voltage NMOS PM1 and drive stage circuit;

[0010] The D pole of low voltage NMOS NM2 is electrically connected with the other end of capacitor C1 and the S pole of low voltage NMOS PM1;

[0011] The D terminal of the low-voltage NMOS PM1 is electrically connected with a low-voltage power supply rail VDD2 and a current bias mirror module.

[0012] Preferably, the current bias mirror module comprises a high-voltage PMOS HVPM1, the S terminal of the high-voltage PMOS HVPM1 is electrically connected with a high-voltage power supply rail VDD1, the S terminal of a high-voltage PMOS HVPM2 and a driving stage circuit;

[0013] The D terminal of the high-voltage PMOS HVPM1 is electrically connected with the D terminal of a high-voltage NMOS HVNM1, the S terminal of the high-voltage NMOS HVNM1 is electrically connected with the D terminal of a low-voltage NMOS NM4 and one end of a current meter, and the other end of the current meter is grounded.

[0014] Preferably, the D terminal of the high-voltage PMOS HVPM2 is electrically connected with a voltage clamping circuit and the driving stage circuit, and the other end of the current meter is electrically connected with the voltage clamping circuit and the driving stage circuit.

[0015] Preferably, the driving stage circuit comprises a high-voltage NMOS HVNM2, the D terminal of the high-voltage NMOS HVNM2 is electrically connected with the S terminal of the high-voltage PMOS HVPM2, the S terminal of the high-voltage NMOS HVNM2 is electrically connected with the D terminal of a high-voltage NMOS HVNM3, and the S terminal of the high-voltage NMOS HVNM3 is electrically connected with the other end of the current meter.

[0016] Preferably, the S terminal of a high-voltage NMOS HVNM4 is electrically connected with the other end of the current meter and the voltage clamping circuit, and the D terminal of the high-voltage NMOS HVNM4 is electrically connected with the D terminal of the high-voltage PMOS HVPM2.

[0017] The G terminal of the high-voltage NMOS HVNM4 and the G terminal of the high-voltage NMOS HVNM3 are electrically connected with the G terminal of the low-voltage NMOS NM1.

[0018] The utility model discloses a beneficial technical effect:

[0019] The utility model discloses a kind of instantaneous acceleration formula high-voltage drive circuit, simple structure, lower cost, by adjusting capacitor coupling acceleration module can adjust drive rising speed, lower cost can meet different drive speed requirement. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 It is the circuit diagram according to a preferred embodiment of a kind of instantaneous acceleration formula high-voltage drive circuit of the utility model.

[0021] Figure 2 It is the driving current with time relationship schematic diagram according to a preferred embodiment of a kind of instantaneous acceleration formula high-voltage drive circuit of the utility model.

[0022] In the figure: 1-capacitance coupling acceleration module; 2-current bias mirror module; 3-voltage clamping circuit; 4-driving stage circuit. DETAILED DESCRIPTION

[0023] In order to make the skilled in the art more clear and clear the technical scheme of the utility model, the utility model is described in further detail below in combination with examples and drawings, but the implementation of the utility model is not limited to this.

[0024] Voltage clamping: the characteristics of stabilizing tube and other elements or the structure of operational amplifier are used to realize the clamping of node voltage, and the upper clamping limits the upper limit of node voltage, and the lower clamping limits the lower limit of node voltage.

[0025] High-voltage drive: some power tubes in switching power supply need a larger driving voltage, for example, the high-voltage power tube in ACDC, the gate oxide withstand voltage is as high as 30V, the gate oxide capacitor is in the nF level, and the normal driving voltage is about 12V.

[0026] Level converter: a level converter is needed for level conversion when a logic signal is transmitted between different power supply levels, such as low-voltage to high-voltage or high-voltage to low-voltage.

[0027] Reference Figure 2 The high-voltage drive circuit designed in the utility model comprises a capacitance coupling acceleration module 1, a current bias mirror module 2, a voltage clamping circuit 3 and a driving stage circuit 4. A low-voltage power supply rail VDD2 supplies power to the capacitance acceleration module 1 and the driving logic, and simultaneously provides a gate bias for the high-voltage isolation N tube HVNM1. The current bias module 2 mirrors the static bias current I0 and the transient bias current generated by NM4, generates a driving current to drive the gate of HVNM2, and controls the pull-up opening of HVNM2. The voltage clamping circuit module 3 realizes the upper clamping of the gate voltage of HVNM2 and limits the driving output voltage. The driving stage circuit cooperates with the clamping circuit to realize the conversion of the high-voltage power supply rail VDD1 into a suitable driving output, and HVNM4 controls the pull-down closing of HVNM2.

[0028] The circuit of the utility model comprises low-voltage NMOS NM1, NM2, NM3 and NM4, low-voltage PMOS PM1, high-voltage NMOS HVNM1, HVNM2, HVNM3 and HVNM4, high-voltage PMOS HVPM1 and HVPM2, capacitors C1 and C2, and a current source I0. In the normal working process, when the driving logic is high, HVNM3 and HVNM4 are closed, HVPM2 mirrors the current of HVPM1 to generate a driving current to raise the gate voltage of HVNM2, the upper clamping voltage of the clamping module 3 is set as V CLAMP , and the highest rising voltage of HVNM2 is V CLAMP , and the driving output voltage is:

[0029] VDRIVE = V CLAMP -V GS-HVNM2

[0030] The appropriate driving voltage output can be selected by adjusting the clamping circuit. When the driving logic is low, HVNM4 is turned on to pull down the HVNM2 gate, HVNM2 is turned off, and HVNM3 is turned on to pull the driving output to 0. The power tube of the later-stage driving has a large gate oxide capacitor, and in order to ensure the opening speed of the power tube, the gate voltage of HVNM2 needs to have a suitable rising time when it is turned on. The speed can be controlled by controlling the driving current, and in the case where the capacitor coupling acceleration module 1 is not added, the static bias current I0 determines the driving current, and adjusting the I0 current value can meet the driving speed requirements. In the case where the driving speed has a high requirement, a larger I0 means a larger static power consumption. In the circuit, the capacitor coupling acceleration module 1 is added, when the driving logic is low, NM1 and NM2 are turned on, PM1 is turned off, and there is no charge on the capacitor C1. When the driving logic is flipped from low to high, NM1 and NM2 are turned off, PM1 is turned on, and the capacitor C1 is coupled to the voltage on the NM3 and NM4 gates from the low-voltage power supply rail VDD2. Thus, a large instantaneous current can be generated on NM4, and the driving speed is instantaneously improved. Moreover, in this design, only a large driving current is generated at the moment of flipping, and then the charge on NM3 and NM4 is discharged to the ground through NM3, and when the gate voltage drops below the threshold voltage, the driving current will be reduced to the normal bias current I0. Reference Figure 2 describes the driving current variation diagram during the driving flip process, so this design greatly reduces the static power consumption while meeting the driving speed. By adding the capacitor C2, the length of the ΔTd period in Figure 2 can be extended, and the rising slope of the driving voltage near the peak value can be improved, but the design needs to meet C1>>C2, and the driving current peak I D-peak .

[0031] The above is only a further embodiment of the present application, but the protection scope of the present application is not limited thereto. Any skilled person in the art can make equivalent replacement or change according to the technical scheme and concept of the present application within the scope disclosed by the present application, and it belongs to the protection scope of the present application.

Claims

1. A high voltage drive circuit for instantaneously accelerating, characterized by: The capacitor coupling acceleration module (1) includes a low-voltage power supply rail VDD2 electrically connected to the input end of the capacitor coupling acceleration module (1); The output end of the capacitor coupling acceleration module (1) is coupled to the current bias mirror module (2), and the output end of the current bias mirror module (2) is coupled to the voltage clamping circuit (3) and the driving stage circuit (4).

2. The high voltage drive circuit according to claim 1, wherein: The capacitor coupling acceleration module (1) includes a low-voltage NMOS NM1, the S pole of which is electrically connected to the S pole of a low-voltage NMOS NM3, one end of a capacitor C2, and the S pole of a low-voltage NMOS NM4. The D pole of the low-voltage NMOS NM1 is electrically connected to the S pole of a low-voltage NMOS NM2, one end of a capacitor C1, the D pole of a low-voltage NMOS NM3, the other end of the capacitor C1, and the G pole of a low-voltage NMOS NM4.

3. The high voltage drive circuit according to claim 2, wherein: The G pole of the low-voltage NMOS NM1 is electrically connected to the G pole of the low-voltage NMOS NM2, the G pole of a low-voltage NMOS PM1, and the driving stage circuit (4). The D pole of the low-voltage NMOS PM1 is electrically connected to the low-voltage power supply rail VDD2 and the current bias mirror module (2). The current bias mirror module (2) includes a high-voltage PMOS HVPM1, the S pole of which is electrically connected to a high-voltage power supply rail VDD1, the S pole of a high-voltage PMOS HVPM2, and the driving stage circuit (4).

4. The high voltage drive circuit according to claim 3, wherein: The D pole of the high-voltage PMOS HVPM1 is electrically connected to the D pole of a high-voltage NMOS HVNM1, the S pole of the high-voltage NMOS HVNM1 is electrically connected to the D pole of the low-voltage NMOS NM4 and one end of an ammeter, and the other end of the ammeter is grounded. The D pole of the high-voltage PMOS HVPM2 is electrically connected to the voltage clamping circuit (3) and the driving stage circuit (4), and the other end of the ammeter is electrically connected to the voltage clamping circuit (3) and the driving stage circuit (4).

5. The high voltage drive circuit according to claim 4, wherein: The driving stage circuit (4) includes a high-voltage NMOS HVNM2, the D pole of which is electrically connected to the S pole of the high-voltage PMOS HVPM2, the S pole of the high-voltage NMOS HVNM2 is electrically connected to the D pole of a high-voltage NMOS HVNM3, and the S pole of the high-voltage NMOS HVNM3 is electrically connected to the other end of the ammeter.

6. The high voltage drive circuit according to claim 5, wherein: The S pole of a high-voltage NMOS HVNM4 is electrically connected to the other end of the ammeter and the voltage clamping circuit (3), and the D pole of the high-voltage NMOS HVNM4 is electrically connected to the D pole of the high-voltage PMOS HVPM2.

7. The high voltage drive circuit according to claim 6, wherein: The G poles of the high-voltage NMOS HVNM4 and the high-voltage NMOS HVNM3 are electrically connected to the G pole of the low-voltage NMOS NM1. ​

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