Edge-triggered monopulse circuit, system and device

By designing an edge-triggered single-pulse circuit, and utilizing MOSFETs, resistors, capacitors, and diodes, the problem of high cost due to circuit complexity in existing technologies is solved, enabling low-cost generation of high and low level pulse signals, which is suitable for consumer electronics products.

CN223584155UActive Publication Date: 2025-11-21JWIPC TECH CO LTD
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Patent Information

Application Number
CN202520260520.X
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2025-02-18
Publication Date
2025-11-21
Estimated Expiration
2035-02-18

AI Technical Summary

Technical Problem

The circuit designs used to generate high and low level pulses in the existing technology are complex, resulting in high development and production costs, and are not suitable for widespread application in consumer electronics products.

Method used

An edge-triggered single-pulse circuit design is adopted, which uses several MOSFETs, resistors, capacitors and diodes to build a low-cost edge-triggered single-pulse circuit to generate a simple power-on signal or secondary reset signal.

Benefits of technology

It enables low-cost generation of high and low level pulse signals, simplifies circuit design, reduces development and production costs, and is suitable for consumer electronics products.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model relates to an edge-triggered monopulse circuit, system and device. The circuit comprises a first resistor, a second resistor, a third resistor, a capacitor, a diode, a first MOS tube and a second MOS tube. One end of the first resistor is connected to a control signal input end, the other end of the first resistor is connected with a grid electrode of the first MOS tube, a drain electrode of the first MOS tube is connected with one end of the second resistor and one end of the third resistor, and the other end of the second resistor is connected to a first continuous power supply end; the other end of the third resistor is connected with one end of a capacitor, the other end of the capacitor is connected with the positive electrode of a diode, the negative electrode of the diode is connected with the grid electrode of a second MOS tube, and the drain electrode of the second MOS tube is connected to the low-pulse output end; source electrodes of the first MOS tube and the second MOS tube are grounded; the circuit is simple in design, low in development and manufacturing cost, capable of achieving effective signal control while meeting the function of generating low pulses, and beneficial to application and popularization.
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Description

TECHNICAL FIELD

[0001] The utility model relates to electronic circuit technical field more specifically, relate to a kind of edge trigger single pulse circuit, system and device. BACKGROUND

[0002] In the consumer electronics product circuit without MCU / EC, sometimes need to build a rising edge or falling edge circuit by hardware to generate a high-low level pulse, for the secondary reset of a certain functional chip, so that the chip can reset and restart to recover normal after failure. For example, after general system startup, CPU can send a high-low level pulse to reset functional chip by GPIO, but when the system is in hibernation state, CPU cannot operate GPIO, so it cannot generate such a secondary reset signal, so it is usually necessary to build a rising edge or falling edge circuit by hardware to generate a high-low level pulse, so as to realize the operation of secondary reset. However, the circuit design for realizing pulse trigger adopted in the prior art is often relatively complex, resulting in high cost of development and production and manufacture, which is not conducive to popularization and application. SUMMARY

[0003] The technical problem to be solved by the utility model is to provide an edge trigger single pulse circuit, system and device in view of the above defects of the prior art.

[0004] The technical scheme adopted by the utility model to solve its technical problem is:

[0005] On the one hand, the utility model provides an edge trigger single pulse circuit, which comprises a first resistor, a second resistor, a third resistor, a capacitor, a diode, a first MOS tube and a second MOS tube; one end of the first resistor is connected to a control signal input end, the other end of the first resistor is connected to the gate of the first MOS tube, the drain of the first MOS tube is connected to one end of the second resistor and the third resistor respectively, the other end of the second resistor is connected to a first continuous power supply end; the other end of the third resistor is connected to one end of the capacitor, the other end of the capacitor is connected to the positive electrode of the diode, the negative electrode of the diode is connected to the gate of the second MOS tube, the drain of the second MOS tube is connected to a low pulse output end; the source of the first MOS tube and the second MOS tube is grounded.

[0006] In some embodiments, the circuit further comprises a fourth resistor, one end of the fourth resistor is connected between the first resistor and the gate of the first MOS tube, the other end of the fourth resistor is connected between the third resistor and the capacitor.

[0007] In some embodiments, the circuit further comprises a fifth resistor, one end of the fifth resistor is connected between the capacitor and the positive electrode of the diode, the other end of the fifth resistor is grounded.

[0008] In some embodiments, the circuit further comprises a sixth resistor, one end of the sixth resistor is connected between the drain of the second MOS tube and the low pulse output end, and the other end of the sixth resistor is connected to the second continuous power supply end.

[0009] In some embodiments, the first MOS tube is provided with a first parasitic diode, a positive electrode of the first parasitic diode is connected to a source electrode of the first MOS tube, and a negative electrode of the first parasitic diode is connected to a drain electrode of the first MOS tube.

[0010] In some embodiments, the second MOS tube is provided with a second parasitic diode, a positive electrode of the second parasitic diode is connected to a source electrode of the second MOS tube, and a negative electrode of the second parasitic diode is connected to a drain electrode of the second MOS tube.

[0011] In some embodiments, the power supply voltage of the first continuous power supply end is 3.3V.

[0012] In some embodiments, the power supply voltage of the second continuous power supply end is 2.2V.

[0013] In another aspect, the utility model also provides a kind of edge trigger single pulse system, including the edge trigger single pulse circuit as any one of the above.

[0014] In another aspect, the utility model also provides a kind of edge trigger single pulse device, including the edge trigger single pulse system as described above.

[0015] The utility model has the advantages that, different from prior art, the edge trigger single pulse circuit of the utility model is designed by using a plurality of MOS tubes, resistors, capacitors and diodes to produce a low-cost, low-pulse edge trigger single pulse circuit, which can be used to generate a simple trigger power-on signal or a secondary reset signal, and is applied in consumer electronics products, with low development and production costs, effectively controls signals while meeting the low-pulse function, and is conducive to promotion and application. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is the schematic diagram of the edge trigger single pulse circuit in the embodiment of the utility model;

[0017] Figure 2 is the corresponding pulse schematic diagram of A, B, C and D in the embodiment of the utility model. DETAILED DESCRIPTION

[0018] The terms "first", "second", "third", and "fourth" and the like in the description and claims of the present document are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprising", "including", "containing", and "having" and their conjugates, as used herein, are inclusive and are intended to permit the inclusion of the listed elements, as well as additional elements, without precluding other elements. For example, processes, methods, articles, or apparatuses that "comprise", "include", "contain", or "have" a series of steps or units are not limited to only those steps or units that are listed, but can also optionally include additional steps or units that are not listed.

[0019] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same embodiment, or to a single alternative embodiment. It is explicitly contemplated that embodiments described herein can be combined with each other.

[0020] "Multiple" means two or more. "And / or", describing the relationship between the associated objects, means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. The character " / " generally represents that the associated objects before and after are a "or" relationship.

[0021] Furthermore, the terms "upper", "lower", "front", "back", "left", "right", "upper end", "lower end", and the like indicating the orientation are all based on the attitude position of the device or equipment described in the present application during normal use.

[0022] In order to make the purposes, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be described clearly and completely below. Obviously, the described embodiments are part of the embodiments of the present application, not all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0023] Embodiment one: the embodiment of the present application provides a kind of edge trigger single pulse circuit, such as Figure 1As shown in the figure, the edge-triggered single-pulse circuit includes a first resistor R235, a second resistor R233, a third resistor R234, a capacitor C62, a diode D36, a first MOS Q81 and a second MOS Q80; one end of the first resistor R235 is connected to a control signal input end, the other end of the first resistor R235 is connected to a gate of the first MOS Q81, a drain of the first MOS Q81 is connected to one end of the second resistor R233 and one end of the third resistor R234 respectively, the other end of the second resistor R233 is connected to a first continuous power supply end; the other end of the third resistor R234 is connected to one end of the capacitor C62, the other end of the capacitor C62 is connected to a positive electrode of the diode D36, a negative electrode of the diode D36 is connected to a gate of the second MOS Q80, a drain of the second MOS Q80 is connected to a low pulse output end; the source of the first MOS Q81 and the source of the second MOS Q80 are both grounded.

[0024] Further, in the embodiment, the edge-triggered single-pulse circuit further includes a fourth resistor R236, a fifth resistor R231 and a sixth resistor R232; one end of the fourth resistor R236 is connected between the first resistor R235 and the gate of the first MOS Q81, the other end of the fourth resistor R236 is connected between the third resistor R234 and the capacitor C62; one end of the fifth resistor R231 is connected between the capacitor C62 and the positive electrode of the diode D36, the other end of the fifth resistor R231 is grounded; one end of the sixth resistor R232 is connected between the drain of the second MOS Q80 and the low pulse output end, the other end of the sixth resistor R232 is connected to a second continuous power supply end; the power supply voltage of the first continuous power supply end is 3.3V, and the power supply voltage of the second continuous power supply end is 2.2V.

[0025] Further, in the embodiment, the first MOS Q81 is provided with a first parasitic diode, a positive electrode of the first parasitic diode is connected to the source of the first MOS Q81, and a negative electrode of the first parasitic diode is connected to the drain of the first MOS Q81; the second MOS Q80 is provided with a second parasitic diode, a positive electrode of the second parasitic diode is connected to the source of the second MOS Q80, and a negative electrode of the second parasitic diode is connected to the drain of the second MOS Q80.

[0026] It should be noted that if the absolute value of Vgs of the second MOS Q80 can cover the corresponding negative voltage pulse, the diode D36 can be short-circuited.

[0027] The embodiment of the utility model discloses a low-cost edge-triggered single-pulse circuit for generating low pulse by adopting a plurality of MOS, resistor, capacitor and diode, which can be used to generate simple trigger power-on signal or secondary reset signal. Figure 1As shown, a rising edge is inputted at the control signal input end of A, which can be the first reset signal Reset# and is pulled high; if the fourth resistor R236 is not connected, a falling edge can be inputted at the control signal input end of A, a rising edge is obtained through the non-inverter composed of the first MOS Q81, and finally a low pulse output from D is obtained. Figure 1 The corresponding pulse diagrams at A, B, C and D are shown in the accompanying drawings. Figure 2 .

[0028] Embodiment two: the utility model embodiment further provides a kind of edge trigger single pulse system, and the edge trigger single pulse system includes the edge trigger single pulse circuit provided in embodiment one.Therein, see embodiment one regarding the description of edge trigger single pulse circuit, this embodiment will not be repeated.

[0029] Embodiment three: the utility model embodiment further provides a kind of edge trigger single pulse device, and the edge trigger single pulse device includes the edge trigger single pulse system provided in embodiment two, and the edge trigger single pulse system includes the edge trigger single pulse circuit provided in embodiment one.Therein, see embodiment one regarding the description of edge trigger single pulse circuit, this embodiment will not be repeated.

[0030] It should be understood that, for those of ordinary skill in the art, improvements or changes can be made according to the above description, and all such improvements and changes shall fall within the scope of protection of the appended claims of the utility model.

Claims

1. An edge triggered one-shot circuit, characterized by: The circuit comprises a first resistor, a second resistor, a third resistor, a capacitor, a diode, a first MOS tube and a second MOS tube; one end of the first resistor is connected to a control signal input end, the other end of the first resistor is connected to a gate of the first MOS tube, a drain of the first MOS tube is connected to one end of the second resistor and one end of the third resistor respectively, the other end of the second resistor is connected to a first continuous power supply end; the other end of the third resistor is connected to one end of the capacitor, the other end of the capacitor is connected to a positive electrode of the diode, a negative electrode of the diode is connected to a gate of the second MOS tube, a drain of the second MOS tube is connected to a low pulse output end; the source of the first MOS tube and the source of the second MOS tube are both grounded.

2. The edge triggered one-shot circuit of claim 1, wherein: The circuit further comprises a fourth resistor, one end of the fourth resistor is connected between the first resistor and the gate of the first MOS tube, the other end of the fourth resistor is connected between the third resistor and the capacitor.

3. The edge triggered one-shot circuit of claim 1, wherein: The circuit further comprises a fifth resistor, one end of the fifth resistor is connected between the capacitor and the positive electrode of the diode, the other end of the fifth resistor is grounded.

4. The edge triggered one-shot circuit of claim 1, wherein: The circuit further comprises a sixth resistor, one end of the sixth resistor is connected between the drain of the second MOS tube and the low pulse output end, the other end of the sixth resistor is connected to a second continuous power supply end.

5. The edge triggered one-shot circuit of claim 1, wherein: The first MOS tube is provided with a first parasitic diode, a positive electrode of the first parasitic diode is connected to the source of the first MOS tube, a negative electrode of the first parasitic diode is connected to the drain of the first MOS tube.

6. The edge triggered one-shot circuit of claim 1, wherein: The second MOS tube is provided with a second parasitic diode, a positive electrode of the second parasitic diode is connected to the source of the second MOS tube, a negative electrode of the second parasitic diode is connected to the drain of the second MOS tube.

7. The edge triggered one-shot circuit according to any one of claims 1 to 6, characterized in that: The power supply voltage of the first continuous power supply end is 3.3V.

8. The edge triggered one-shot circuit of claim 4, wherein: The power supply voltage of the second continuous power supply end is 2.2V.

9. An edge triggered one-shot system, characterized by: The edge-triggered single-pulse circuit of any one of claims 1-8 is included.

10. An edge triggered one-shot device, characterized by: The edge-triggered single-pulse system of claim 9 is included.