Memory unit and integrated circuit

Abstract

The embodiment of the utility model provides a memory unit and an integrated circuit. An integrated circuit includes an array including a plurality of memory cells, wherein each memory cell includes a source region; a drain region; the channel region is connected between the source region and the drain region; a storage node formed on the channel region; and a control gate on the storage node; a plurality of word lines, wherein each word line is connected to the control gate in one column of the memory cells in the array; a bit line connected to a drain region of a row of the memory cells in the array; and a source line connected to the source region of at least one column of the memory cells in the array.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a non-volatile memory cell and an integrated circuit. BACKGROUND

[0002] Many modern electronic devices contain electronic memory to store data. Electronic memory can be volatile memory or non-volatile memory (NVM). Volatile memory stores data when powered on, while NVM is capable of retaining data when powered off. Multi-time programmable (MTP) cells are a promising candidate for next generation NVM. NVM is sometimes embedded in an integrated circuit, referred to as eNVM. Conventional eNVM uses a floating poly gate as a charge storage node. Thin oxide and metal gate processes become a bottleneck for eNVM during technology scaling. Embodiments of the present disclosure provide a novel NVM cell suitable for eNVM. SUMMARY

[0003] Embodiments of the present disclosure provide a memory cell, comprising a source region; a drain region; a channel region connecting the source region and the drain region; a first gate dielectric layer disposed on the channel region; a storage gate electrode layer disposed on the first gate dielectric layer; and a second gate electrode layer disposed on the storage gate electrode layer; and a second gate dielectric layer disposed between the storage gate electrode layer and the second gate electrode layer.

[0004] Some embodiments of the present disclosure relate to a memory cell, comprising a source region; a drain region; a channel region connecting the source region and the drain region and comprising two or more semiconductor fins; a first gate dielectric layer disposed on the channel region; a storage gate electrode layer disposed on the first gate dielectric layer; and a conductive gate electrode layer disposed on the storage gate electrode layer; and a second gate dielectric layer disposed between the storage gate electrode layer and the conductive gate electrode layer.

[0005] Some embodiments of the present disclosure relate to an integrated circuit, comprising an array comprising a plurality of memory cells, wherein each memory cell comprises a source region; a drain region; a channel region connecting between the source region and the drain region; a storage node formed on the channel region; and a control gate over the storage node; a plurality of word lines, wherein each word line is connected to the control gates in one column of memory cells in the array; a bit line connected to the drain regions of one row of memory cells in the array; and a source line connected to the source regions of at least one column of memory cells in the array. BRIEF DESCRIPTION OF DRAWINGS

[0006] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, for the purposes of conciseness and clarity, various features are not necessarily drawn to scale in the drawings. Indeed, the dimensions of the various features can be arbitrarily increased or decreased for the sake of presentation. In addition, some of the drawings can be simplified for a clear understanding. It should be noted that, in the following detailed description, references made to the figures will be by numbering thereof, relative to the priority date of the present disclosure.

[0007] FIGS. 1A-1C FIG. illustrates various views of a memory cell according to the present disclosure;

[0008] FIG. 2A FIG. illustrates a block diagram of circuitry of one embodiment of a memory cell according to the present disclosure; FIGS. 1A-1C

[0009] FIG. 2B and FIG. 2C FIG. illustrates operational states of a memory cell according to the present disclosure; FIG. 2A

[0010] FIG. 2D FIG. illustrates a block diagram of circuitry of another embodiment of a memory cell according to the present disclosure; FIGS. 1A-1C

[0011] FIG. 2E and FIG. 2F FIG. illustrates operational states of a memory cell according to the present disclosure; FIG. 2D

[0012] FIGS. 3A-3D is a schematic of voltages applied to the control gate, source region, and drain region in various operations;

[0013] FIGS. 4A-4B FIG. illustrates various views of a memory cell according to the present disclosure;

[0014] FIG. 5A is a layout diagram of a memory circuit according to an embodiment of the present disclosure;

[0015] FIGS. 5B-5C is a schematic cross-sectional view of a memory cell in a memory circuit according to the present disclosure; FIG. 5A

[0016] is a block diagram of a memory circuit according to the present disclosure; FIG. 5D FIG. 5A is a layout diagram of a memory circuit according to an embodiment of the present disclosure;

[0017] FIG. 6A is a schematic circuit of a memory circuit according to the present disclosure;

[0018] FIG. 6B FIG. 6A is a flowchart of a method for forming a memory cell according to an embodiment of the present disclosure;

[0019] FIG. 7 is a flowchart of a method for forming a memory cell according to an embodiment of the present disclosure;

[0020] ​​​​​​FIGS. 8-10A , FIGS. 10B-10D , FIG. 11A , FIGS. 11B-11D , FIG. 12A , FIGS. 12B-12D ,and FIGS. 13A-13C The illustrations show various views of forming memory cells according to embodiments of the present disclosure;

[0021] FIG. 14 A flowchart of a method for forming a memory cell according to an embodiment of the present disclosure;

[0022] FIG. 15A , FIGS. 15B-15D , FIG. 16A , FIGS. 16B-16D ,and FIGS. 17A-17C The figures illustrate various views of forming memory cells according to embodiments of the present disclosure.

[0023] [Symbol Explanation]

[0024] 100: Memory Unit

[0025] 100a: Memory unit

[0026] 100N: n-type field-effect transistor (N-type FET) / transistor

[0027] 100P: P-type field-effect transistor (P-type FET) / transistor

[0028] 101: Center Line

[0029] 102: Semiconductor substrate

[0030] 104: Fin-shaped channel area / channel area

[0031] 104s: Sidewall

[0032] 106: Quarantine Zone

[0033] 108d: Drain region

[0034] 108s: Source Region

[0035] 110: Gate structure

[0036] 112: First gate electrode layer

[0037] 114: First gate dielectric layer

[0038] 116: Second gate electrode layer

[0039] 116a, 116b: Second gate electrode layer / partial

[0040] 118: Second gate dielectric layer

[0041] 120: third gate dielectric layer

[0042] 122: sidewall spacer

[0043] 124: gate contact feature

[0044] 124a, 124b: gate contact feature

[0045] 126: control line

[0046] 128d: drain contact feature

[0047] 128s: source contact feature

[0048] 130: storage node

[0049] 132: current

[0050] 134: current

[0051] 200: memory circuit

[0052] 202: memory cell

[0053] 204: word line decoder

[0054] 206: bit line decoder

[0055] 208: control circuit

[0056] 250: memory circuit

[0057] 252: MTP cell

[0058] 254: bit line select transistor

[0059] 256: ground select transistor

[0060] 300: method

[0061] 302, 304, 306, 308, 310: operations

[0062] 400: memory circuit

[0063] 400a: memory circuit

[0064] 402: substrate

[0065] 404: semiconductor fin

[0066] 406: isolation layer

[0067] 408: sacrificial gate dielectric layer

[0068] 410: sacrificial gate electrode layer

[0069] 412: gate sidewall spacer

[0070] 414: replacement gate structure

[0071] 414a: replacement gate structure

[0072] 416: sacrificial gate structure

[0073] 418: source / drain region

[0074] 420: CESL

[0075] 422: ILD layer

[0076] 424: first gate dielectric layer

[0077] 424a: gate dielectric layer

[0078] 426: gate electrode layer

[0079] 426a: gate electrode layer

[0080] 428: storage node

[0081] 428a: storage node

[0082] 430: second gate dielectric layer

[0083] 432: storage gate electrode layer

[0084] 432a: storage gate electrode layer

[0085] 434: center axis

[0086] 436: gate contact feature

[0087] 438: word line

[0088] 440: source / drain contact feature

[0089] 442: source line

[0090] 444: conductive via

[0091] 446: bit line

[0092] 450: memory cell

[0093] 450a: memory cell

[0094] 500: method

[0095] 506, 508: operations

[0096] D: distance

[0097] T: thickness

[0098] S: interval

[0099] A-A, B-B, C-C: line DETAILED DESCRIPTION

[0100] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, formation of a first feature over or on a second feature in the following description can include embodiments in which the first feature is formed directly on the second feature or embodiments in which additional features can be formed between the first feature and the second feature such that the first feature is not formed directly on the second feature. Also, the present disclosure can refer to a number of elements by reference to a number of figures included herewith. Such references are intended to be illustrative of the various embodiments and / or configurations of the present disclosure and are not intended to limit the present disclosure in any way.

[0101] Also for ease of description, spatial terms, such as "below", "under", "lower", "above", "upper", and the like, can be used with respect to the drawings. The spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the drawings. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0102] Embodiments provide a multi-time programmable (MTP) memory cell including a Fin field effect transistor (FinFET) having a storage gate and a control gate. The storage gate includes a silicon nitride gate electrode. The control gate includes a metal-containing gate. The storage gate surrounds a channel region of the FinFET. The control gate surrounds the storage gate. In some embodiments, the storage gate and the control gate can be formed using a series of cut-metal gate processes used to fabricate complementary metal-oxide semiconductor (CMOS) transistors. The MTP memory cell according to the present disclosure can be formed from a P-type FinFET or an N-type FinFET.

[0103] The configuration of the storage gate and metal control gate enables efficient programming and erasure. Electrons can be selectively trapped in the storage gate of the MTP cell, allowing the MTP cell to be selectively set to a programmed or erased state. For example, in the programmed state, electrons are trapped in the storage gate, resulting in a low read current. In the erased state, electrons are cleared from the storage gate, resulting in a high read current. The MTP cell can be programmed or erased by applying a suitable control voltage to the control gate. The MTP cell can be programmed and / or erased via Fowler-Nordheim (FN) tunneling, channel hot electron injection (CHE), or band-to-band hot hole (BBHH) injection.

[0104] FIGS. 1A-1C The illustrations show various views of the memory cell 100 according to this disclosure. FIG. 1C This is a schematic top view of memory unit 100. FIG. 1A Along memory cell 100 FIG. 1C A schematic cross-sectional view of line AA in the middle. FIG. 8 Along memory cell 100 FIG. 1C A schematic cross-sectional view of the middle BB line. (See diagram below.) FIGS. 1A-1C As shown, memory cell 100 is a FinFET transistor formed on semiconductor substrate 102. Memory cell 100 may include a fin channel region 104. Fin channel region 104 may be formed by semiconductor substrate 102 and surrounded by isolation region 106. Memory cell 100 includes a gate structure 110 extending along a direction substantially perpendicular to fin channel region 104. Gate structure 110 is formed above fin channel region 104 and isolation region 106. Source region 108s and drain region 108d are disposed on opposite sides of gate structure 110. Source region 108s and drain region 108d may be epitaxially grown from fin channel region 104.

[0105] The gate structure 110 may include a first gate dielectric layer 114, a second gate dielectric layer 118, a third gate dielectric layer 120, a first gate electrode layer 112, and a second gate electrode layer 116 disposed between two sidewall spacers 122. The sidewall spacers 122 separate the source region 108s and the drain region 108d from the first, second, and third gate dielectric layers 114, 118, 120 and the first and second gate electrode layers 112, 116. The first gate dielectric layer 114 is disposed above a portion of the finned channel region 104 and the sidewall spacers 122. The first gate electrode layer 112 is disposed above the first gate dielectric layer 114 and surrounds the finned channel region 104 between the sidewall spacers 122. In some embodiments, the first gate electrode layer 112 may be substantially symmetrically disposed about the centerline 101 of the finned channel region 104. FIG. 1A As shown, a first gate electrode layer 112 is disposed on the sidewall 104s of the fin-shaped channel region 104. In some embodiments, the first gate electrode layer 112 may extend a distance D from both sides of the fin-shaped channel region 104. A second gate electrode layer 116 is disposed outside the first gate electrode layer 112. In some embodiments, two portions 116a and 116b of the second gate electrode layer 116 are disposed on both sides of the first gate electrode layer 112. A second gate dielectric layer 118 is disposed between the first gate electrode layer 112 and the second gate electrode layer 116. A third gate dielectric layer 120 is disposed between the second gate electrode layer 116 and the sidewall spacer 122, and between the second gate electrode layer 116 and the isolation region 106.

[0106] The first gate electrode layer 112 and the first gate dielectric layer 114 form a storage node 130 for the memory cell 100. Charge carriers, such as electrons, can be stored in or erased from the storage node 130. The second gate electrode layer 116 adjacent to the storage node 130 can be used as a control gate for programming and erasing the storage node 130. By connecting the second gate electrode layer 116 via interconnects, an appropriate control gate voltage can be applied to the storage node 130 to program and erase the memory cell 100. The efficiency of programming and erasing operations can be improved by selecting an appropriate control gate voltage. Furthermore, the distance D between the second gate electrode layer 116 and the fin channel region 104 can be selected to obtain a desired cell coupling ratio. For example, reducing the distance D can improve the efficiency of programming / erasing operations. In some embodiments, the distance D is in the range of about 5 nm to about 100 nm. A distance D greater than 100 nm may not achieve an effective programming / erasing operation. A distance D less than 5 nm may not provide enough storage volume in storage node 130 to trap enough electrons to induce a detectable difference between programmed and erased states.

[0107] Different combinations of voltages can be applied to the second gate electrode layers 116, the source regions 108s, and the drain regions 108d to program (charge), erase, and read the charge in the storage node 130. Gate contact features 124a, 124b are formed in contact with the second gate electrode layers 116a, 116b. In some embodiments, the gate contact features 124a, 124b are electrically connected by a control line 126. A control voltage can be applied to the second gate electrode layers 116a, 116b through the control line 126. Source contact features 128s and drain contact features 128d are in contact with the source regions 108s and the drain regions 108d, respectively. Voltages can be applied to the source regions 108s and the drain regions 108d through the source contact features 128s and the drain contact features 128d, respectively.

[0108] The semiconductor substrate 102 can be or include a bulk semiconductor substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or another suitable substrate material. In some embodiments, the semiconductor substrate 102 can include one or more doped regions.

[0109] The fin-shaped channel regions 104 can be formed in discrete doped regions or well regions in the semiconductor substrate 102. The fin-shaped channel regions 104 can include p-type dopants or n-type dopants, resulting in the memory cell 100 being a p-type FinFET or an n-type FinFET.

[0110] The source regions 108s and the drain regions 108d can include one or more layers of Si, SiP, SiC, and SiCP for n-type devices or Si, SiGe, Ge for p-type devices. For n-type devices, the source regions 108s and the drain regions 108d also include n-type dopants, such as phosphorus (P), arsenic (As), etc. For p-type devices, the source regions 108s and the drain regions 108d can include p-type dopants, such as boron (B).

[0111] The first gate electrode layer 112 can be formed of silicon nitride, silicon oxynitride, an alloy of silicon oxide and silicon nitride, combinations thereof, or any suitable material for storing charge therein.

[0112] The second gate electrode layer 116 can be one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. In some embodiments, the second gate electrode layer 116 can include tungsten, aluminum, titanium nitride, tantalum nitride, or combinations thereof.

[0113] The first gate dielectric layer 114, the second gate dielectric layer 118, and the third gate dielectric layer 120 can include one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric material, and / or combinations thereof. Examples of high-k dielectric material include Hf02, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (Hf02- Al203) alloy, other suitable high-k dielectric material, and / or combinations thereof. In some embodiments, the first gate dielectric layer 114, the second gate dielectric layer 118, and the third gate dielectric layer 120 can include SiOx, HfOx, ZrOx, or combinations thereof. The first gate dielectric layer 114, the second gate dielectric layer 118, and the third gate dielectric layer 120 can have the same or different compositions and / or thicknesses, depending on the circuit design.

[0114] FIG. 2A FIG. 1 is a schematic diagram of a memory cell 100. FIGS. 1A-1C FIG. 2 is a block diagram of the circuit of the memory cell 100. FIG. 2B FIG. 3 is a schematic diagram of the memory cell 100. FIG. 2C FIG. 4 is a schematic diagram of the memory cell 100. FIGS. 1A-1C FIG. 5 is a schematic diagram of the memory cell 100. FIG. 2A As shown in FIG. 5, the source region 108s, the drain region 108d, the channel region 104, and the gate structure 110 form an n-type field effect transistor 100N, in which the majority of the current carriers are electrons. In this case, the transistor 100N is an N-type FinFET. In some embodiments, the transistor 100N is an N-channel enhancement mode MOSFET. When the transistor 100N is turned on, i.e., a sufficient positive voltage Vdd is applied to the drain region 108d and a sufficient positive voltage (e.g., Vdd) is applied to the second gate electrode layer 116, a current 132 of electrons flows through the channel region 104. In some embodiments, the voltage Vdd indicates a positive power supply voltage for the MOSFET circuit. The voltage Vdd can be about 5 V, about 3.3 V, about 1.8 V, about 1.2 V, or any suitable value depending on the circuit design.

[0115] FIG. 2B FIG. 6 shows the transistor 100N of the memory cell 100 in an initial state or an erased state, in which electrons are not trapped or ejected from the first gate electrode layer 112 of the storage node 130. When the transistor 100N is turned on in the initial or erased state, a normal or high current 132 of electrons flows through the channel region 104.

[0116] FIG. 2CThe transistor 100N of the memory cell 100 in the programmed state is shown, wherein a portion of the current-carrying electrons in the channel region 104 are trapped in the first gate electrode layer 112 of the storage node 130. When the transistor 100N is turned on in the programmed state, the reduced number of current-carrying electrons in the channel region 104 reduces the electron current 132, resulting in a low-current state.

[0117] During a read operation, transistor 100N is turned on, and the value of memory cell 100 is obtained through current 132. A high current 132 via channel region 104 indicates that memory cell 100 is in an erase or initial state, while a low current 132 via channel region 104 indicates that memory cell 100 is in a programmed state.

[0118] Alternatively, the source region 108s, drain region 108d, channel region 104, and gate structure 110 can also be P-type transistors and function in a similar manner.

[0119] FIG. 2D The figure shows a block diagram of a circuit according to another embodiment of memory cell 100. FIG. 2D In this configuration, the source region 108s, drain region 108d, channel region 104, and gate structure 110 form a P-type field-effect transistor 100P, wherein the majority of the current carriers are holes. In this case, transistor 100P is a P-type FinFET. In some embodiments, transistor 100P is a P-channel enhancement-mode MOSFET. When transistor 100P is turned on, i.e., when a sufficient negative voltage (Vdd) is applied to drain region 108d, 0V is applied to source region 108s, and a negative voltage (Vdd) is also applied to second gate electrode 116, a normal or low hole current 134 flows through channel region 104.

[0120] FIG. 2E and FIG. 2F Illustration FIG. 2D The operational state of the memory unit. FIG. 2E The transistor 100P of the memory cell 100 is displayed in an initial or erased state, wherein electrons are not trapped or ejected from the first gate electrode layer 112 of the storage node 130. When the transistor 100P is turned on in the initial or erased state, a normal or low hole current 134 flows through the channel region 104.

[0121] FIG. 2F The transistor 100P of the memory cell 100 in a programmed state is shown, wherein electrons in the channel region 104 are trapped in the first gate electrode layer 112 of the storage node 130, thereby generating additional current-carrying holes in the channel region 104. When the transistor 100P is turned on in the programmed state, the additional current-carrying holes in the channel region 104 achieve a high hole current 134, resulting in a high current state.

[0122] During a read operation, transistor 100P is turned on and the value of memory cell 100 is obtained through current 134. A low current 134 through channel region 104 indicates that memory cell 100 is in an erased or initial state, while a high current 134 through channel region 104 indicates that memory cell 100 is in a programmed state.

[0123] As mentioned above, memory cell 100 is a multiple-time-programmable (MTP) cell with two states: a programmed state and an erased state. Electrons are stored in storage node 130 in the programmed state and are released from storage node 130 in the erased state. The electrons stored in storage node 130 affect the threshold voltage of memory cell 100 and the current through channel region 104. For a memory cell with an n-channel, the programmed state has a low current and the erased state has a high current. For a memory cell with a p-channel, the programmed state has a high current and the erased state has a low current.

[0124] Memory cell 100 can be programmed and erased by applying appropriate voltages to source region 108s, drain region 108d, and second gate electrode layer 116 or control gate. Memory cell 100 can be programmed by Fowler-Nordheim (FN) tunneling or by channel hot electron injection (CHE). Memory cell 100 can be erased by Fowler-Nordheim (FN) tunneling or by band-to-band hot hole injection (BBHH).

[0125] Table 1 is a table of programming and erasing operation conditions for memory cell 100. In particular, Table 1 shows programming and erasing operations for memory cell 100 with an N-type FET 100N.

[0126]

[0127] Table 1, Programming and erasing operation conditions for memory cell

[0128] Programming and erasing methods can be mixed and combined according to circuit design. FIGS. 3A-3D To show the voltages applied to control gate or second gate electrode layer 116, source region 108s, and drain region 108d in various operations.

[0129] As FIG. 3AAs shown, to program a memory cell with an N-type FET 100N using channel hot electron injection (CHE), a positive voltage Vdd2 is applied to the control gate or second gate electrode 116, a positive voltage Vdd1 is applied to the drain region 108d, and the voltage applied to the source region 108s is approximately 0V. The N-type FET 100N is turned on by the positive voltages Vdd2 and Vdd1, causing an electron current to flow through the channel region 104. A portion of the electrons in the current can be injected and trapped in the storage node 130, thereby turning the memory cell 100 into a programmed state. In some embodiments, the positive voltages Vdd1 and Vdd2 are greater than Vdd. Voltages Vdd1 and Vdd2 can be selected according to the circuit design. In some embodiments, voltage Vdd2 is greater than voltage Vdd1 to obtain an improved charging speed.

[0130] like FIG. 3C As shown, to program a memory cell with an N-type FET 100N using Fowler-Nordheim (FN) tunneling, a positive high voltage HV is applied to the control gate or second gate electrode layer 116, while the voltage applied to the source region 108s and drain region 108d is approximately 0V. When the positive high voltage HV is applied to the second gate electrode layer 116, electrons in the channel region 104 are "sucked in" and trapped in the storage node 130, thereby putting the memory cell 100 into a programmed state. In some embodiments, for example, the high voltage HV may be in the range of about 7 to 10V, about 11 to 18V, or another suitable value.

[0131] like FIG. 3B As shown, to erase a memory cell with an N-type FET 100N using band-to-band hot hole injection (BBHH), a negative voltage Vdd4 is applied to the control gate or second gate electrode layer 116 to attract holes for injection into the storage gate, and a positive voltage Vdd3 is applied to the drain region 108d and the source region 108s. The positive voltage Vdd4 is lower than the positive voltage Vdd3. The higher voltage Vdd3 in the source region 108s and the drain region 108d drives hot holes in the channel region 104 into the storage node 130 to erase the trapped electrons in the storage node 130, thereby putting the memory cell into an erased state. In some embodiments, the positive voltages Vdd3 and Vdd4 are greater than Vdd.

[0132] like FIG. 3DAs shown, to erase a memory cell having an N-type FET 100N using Fowler-Nordheim (FN) tunneling, a negative high voltage -HV is applied to the control gate or second gate electrode layer 116, while the voltage applied to the source region 108s and the drain region 108d is about 0 V. When the negative high voltage -HV is applied to the second gate electrode layer 116, the electrons trapped in the storage node 130 are driven back into the channel region 104, thereby changing the memory cell 100 to an erased state. In some embodiments, for example, the high voltage HV can be in a range of about 7 to 10 V, in a range of about 11 to 18 V, in a range of about 7 to 18 V, or another suitable value.

[0133] Although one fin-shaped channel region 104 is shown in the memory cell 100, a memory cell according to the present disclosure can include two or more fin structures to obtain a larger channel region.

[0134] FIGS. 4A-4B Figures illustrating various views of a memory cell 100a according to the present disclosure. FIG. 4B is a schematic top view of the memory cell 100a. FIG. 4A is a schematic cross-sectional view of the memory cell 100a along line A-A of FIG. 4B The memory cell 100a is substantially similar to the memory cell 100, except that the memory cell 100a includes two fin-shaped channel regions 104 to form an increased channel region.

[0135] FIG. 5A is a layout diagram of a memory circuit 200 according to embodiments of the present disclosure. FIGS. 5B-5C is a schematic top view of the memory circuit 200. FIG. 5A is a schematic cross-sectional view of the memory cell 100 in the memory circuit 200 of FIG. 5D is a schematic circuit of the memory circuit 200. FIG. 5A is a schematic circuit of the memory circuit 200.

[0136] Memory circuit 200 includes a plurality of rows and columns of memory cells 202. In some embodiments, each memory cell 202 can have a structure similar to memory cell 100 or memory cell lOOa. Memory circuit 200 includes a plurality of memory cells 202, a plurality of bit lines BLk (k is an integer), a plurality of source lines SLm (m is an integer), and a plurality of word lines WLn (n is an integer), a word line decoder 204, a bit line decoder 206, and a control circuit 208. The plurality of word lines WLn are electrically connected to word line decoder 204. The plurality of bit lines BLk are electrically connected to bit line decoder 206. A memory cell 202 in the kth row and the nth column can be identified by 202(n, k). In some embodiments, the plurality of source lines SLm are electrically coupled to support read circuitry (not shown), such as multiplexers and / or amplifiers to determine the output of a read operation.

[0137] In FIG. 5A and FIG. 5D , a portion of memory circuit 200 having 16 memory cells 202 is shown. In particular, FIG. 5A and FIG. 5D four word lines WLn, WLn+1, WLn+2, WLn+3 are shown, four bit lines BLk, BLk+1, BLk+2, BLk+3 are shown, and two source lines SLm, SLm+1 are shown.

[0138] In FIG. 5A , memory cells 202 can be configured as FIGS. 1A-1C memory cells 100. Memory cells 202 are configured within a memory array including rows and columns. Memory cells 202 within a column of the memory array are operatively coupled to a word line WLn, while memory cells 202 within a row of the memory array are operatively coupled to a bit line BLk. Thus, a plurality of memory cells 202 will be associated with an address defined by the intersection of a word line WLn and a bit line BLk, respectively.

[0139] The memory array is electrically coupled to support circuitry to perform write operations (i.e., erase operations and / or program operations) and / or read operations on the plurality of memory cells 202. In some embodiments, the support circuitry includes control circuit 208, word line decoder 204, and bit line decoder 206. In some embodiments, control circuit 208 is a microprocessor circuit.

[0140] In some embodiments, FIG. 5A and FIG. 5DThe memory array in the memory circuit 200 is a NOR array. The control gate or second gate electrode layer 116 of the memory cell 100 is connected to a corresponding word line WLn. The source region 108s of each memory cell 100 is connected to a corresponding source line SLm. The drain region 108d of each memory cell 100 is connected to a corresponding bit line BLk. The word line WLn, the bit line BLk, and the source line SLm are used together to accomplish read, program, and erase operations.

[0141] In some embodiments, two adjacent memory cells 100 in the same row are mirror images of each other, such that the source regions 108s can be merged to connect with one source line SLm, thereby increasing cell density. Similarly, the drain regions 108d of adjacent memory cells 100 in the same row can be merged to connect with one bit line connector, thereby increasing cell density.

[0142] FIG. 5B and FIG. 5C A local cross-sectional view of one memory cell 202(n+3, k+3) in the memory circuit 200 to show a connection configuration according to one embodiment of the disclosure. The word line WLn and the source line SLm can be configured along a first direction and in the same intermetal dielectric (IMD) layer, for example, in a first IMD layer. The bit line BLk can be configured along a second direction perpendicular to the first direction and in a different IMD layer, for example, in a second IMD layer.

[0143] The control circuit 208 is used to control the word line decoder 204 and / or the bit line decoder 206 to accomplish read, program, and erase operations. For example, the control circuit 208 can supply an address (e.g., an address associated with a single memory cell 202 in the memory array) to the word line decoder 204 and / or the bit line decoder 206. In some embodiments, the word line decoder 204 is used to selectively apply a signal (e.g., a current and / or a voltage) to the word line WLn based on the received address. The bit line decoder 206 is used to selectively apply a signal (e.g., a current and / or a voltage) to the bit line BLk based on the received address. A multiplexer and / or an amplifier can determine the output of a read operation according to the current via the corresponding source line SLm.

[0144] FIG. 6A A layout diagram of a memory circuit 250 according to an embodiment of the disclosure. FIG. 6B A layout diagram of a memory circuit 250 according to an embodiment of the disclosure. FIG. 6Aschematic circuit of a memory circuit 250. The memory circuit 250 can be placed and designed with a NAND-type memory array. In some embodiments, the memory circuit 250 includes a plurality of multi-MTP cells 252. Each multi-MTP cell 252 includes a chain of n memory cells 252i,..., 252 n formed in rows. Each of the memory cells 252i,..., 252 n may be a FinFET transistor having storage nodes and a control gate formed over the storage nodes, with a spacing S between the storage nodes. The memory cells 252i,..., 252 n may be fabricated from the same one or more semiconductor fins. The number n can be 8, 16, or other suitable number according to circuit design. In some embodiments, the memory cells 252i,..., 252 n may be similar to the memory cells 100, 100a described above.

[0145] Each multi-MTP cell 252 further includes a bit line select transistor 254 and a ground select transistor 256. The bit line select transistor 254 and the ground select transistor 256 are connected in series with the chain of cells. For example, the bit line select transistor 254 can be disposed adjacent to the first memory cell 252i, and the ground select transistor 256 can be disposed adjacent to the last memory cell 252 n In some embodiments, the bit line select transistor 254 and the ground select transistor 256 can be formed from the same fins as the memory cells 252i,..., 252 n .

[0146] The memory circuit 250 includes an array of the multi-MTP cells 252 configured in an array. FIG. 6A and FIG. 6B shows two rows of multi-MTP cells 252, one column per row. It is noted that the memory circuit 250 can include multiple rows of multi-MTP cells 252, each row including two or more multi-MTP cells 252. The memory circuit 250 further includes a plurality of bit lines BLk (k is an integer), a plurality of source lines SLm (m is an integer), and a plurality of word lines WLn (n is an integer). The plurality of word lines WLn can be connected to a word line decoder. The plurality of bit lines BLk can be connected to a bit line decoder 206.

[0147] Each word line BLk is operatively coupled to the bit line select transistor 254 of the multi-MTP cell 252 in the k-th row. Each word line WLn is operatively coupled to the control gate or second gate electrode of the memory cell 252n in the multiple rows of multi-MTP cells 252. Each source line SLm is connected to the ground select transistor 256 of the m-th multi-MTP cell 252 in a row. Each multi-MTP cell 252 contains memory cells 2521, ..., 252. n They share a single source line SLm. As mentioned above, memory cells 2521, ..., 252... n Each of the memory cells 100 or 100a may have the structure described above. In the memory circuit 250, the control gate or second gate electrode layer 116 of the memory cell 100 (memory cell 252) is connected to the corresponding word line WLn. However, the source region 108s and drain region 108d of each memory cell 100 are not in direct contact with the source line SLm or the bit line BLk. Instead, the source region 108s and drain region 108d of each memory cell 100 are connected to the corresponding source line SLm or bit line BLk through the ground selection transistor 256 and the bit line selection transistor 254 in the multi-MTP cell 252. This configuration allows for the minimization of memory cells 100 and 100a, thereby achieving a high cell density.

[0148] FIG. 7 This is a flowchart of a method 300 for forming a memory circuit according to an embodiment of the present disclosure. FIGS. 8-10A , FIGS. 10B-10D , FIG. 11A , FIGS. 11B-11D , FIG. 12A , FIGS. 12B-12D ,and FIGS. 13A-13C The figures illustrate various views of a memory circuit 400 formed according to an embodiment of the present disclosure. The memory circuit 400 may include a plurality of memory cells, similar to the memory cell 100 described above.

[0149] In operation 302 of method 300, semiconductor fins 404 are formed on substrate 402, and an isolation layer 406 is formed in the trenches between the semiconductor fins 404, such as FIG. 8 As shown in the image. FIG. 8A schematic perspective view of a memory circuit 400 according to the present disclosure. The substrate 402 can comprise a single crystalline semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Depending on the circuit design, the substrate 402 can comprise various doping configurations. For example, the substrate 402 can be one or more p-type doped regions and one or more n-type doped regions. The semiconductor fins 404 are then formed using one or more patterning and etching processes. The isolation layer 406 is formed in the trenches between the semiconductor fins 404 by a suitable deposition followed by an etch-back process. As an example, the bottom profile of the isolation layer 406 is shown as curved. Depending on the pitch and / or height of the semiconductor fins 404, the bottom profile of the isolation layer 406 can vary, for example, curved, substantially flat, or other shape. The isolation layer 406 can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition process. In some embodiments, the isolation layer 406 can comprise silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate glass, low-k dielectric, combinations thereof. In some embodiments, the isolation layer 406 is formed by a suitable deposition process to cover the semiconductor fins 404, filling the trenches between the semiconductor fins 404, a planarization process can be performed to expose the semiconductor fins 404, and then a suitable anisotropic etching process is used to etch the recesses to expose a portion of the semiconductor fins 404, as shown in FIG. 8

[0150] At operation 304, the sacrificial gate structure 416 and the source / drain regions 418 are formed, as shown in FIG. 9 FIG. 9 A schematic perspective view of a memory circuit 400 according to the present disclosure.

[0151] To form the sacrificial gate structure 416, a sacrificial gate dielectric layer 408 is conformally formed over the substrate 402. The sacrificial gate dielectric layer 408 is formed over the semiconductor fins 404 and the isolation layer 406. The sacrificial gate dielectric layer 408 can comprise silicon oxide, silicon nitride, combinations thereof, or the like. The sacrificial gate dielectric layer 408 can be deposited or thermally grown according to acceptable techniques such as thermal CVD, CVD, ALD, and other suitable methods.

[0152] ​​A sacrificial gate electrode layer 410 is deposited on the sacrificial gate dielectric layer 408 and then planarized by a CMP process. The sacrificial gate electrode layer 410 includes silicon, such as polysilicon, amorphous silicon, polysilicon germanium (SiGe), or the like. In some embodiments, the sacrificial gate electrode layer 410 is subjected to a planarization operation. The sacrificial gate electrode layer 410 can be deposited using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable processes. A patterning operation is performed on the sacrificial gate electrode layer 410 and the sacrificial gate dielectric layer 408 to form the sacrificial gate structure 416 using one or more etching processes, such as one or more plasma etching processes or one or more wet etching processes. In some embodiments, a masking layer and a liner layer (not shown) are first patterned using a patterning process. The patterned masking layer and liner layer are then used as an etching mask to pattern the sacrificial gate electrode layer 410. In some embodiments, the sacrificial gate electrode layer 410 can be etched by an anisotropic etch, such as a reactive ion etching (RIE) process. The anisotropic etch has a greater etch rate along the Z direction than the etch rate along the X and Y directions. During etching of the sacrificial gate electrode layer 410, the sacrificial gate dielectric layer 408 on the semiconductor fin 404 can act as an etch stop layer to prevent the etchant from removing the semiconductor fin 404. In some embodiments, after patterning the sacrificial gate electrode layer 410, any exposed residual sacrificial gate dielectric layer 408 is removed by a suitable etching process. In some embodiments, the residual sacrificial gate dielectric layer 408 can be etched by tuning one or more parameters of the etching process used to etch the sacrificial gate electrode layer 410, such as the etchant, etching temperature, etching solution concentration, etching pressure, source power, radio frequency (RF) bias voltage, etchant flow rate.

[0153] The sacrificial gate structure 416 covers a portion of the semiconductor fin 404. The portion of the semiconductor fin 404 covered by the sacrificial gate structure 416 eventually forms a channel region. A gate sidewall spacer 412 is formed on the sidewalls of the sacrificial gate structure 416. The gate sidewall spacer 412 can include one or more dielectric layers.

[0154] The semiconductor fin 404 not covered by the sacrificial gate structure 416 is recess etched to form source / drain recesses on both sides of the sacrificial gate structure 416. Epitaxial source / drain regions 418 are formed in the source / drain recesses. In some embodiments, the epitaxial source / drain regions 418 can be grown in an epitaxial chamber by a suitable process.

[0155] As FIG. 10A , FIG. 10B , FIG. 10C , and FIG. 10DAs shown in FIG. 4, a contact etch stop layer (CESL) 420 and an interlayer dielectric (ILD) layer 422 are formed over the memory circuit 400. FIG. 10A FIG. 5 is a schematic perspective view of a memory circuit 400 according to the present disclosure. FIG. 10B 、 FIG. 10C 、and FIG. 10D are schematic cross-sectional views of the memory circuit 400 along the centerlines A-A, B-B, and C-C, respectively. FIG. 10A

[0156] The CESL 420 is conformally formed over the exposed surface of the memory circuit 400. The CESL 420 is formed over the exposed epitaxial source / drain regions 418, the gate sidewall spacers 412, and the isolation layer 406. The CESL 420 can include SiN, SiON, SiCN, or any other suitable material, and can be formed by CVD, PVD, or ALD. An interlayer dielectric (ILD) layer 422 is formed over the CESL 420. Materials for the ILD layer 422 include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, can be used for the ILD layer 422. In some embodiments, the ILD layer 422 can be formed by flowable CVD (FCV). The ILD layer 422 protects the epitaxial source / drain regions 418 during removal of the sacrificial gate structure 416.

[0157] At operation 306, as shown in FIG. 11A 、 FIGS. 11B-11D 、 FIG. 11A 、and FIGS. 11B-11D the replacement gate structure 414 is formed. FIG. 11A FIG. 5 is a schematic perspective view of a memory circuit 400 according to the present disclosure. FIGS. 11B-11D 、 FIG. 11A 、and FIGS. 11B-11D are schematic cross-sectional views of the memory circuit 400 along the centerlines A-A, B-B, and C-C, respectively. FIG. 11A The sacrificial gate dielectric layer 408 and the sacrificial gate electrode layer 410 are removed by one or more suitable processes, such as dry etching, wet etching, or a combination thereof, to expose the semiconductor fin 404. In some embodiments, a wet etchant, such as tetramethylammonium hydroxide (TMAH) solution, is used. The replacement gate structure can include a first gate dielectric layer 424 and a gate electrode layer 426.

[0158]

[0159] ​​The first gate dielectric layer 424 may be conformally deposited on the exposed surface in the gate cavity. For N-type and P-type devices, the first gate dielectric layer 424 may have different compositions and dimensions, and may be formed separately using a patterned masking layer and different deposition formulations. The first gate dielectric layer 424 may include one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The first gate dielectric layer 424 may be formed by CVD, ALD, or any suitable method.

[0160] Next, a gate electrode layer 426 is formed on the first gate dielectric layer 424 to fill the gate cavity. The gate electrode layer 426 may comprise one or more layers of conductive materials, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. In some embodiments, the gate electrode layer 426 may be formed by CVD, ALD, electroplating, or other suitable methods. After forming the gate electrode layer 426, a planarization process, such as a CMP process, is performed to remove excess deposits of the gate electrode material and expose the top surface of the ILD layer 422.

[0161] At operation 308, storage node 428 is formed between gate sidewall spacers 412 above semiconductor fin 404, such as FIGS. 12B-12D , FIG. 12A , FIGS. 12B-12D , FIG. 12A As shown in the image. FIGS. 12B-12D This is a schematic perspective view of the memory circuit 400 according to the present disclosure. FIG. 12A , FIGS. 12B-12D ,and FIG. 12A respectively along FIGS. 1A-1C A schematic cross-sectional view of the memory circuit 400 with center lines AA, BB, and CC.

[0162] The storage node 428 is formed within the replacement gate structure 414 and above the semiconductor fin 404. A patterning process can be performed to "cut" the replacement gate structure 414 into sections by removing the gate electrode layer 426 and the first gate dielectric layer 424 above the semiconductor fin 404. After the cutting process, the semiconductor fin 404 is exposed between the gate sidewall spacers 412. A second gate dielectric layer 430 is then deposited over the exposed surfaces including the semiconductor fin 404, the isolation layer 406, the gate sidewall spacers 412, the first gate dielectric layer 424, and the gate electrode layer 426. A storage gate electrode layer 432 is then deposited over the second gate dielectric layer 430 and fills the opening above the semiconductor fin 404. The storage gate electrode layer 432 and the second gate dielectric layer 430 form the storage node 428.

[0163] In some embodiments, the second gate dielectric layer 430 can include one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include Hf02, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (Hf02- Al203) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the second gate dielectric layer 430 can include SiOx, HfO, ZrOx, or combinations thereof. The second gate dielectric layer 430 can be formed by CVD, ALD, or any suitable method. The composition and dimensions of the second gate dielectric layer 430 can be selected according to the circuit design.

[0164] In some embodiments, the storage gate electrode layer 432 can include one or more layers of materials suitable for trapping electrons therein. In some embodiments, the storage gate electrode layer 432 is formed of silicon nitride, silicon oxynitride, an alloy of silicon oxide and silicon nitride, combinations thereof, or any suitable material for storing charge therein. The storage gate electrode layer 432 can be formed by CVD, ALD, or any suitable method. After depositing the storage gate electrode layer 432, a planarization process, such as CMP, can be performed to expose the gate electrode layer 426 for subsequent formation of gate contact features.

[0165] In some embodiments, the storage node 428 can be formed substantially symmetrically about a central axis 434 of the corresponding semiconductor fin 404. As shown in FIG. 4B, the central axis 434 of the semiconductor fin 404 is aligned with the center of the replacement gate structure 414. The storage node 428 is formed symmetrically about the central axis 434 of the semiconductor fin 404. In some embodiments, the storage node 428 can be formed asymmetrically about the central axis 434 of the corresponding semiconductor fin 404. For example, the storage node 428 can be formed asymmetrically about the central axis 434 of the semiconductor fin 404 to compensate for asymmetry in the replacement gate structure 414. FIG. 17AAs shown in FIG. 4, the storage gate electrode layer 432 can have substantially equal thickness T on either side of the semiconductor fin 404. The thickness T can be in a range between about 5 nm and about 100 nm. In some embodiments, the second gate dielectric layer 430 can have a thickness in a range between about 2 nm and about 10 nm. In some embodiments, a ratio of the thicknesses of the second gate dielectric layer 430 and the storage gate electrode layer 432 can be in a range between about 0.01 and about 0.2.

[0166] As FIGS. 17B-17C shown in FIG. 4, the second gate dielectric layer 430 is disposed between the gate electrode layer 426 and the storage gate electrode layer 432. In some embodiments, the first gate dielectric layer 424 and the second gate dielectric layer 430 can be formed of the same material. In other embodiments, the first gate dielectric layer 424 and the second gate dielectric layer 430 can be formed of different materials depending on the circuit design.

[0167] After operation 308, a plurality of memory cells 450 is formed over the substrate 402. The memory cells 450 are similar to the memory cells 100 of FIG. 17A FIG. 3.

[0168] At operation 310, gate contact features 436 and / or source / drain contact features 440 can be formed to connect the memory cells 450, as shown in FIGS. 17B-17C , FIG. 17A , and FIGS. 17B-17C FIGS. 5, 6, and 7, respectively. FIG. 17A , FIGS. 16B-16D , and ​ are schematic cross-sectional views of the memory circuit 400 along the centerlines A-A, B-B, and C-C of ​ FIG. 4, respectively.

[0169] At operation 310, conductive lines and vias are formed in the dielectric material in the layer to provide electrical connections to the source / drain regions 418 and the gate electrode layer 426 so that the memory cells 450 can be read, programmed, and erased. In some embodiments, the gate contact features 436 are formed to connect the gate electrode layer 426 to the word lines 438. The source / drain contact features 440 are formed to connect the source / drain regions 418 to the source lines 442 or the bit lines 446 through the conductive vias 444. In some embodiments, the word lines 438 and the source lines 442 are disposed in the first IMD layer and extend along the y-axis, while the bit lines 446 are disposed in the second IMD layer and extend along the x-axis. The conductive lines and vias can be configured in different configurations depending on the circuit design.

[0170] ​ is a flowchart of a method 500 for forming a memory circuit according to embodiments of the present disclosure. ​ , ​ ,​ , ​ ,and ​ The figures illustrate various views of forming a memory circuit 400a according to an embodiment of the present disclosure. The memory circuit 400a may include a plurality of memory cells, similar to the memory cell 100 described above. Method 500 begins with operations 302 and 304, as described above and as... ​ As shown in the image.

[0171] At operation 506, storage node 428a is formed by cutting the sacrificial gate electrode layer 410 over semiconductor fin 404 and depositing storage gate electrode layer 432a, as shown. ​ , ​ , ​ , ​ As shown in the image. ​ This is a schematic perspective view of the memory circuit 400a according to the present disclosure. ​ , ​ ,and ​ respectively along ​ A schematic cross-sectional view of the memory circuit 400a with center lines AA, BB, and CC.

[0172] Storage node 428a is formed within the sacrificial gate structure 416 and above the semiconductor fin 404. A patterning process is performed to "cut" the sacrificial gate electrode layer 410 into several portions through patterning and etching processes. After the cutting process, the sacrificial gate dielectric layer 408 is exposed between the gate sidewall spacers 412. Storage gate electrode layer 432a is then deposited over the sacrificial gate dielectric layer 408 and fills the openings between the gate sidewall spacers 412. Storage gate electrode layer 432a and sacrificial gate dielectric layer 408 form storage node 428a. Storage gate electrode layer 432a contacts the gate sidewall spacers 412 and several portions of the sacrificial gate electrode layer 410.

[0173] In some embodiments, the storage gate electrode layer 432a may comprise one or more layers of materials suitable for trapping electrons therein. In some embodiments, the storage gate electrode layer 432a is formed of silicon nitride, silicon oxynitride, an alloy of silicon oxide and silicon nitride, a combination thereof, or any suitable material for storing charge therein. The storage gate electrode layer 432a may be formed by CVD, ALD, or any suitable method. After depositing the storage gate electrode layer 432a, a planarization process, such as CMP, may be performed to expose the sacrificial gate electrode layer 410 for replacement gate processes.

[0174] At operation 508, such as ​ , ​ , ​ ,and ​ As shown, a replacement gate structure 414a is formed.​ FIG. 19 is a schematic perspective view of a memory circuit 400a according to the present disclosure. ​ ​ ​ FIGS. 19, 20, 21, and 22 are schematic cross-sectional views of the memory circuit 400a along the centerlines A-A, B-B, and C-C, respectively. ​

[0175] In some embodiments, the sacrificial gate electrode layer 410 is selectively etched to expose the underlying sacrificial gate dielectric layer 408. In some embodiments, the sacrificial gate dielectric layer 408 can be removed by one or more suitable processes, such as dry etching, wet etching, or a combination thereof, to expose the semiconductor fin 404. A gate cavity is formed between the gate sidewall spacers 412 and between the storage gate electrode layers 432a.

[0176] A gate dielectric layer 424a is then deposited on the exposed surfaces of the gate cavity. In particular, the gate dielectric layer 424a can be deposited over the sidewalls of the storage gate electrode layers 432a, the gate sidewall spacers 412, and the isolation layer 406.

[0177] The gate dielectric layer 424a can have different compositions and dimensions for N-type devices and P-type devices, and formed separately using patterned masking layers and different deposition recipes. The gate dielectric layer 424a can include one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include Hf02, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (Hf02-Al203) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 424a can be formed by CVD, ALD, or any suitable method.

[0178] A gate electrode layer 426a is then formed on the gate dielectric layer 424a to fill the gate cavity. The gate electrode layer 426a can include one or more layers of conductive materials, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. In some embodiments, the gate electrode layer 426a can be formed by CVD, ALD, electroplating, or other suitable methods. After forming the gate electrode layer 426a, a planarization process, such as a CMP process, is performed to remove excess deposition of the gate electrode material and expose the top surface of the ILD layer 422.

[0179] After operation 508, a plurality of memory cells 450a is formed over the substrate 402. The memory cells 450a are similar to the memory cells 450 of FIG. 18, except that the memory cells 450a include the gate dielectric layer 424a and the gate electrode layer 426a.​​​​ memory cell 100.

[0180] Operation 310 is then performed to form gate contact features 436 and / or source / drain contact features 440 can be formed to connect memory cell 450a, as shown in ​ 、 ​ 、 ​ shown in FIG. 4B. ​ 、 ​ 、 and ​ are schematic cross-sectional views of memory circuit 400a along centerlines A-A, B-B, and C-C, respectively, of ​

[0181] Embodiments of the present disclosure provide a MTP memory cell and methods of forming the same. The MTP memory cell includes a FinFET transistor having a storage node formed around a channel region and a metal gate formed around the storage node. The memory cell can be implemented by either an n-channel transistor or a p-channel transistor, providing design flexibility. The MTP memory cell includes only a single transistor, and thus can be used to achieve high-density memory arrays. The MTP memory cell can be programmed / erased by various methods, including CHE, BBHH, and FN tuning, providing additional design options. Furthermore, the MTP memory cell can be fabricated using existing processing procedures, such as a cut-metal gate procedure.

[0182] It should be understood that not all advantages are necessary discussed herein, that not all advantages need necessarily be achieved, that not all examples or embodiments necessarily achieve the same advantages, and that other examples or embodiments can achieve different advantages.

[0183] ​Embodiments of the present disclosure provide a memory cell, including a source region; a drain region; a channel region connecting the source region and the drain region; a first gate dielectric layer disposed on the channel region; a storage gate electrode layer disposed on the first gate dielectric layer; and a second gate electrode layer disposed on the storage gate electrode layer, wherein the second gate electrode layer includes a conductive material; and a second gate dielectric layer disposed between the storage gate electrode layer and the second gate electrode layer. In some embodiments, the storage gate electrode layer includes silicon nitride. In some embodiments, the channel region includes a semiconductor fin having a first sidewall and a second sidewall, and the storage gate electrode layer is disposed over the first sidewall and the second sidewall. In some embodiments, the second gate electrode layer has a first portion and a second portion, the first portion of the second gate electrode layer facing the first sidewall of the channel region, and the second portion of the second gate electrode layer facing the second sidewall of the channel region. In some embodiments, the memory cell further includes a first gate contact feature in contact with the first portion of the second gate electrode layer, a second gate contact feature in contact with the second portion of the second gate electrode layer, and the first gate contact feature and the second gate contact feature are electrically coupled. In some embodiments, the channel region is a p-type channel. In some embodiments, the channel region is an n-type channel. In some embodiments, the channel region includes two or more semiconductor fins.

[0184] Some embodiments of the present disclosure are directed to a method for operating a memory cell, including providing a multi-time programmable memory cell, the memory cell including: a source region; a drain region; a channel region connecting between the source region and the drain region; a storage node formed on the channel region; and a control gate on the storage node; injecting electrons into the storage node by applying a first control voltage to the control gate; and removing electrons from the storage node by applying a second control voltage to the control gate. In some embodiments, the step of injecting electrons into the storage node includes applying a source voltage to the source region and applying a drain voltage to the drain region, wherein the first control voltage is a positive voltage, and the source voltage and the drain voltage are about 0 V. In some embodiments, the step of injecting electrons into the storage node includes applying a source voltage to the source region and applying a drain voltage to the drain region, wherein the first control voltage is a positive voltage, the source voltage is about 0 V, and the drain voltage is a positive voltage. In some embodiments, the step of removing electrons from the storage node includes applying a source voltage to the source region and applying a drain voltage to the drain region, wherein the second control voltage is a negative voltage, and the source voltage and the drain voltage are about 0 V. In some embodiments, the step of removing electrons from the storage node includes applying a source voltage to the source region and applying a drain voltage to the drain region, wherein the second control voltage is a positive voltage, the source voltage and the drain voltage are positive voltages greater than the first voltage.

[0185] Some embodiments of the disclosure are directed to an integrated circuit including an array of memory cells, wherein each memory cell includes a source region; a drain region; a channel region connected between the source region and the drain region; a storage node formed on the channel region; and a control gate over the storage node; a plurality of word lines, wherein each word line is connected to the control gates in one column of memory cells in the array; a bit line connected to the drain regions of one row of memory cells in the array; and a source line connected to the source regions of at least one column of memory cells in the array. In some embodiments, the source line is connected to the source regions of two adjacent columns of memory cells in the array. In some embodiments, two adjacent memory cells in the same row share one contact feature to connect to the bit line. In some embodiments, the source line and the word line extend along a first direction, and the bit line extends along a second direction. In some embodiments, the integrated circuit further includes a bit line select transistor and a source select transistor, wherein the bit line select transistor and the source select transistor are connected in series to one row of memory cells, the bit line is connected to the row of memory cells through the bit line transistor, and the source line is connected to the source regions through the source select transistor. In some embodiments, the source region and the drain region of the memory cell are not in contact with the plurality of conductive features. In some embodiments, the control gate in the memory cell includes two portions disposed on two sides of the storage node and connected to corresponding word lines.

[0186] Some embodiments of the disclosure are directed to a memory cell including a source region, a drain region, a channel region connecting the source region and the drain region, wherein the channel region includes two or more semiconductor fins. The memory cell further includes a first gate dielectric layer disposed on the channel region, a storage gate electrode layer disposed on the first gate dielectric layer, a conductive gate electrode layer disposed on the storage gate electrode layer, and a second gate dielectric layer disposed between the storage gate electrode layer and the conductive gate electrode layer.

[0187] The foregoing outlines features of several embodiments so that a thorough comprehension of the disclosure can be attained. Those skilled in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A memory cell comprising: Comprising: a source region; a drain region; a channel region connecting the source region and the drain region; a first gate dielectric layer disposed on the channel region; a storage gate electrode layer disposed on the first gate dielectric layer; a second gate electrode layer disposed on the storage gate electrode layer; and a second gate dielectric layer disposed between the storage gate electrode layer and the second gate electrode layer.

2. The memory cell of claim 1, wherein, wherein the channel region comprises a semiconductor fin having a first sidewall and a second sidewall, the storage gate electrode layer disposed over the first sidewall and the second sidewall.

3. The memory cell of claim 2, wherein, wherein the second gate electrode layer has a first portion and a second portion, the first portion of the second gate electrode layer facing the first sidewall of the channel region, and the second portion of the second gate electrode layer facing the second sidewall of the channel region.

4. The memory cell of claim 3, wherein, further comprising a first gate contact feature in contact with the first portion of the second gate electrode layer, a second gate contact feature in contact with the second portion of the second gate electrode layer, and the first gate contact feature electrically coupled with the second gate contact feature.

5. A memory cell comprising: Comprising: a source region; a drain region; a channel region connecting the source region and the drain region, wherein the channel region comprises two or more semiconductor fins; a first gate dielectric layer disposed on the channel region; a storage gate electrode layer disposed on the first gate dielectric layer; a conductive gate electrode layer disposed on the storage gate electrode layer; and a second gate dielectric layer disposed between the storage gate electrode layer and the conductive gate electrode layer.

6. An integrated circuit, characterized by Comprising: an array comprising a plurality of memory cells, wherein each of the memory cells comprises: a source region; a drain region; a channel region connected between the source region and the drain region; a storage node formed on the channel region; and a control gate on the storage node; a plurality of word lines, wherein each of the word lines is connected to the plurality of control gates in one column of the plurality of memory cells in the array; a bit line connected to the plurality of drain regions of one row of the plurality of memory cells in the array; and a source line connected to the source regions of at least one column of the plurality of memory cells in the array. wherein the source line is connected to the plurality of source regions of two adjacent columns of the plurality of memory cells in the array. wherein two adjacent ones of the plurality of memory cells in the same row share one contact feature to connect to the bit line.

7. The integrated circuit of claim 6, wherein, wherein the source line and the plurality of word lines extend along a first direction, and the bit line extends along a second direction.

8. The integrated circuit of claim 7, wherein, wherein the control gate in each of the memory cells comprises two portions disposed on two sides of the storage node and connected to a corresponding word line.

9. The integrated circuit of claim 7, wherein, ​ 10. The integrated circuit of claim 6, wherein, ​

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