Display device

Abstract

The display device includes: a substrate defining a display area including pixels and a peripheral area surrounding at least a portion of the display area in a plan view; a first pad portion at one side of the substrate and including a dummy pad; a second pad portion including a test pad electrically connected to the dummy pad; a driving integrated circuit electrically connected to the first pad portion; and a printed circuit board electrically connected to the second pad portion and including a test terminal electrically connected to the test pad, in which the dummy pads include a first dummy pad and a second dummy pad electrically connected to each other, the test pads include a first test pad electrically connected to the first dummy pad, a second test pad electrically connected to the first dummy pad, and a third test pad electrically connected to the second dummy pad, and wherein the test terminals include a 1-1 test terminal and a 1-2 test terminal electrically connected to the first test pad.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2023-0172733, filed on December 1, 2023, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more implementations relate to display devices. Background Technology

[0004] The display device visually displays data. The display device may include a substrate divided into a display area and a peripheral area. In the display area, scan lines and data lines are formed to be insulated from each other and may include multiple pixels. Furthermore, in the display area, thin-film transistors corresponding to each of the multiple pixels and sub-pixel electrodes electrically connected to the thin-film transistors may be disposed. Additionally, opposing electrodes commonly disposed for each pixel may be disposed in the display area. In the peripheral area, various lines, scan drivers, data drivers, controllers, pad portions, etc., configured to send electrical signals to the display area may be disposed.

[0005] Multiple signal pads can be disposed in the pad portion of the display device to connect electrical signals to an external driving device. The driving device may include a chip or film configured to drive the display panel, such as a driver integrated circuit (DIC), flexible printed circuit (FPC) film, etc. Examples of methods for mounting the chip or film as a driving device on the display panel may include the chip-on-glass (COG) method, the chip-on-plastic (COP) method, the film-on-glass (FOG) method, and the film-on-plastic (FOP) method. Contact resistance may occur when the chip or film is attached to the display panel. Utility Model Content

[0006] One or more embodiments include a display device having a structure for reducing the number of pads configured to measure contact resistance. However, this is illustrative and does not limit the scope of this disclosure.

[0007] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description or may be learned by practice of the embodiments presented in this disclosure.

[0008] According to one or more embodiments, a display apparatus includes a substrate defining a display area including pixels and a peripheral area surrounding at least a portion of the display area in a plan view, a first land portion arranged at one side of the substrate and including dummy lands, a second land portion including test lands electrically connected to the dummy lands, a driving integrated circuit electrically connected to the first land portion, and a printed circuit board electrically connected to the second land portion and including test terminals electrically connected to the test lands, wherein the dummy lands include first and second dummy lands electrically connected to each other by an internal connection line in the driving integrated circuit, wherein the test lands include a first test land electrically connected to the first dummy land by a first connection line, a second test land electrically connected to the first dummy land by a second connection line, and a third test land electrically connected to the second dummy land by a third connection line, and wherein the test terminals include a 1-1 test terminal and a 1-2 test terminal electrically connected to the first test land.

[0009] The dummy lands can further include a third dummy land electrically connected to the second dummy land by the internal connection line, wherein the test lands further include a fourth test land electrically connected to the third dummy land by a fourth connection line.

[0010] The internal connection line can be electrically connected to a surface of the first dummy land, a surface of the second dummy land, and a surface of the third dummy land, wherein the first and second connection lines are electrically connected to another surface of the first dummy land, wherein the third connection line is electrically connected to another surface of the second dummy land, and wherein the fourth connection line is electrically connected to another surface of the third dummy land.

[0011] The test terminals can further include a second test terminal electrically connected to the second test land, a third test terminal electrically connected to the third test land, and a fourth test terminal electrically connected to the fourth test land.

[0012] The 1-2 test terminal can be electrically connected to a first node between the 1-1 test terminal and the first test land, wherein the second test terminal is electrically connected to a second node between the first test land and the first dummy land, and wherein the third test terminal is electrically connected to a third node between the first dummy land and the third dummy land.

[0013] The dummy lands can further include a third dummy land electrically connected to the second dummy land by the internal connection line, wherein the test lands further include a fourth test land electrically connected to the second dummy land by a fourth connection line and a fifth test land electrically connected to the third dummy land by a fifth connection line.

[0014] The internal connection lines can be electrically connected to a surface of the first dummy pad, a surface of the second dummy pad, and a surface of the third dummy pad, wherein the first connection line and the second connection line are electrically connected to another surface of the first dummy pad, wherein the third connection line and the fourth connection line are electrically connected to another surface of the second dummy pad, and wherein the fifth connection line is electrically connected to another surface of the third dummy pad.

[0015] The test terminals can further include a second test terminal electrically connected to the second test pad, a third test terminal electrically connected to the third test pad, a fourth test terminal electrically connected to the fourth test pad, and a fifth test terminal electrically connected to the fifth test pad.

[0016] The second test terminal can be connected to a fourth node between the first test pad and the second test pad, wherein the 1-2 test terminal is connected to a fifth node between the 1-1 test terminal and the first test pad.

[0017] The fifth test terminal can be connected to a sixth node between the first dummy pad and the second dummy pad, wherein the fourth test terminal is connected to a seventh node between the second dummy pad and the third test terminal.

[0018] The dummy pads can be insulated from the pixels.

[0019] The first pad portion can include a first signal pad electrically connected to the pixel, wherein the second pad portion includes a plurality of second signal pads electrically connected to the first signal pad.

[0020] The driving integrated circuit can include contact pads corresponding to the dummy pads, respectively.

[0021] A bending axis can be defined between the first pad portion and the pixel, wherein the display apparatus is bent with respect to the bending axis.

[0022] According to one or more embodiments, a display apparatus includes: a pixel; a first pad portion including dummy pads insulated from the pixel; a second pad portion including test pads electrically connected to the dummy pads; a driving integrated circuit electrically connected to the first pad portion; and a printed circuit board electrically connected to the second pad portion and including test terminals electrically connected to the test pads, wherein the dummy pads include first, second, and third dummy pads electrically connected to each other by internal connection lines in the driving integrated circuit, wherein the test pads include first and second test pads electrically connected to the first dummy pad, a third test pad electrically connected to the second dummy pad, and a fourth test pad electrically connected to the third dummy pad, and wherein the test terminals include a 1-1 test terminal connected to the first test pad, a 1-2 test terminal connected to a first node between the 1-1 test terminal and the first test pad, a second test terminal connected to a second node between the first test pad and the first dummy pad, and a third test terminal connected to a third node between the first dummy pad and the third dummy pad.

[0023] The display apparatus can further include: a first connection line connecting the first test pad to the first dummy pad; a second connection line connecting the second test pad to the first dummy pad; a third connection line connecting the third test pad to the second dummy pad; and a fourth connection line connecting the fourth test pad to the third dummy pad.

[0024] The internal connection lines are integrally located on a surface of the first dummy pad, a surface of the second dummy pad, and a surface of the third dummy pad, wherein the first and second connection lines are electrically connected to another surface of the first dummy pad, wherein the third connection line is electrically connected to another surface of the second dummy pad, and wherein the fourth connection line is electrically connected to another surface of the third dummy pad.

[0025] The driving integrated circuit can be mounted on the first pad portion by a chip on glass (COG) method or a chip on plastic (COP) method.

[0026] The printed circuit board can be mounted on the second pad portion by a film on glass (FOG) method or a film on plastic (FOP) method.

[0027] The first pad portion can include a first signal pad electrically connected to the pixel, and the second pad portion can include a second signal pad electrically connected to the first signal pad. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above and other aspects of embodiments of the disclosure will become more apparent by describing in detail embodiments thereof with reference to the accompanying drawings, in which:

[0029] Figure 1is a schematic plan view of a display device according to one or more embodiments;

[0030] Figure 2 is a schematic cross-sectional view of a display area of a display device according to one or more embodiments;

[0031] Figure 3 shows a first pad of a first pad portion according to one or more embodiments;

[0032] Figure 4 shows a second pad of a second pad portion according to one or more embodiments;

[0033] Figure 5 is a schematic cross-sectional view of a display device according to one or more embodiments; Figure 1 Figure 1

[0034] Figure 6 is a perspective view of a connection structure of a test terminal, dummy pad and test pad according to one or more embodiments;

[0035] Figure 7 is a perspective view for describing a method of measuring a contact resistance in a connection structure of Figure 6

[0036] Figure 8 is a schematic circuit diagram for describing a method of measuring a contact resistance of a display device according to one or more embodiments;

[0037] Figure 9A is a perspective view for describing a method of measuring a contact resistance according to a comparative example;

[0038] Figure 9B and Figure 9C is a schematic circuit diagram for describing a method of measuring a contact resistance according to one or more comparative examples corresponding to Figure 9A

[0039] Figure 10 is a perspective view of a connection structure of a test terminal, dummy pad and test pad according to one or more embodiments; and

[0040] Figure 11A and Figure 11B is a perspective view for describing a method of measuring a contact resistance in a connection structure of Figure 10 DETAILED DESCRIPTION

[0041] ​​​​​Aspects of some implementations of the present disclosure, as well as methods implementing them, can be more readily understood by reference to the following detailed description, taken with the accompanying drawings. The described implementations are provided as examples, so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are redundant, or that are not directly related to the description of the implementations, or that are well known in the art can be omitted in order to more clearly describe the aspects of the present disclosure. Unless otherwise noted, like reference characters, numerals, or combinations thereof, throughout the drawings and written description, indicate like elements, and thus, a repeated description of these elements can be omitted.

[0042] The described implementations can have various modifications and can be implemented in different forms, and should not be construed as being limited to the implementations set forth herein. "Possibly", "may" or "may not" used in describing the implementations corresponds to one or more implementations of the present disclosure. The present disclosure encompasses all modifications, equivalents, and alternatives falling within the scope of the idea and technical scope of the present disclosure. Furthermore, each of the features of the various implementations of the present disclosure can be combined partially or entirely with each other, and various interlocks and drives are technically possible. Each implementation can be implemented independently of each other, or can be implemented together in association.

[0043] In the drawings, the relative sizes of elements, layers, and regions can be exaggerated for clarity and / or descriptive purposes. Also, the use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries, regions, layers, and / or elements. Accordingly, unless specifically stated otherwise, the presence of cross-hatching or shading in a drawing, or the absence thereof, does not indicate or imply any preference or requirement for particular material, material properties, dimensions, ratios, commonality of elements between illustrations, and / or any other characteristic, attribute, property, or the like of the elements being portrayed.

[0044] Various implementations are described herein with reference to cross-sectional illustrations that are schematic representations of schematics embodiments and / or intermediate structures of implementations. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Additionally, the particular structural and functional configurations shown in the illustrations herein are illustrative only and are not meant to be restrictive in any way. Thus, the implementations disclosed herein are not to be limited to the particular shapes of elements as illustrated nor to the particular structural configurations, arrangements, and / or methodologies set forth in the illustrations.

[0045] For example, an implant region shown as rectangular will generally have rounded or curved features at its edges and / or a gradient of implant concentration, rather than a binary change from the implant region to the non-implant region. Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which implantation occurred.

[0046] For purposes of explanation, spatial relative terms, such as "below," "beneath," "lower," "bottom," "under," "above," "upper," "top," and the like, can be used herein for purposes of explanation to describe one element or feature's relationship to another element(s) or feature(s) as shown in the figures. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatial relative descriptors used herein interpreted accordingly. Similarly, when a first part is described as being "on" a second part, it indicates that the first part is disposed on the upper side or lower side of the second part, without regard to a gravity- based orientation of the second part.

[0047] Further, the phrase "in plan view" means when viewing the object part from above, and the phrase "in schematic cross-sectional view" means when viewing a schematic cross-section of the object part obtained by cutting the object part vertically from the side. The term "overlapping" or "overlap" means that a first object can be above or below or to the side of a second object, and that a second object can be above or below or to the side of a first object. Additionally, the term "overlapping" can include stacking, facing or facing towards, extending over, covering or partially covering, or any other suitable term as would be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" can include the meaning of "separated from" or "offset from" or "offset from" or any other suitable equivalent as would be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "facing towards" can mean that a first object can be directly or indirectly opposite a second object. In case a third object is interposed between the first object and the second object, the first object and the second object can be understood as indirectly opposite each other, but still facing each other.

[0048] It will be understood that when an element, layer, region or component is referred to as being "formed on" or "formed over" another element, layer, region or component, it can be directly or indirectly formed on or over the other element, layer, region or component, and that there can be one or more intervening elements, layers, regions or components present. In addition, it can be generally intended that the connection or coupling or connection or coupling be direct or indirect and that the connection or coupling be integral or non-integral. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or directly electrically coupled to the other layer, region and / or component, or there can be one or more intervening layers, regions or components. The one or more intervening components can include switches, resistors, capacitors, etc. In describing implementations, expressions of connection indicate electrical connections, and "directly connected / directly coupled" or "directly on" mean that one component is connected or coupled to or directly on another component without intervening components, unless expressly described otherwise.

[0049] Further, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the direction of formation is not limited to the upward direction, but includes formation of the part on a side surface or in a downward direction. Conversely, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is yet another part between the part and the other part. Meanwhile, other expressions describing the relationship between components, such as "between", "directly between", or "adjacent to" and "directly adjacent to", can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can be one or more intervening elements or layers.

[0050] For purposes of this disclosure, expressions such as “at least one of,” “one or more of,” “at least one,” “one or more,” and “at least one of the following” are used to describe existing aspects of the application. These expressions are not used to limit the description of the application in some way only to include one of the following features or set of features, nor should they be construed along those lines. Rather, these expressions are used to provide one or more features from a set of one or more features to describe various embodiments. For example, the expression “at least one of X, Y, and Z” and “at least one of the following items: X, Y, and Z” can be interpreted to be one or more of X, Y, and Z. Similarly, the expression “one or more of X, Y, and Z” can be interpreted to be one or more of X, Y, and Z. As used herein, “or” is generally employed in its sense including at least one of the items from the list of items, and the term “and / or” includes all combinations of one or more of the associated listed items. For example, the expression “A and / or B” can include A, B, or A and B. Similarly, when used in the context of a list of items should be interpreted to be one or more of the items in the list rather than the individual items.

[0051] It will be understood that, although the terms “first,” “second,” “third,” etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, section or part from another element, component, region, layer, section or part. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure. The use of the term “first” to describe an element, component, region, layer or section can not require or imply the presence of a second element, component, region, layer or section. The terms “first,” “second,” etc. can also be used herein to distinguish different categories or different groups of elements. For the sake of brevity, the terms “first,” “second,” etc. can be used herein to designate the “first category (or first group)” and the “second category (or second group),” respectively, as opposed to “first” and “second” categories (or groups).

[0052] In examples, the x-axis, the y-axis, and / or the z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0053] The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "has", "having", "includes" and "including" when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0054] As used herein, the terms "substantially", "approximately", "about", and like terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. For example, "substantially" can include a range of + / - 5% of a recited value. In view of the discussed measurement and the error associated with measuring a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately," as used herein includes the recited value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within + / - 30%, + / - 20%, + / - 10%, + / - 5% of the recited value. Additionally, "may" as used in describing embodiments of the present disclosure indicates "one or more embodiments of the present disclosure."

[0055] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0056] Figure 1 is a schematic plan view of a display apparatus according to one or more embodiments.

[0057] Referring to Figure 1 The display apparatus 1 can include a display panel 10. According to one or more embodiments, the display apparatus 1 can include an organic light emitting display apparatus. According to one or more other embodiments, the display apparatus 1 can include a liquid crystal display, a field emission display (FED), or an electronic paper display.

[0058] A display area DA for displaying an image and a peripheral area PA extending outside the display area DA (e.g., in a plan view) can be arranged in the substrate 100. The display area DA can include a plurality of pixels PX each including a light emitting diode (e.g., an organic light emitting diode) electrically connected to a thin film transistor. The pixels PX can be connected to gate lines GL arranged on the display panel 10 to extend in a first direction (e.g., an x direction), and can be connected to data lines DL arranged on the display panel 10 to cross the gate lines GL and extend in a second direction (e.g., a y direction).

[0059] The pixels PX can include red pixels for emitting red light, green pixels for emitting green light, and blue pixels for emitting blue light. However, according to one or more embodiments, the pixels PX are not limited to the pixels emitting red light, blue light, and green light, and can include pixels for emitting white light or light of other colors. The pixels PX can include pixel circuits and light emitting devices connected to the pixel circuits and emitting light. The pixel circuits can include at least one thin film transistor and at least one capacitor.

[0060] The peripheral area PA can be an area in which the plurality of pixels PX are not arranged, and can surround the display area DA (e.g., in a plan view). The peripheral area PA can include a bending area in which the display panel 10 can be bent in one direction, and a pad area extending outside the bending area.

[0061] The bending area can include a bending axis BX defined between the first pad portion PDA1 and the display area DA. The display panel 10 can be bent in one direction with respect to the bending axis BX.

[0062] The pad area can include the first pad portion PDA1 and the second pad portion PDA2. The first pad portion PDA1 can include a plurality of first pads PD1. The second pad portion PDA2 can include a plurality of second pads PD2. The first pad portion PDA1 and the second pad portion PDA2 can be arranged in the peripheral area PA toward one side of the display area DA. For example, as shown in FIG. 1A, the first pad portion PDA1 and the second pad portion PDA2 can be arranged adjacent to one side (e.g., a bottom side in a plan view) of the display area DA. Figure 1

[0063] ​The driving integrated circuit 30 can be located on the first pad portion PDA1. The display panel 10 can include a plurality of signal lines SL connected to the first pad portion PDA1, and can transmit a signal of the driving integrated circuit 30 to the pixels PX. The signal lines SL can include gate lines GL and data lines DL. The driving integrated circuit 30 can be configured to generate scan signals and data signals in response to a driving power and externally provided signals, and can provide the scan signals and the data signals to the gate lines GL and the data lines DL, respectively. To this end, the driving integrated circuit 30 can include one or more scan drivers configured to generate the scan signals and one or more data drivers configured to generate the data signals.

[0064] The driving integrated circuit 30 can be mounted on the first pad portion PDA1 by a chip on glass (COG) method or a chip on plastic (COP) method. The driving integrated circuit 30 can include contact pads (e.g., bumps, conductive balls, conductive pins, etc.) that can be connected to the first pads PD1 of the first pad portion PDA1. The contact pads PD_30 of the driving integrated circuit 30 can be disposed in one-to-one correspondence with the first pads PD1 of the first pad portion PDA1. When the first pads PD1 and the contact pads PD_30 are coupled to each other, the first pad portion PDA1 and the driving integrated circuit 30 can be connected to each other, and a contact resistance (or COG / COP resistance) can occur due to such coupling. Figure 5 ) can be disposed in one-to-one correspondence with the first pads PD1 of the first pad portion PDA1. When the first pads PD1 and the contact pads PD_30 are coupled to each other, the first pad portion PDA1 and the driving integrated circuit 30 can be connected to each other, and a contact resistance (or COG / COP resistance) can occur due to such coupling.

[0065] The printed circuit board 50 can be located on the second pad portion PDA2. The printed circuit board 50 can include a flexible printed circuit (FPC) film. The printed circuit board 50 can be configured to generate various control signals by receiving driving signals from an external driving circuit, and can drive the pixels PX and / or the driving integrated circuit 30 according to the control signals.

[0066] The printed circuit board 50 can be mounted on the second pad portion PDA2 by a film on glass (FOG) method or a film on plastic (FOP) method. The printed circuit board 50 can include contact pads (e.g., bumps, conductive balls, conductive pins, etc.) that can be connected to the second pads PD2 of the second pad portion PDA2. The contact pads of the printed circuit board 50 can be disposed in one-to-one correspondence with the second pads PD2 of the second pad portion PDA2. When the second pads PD2 and the contact pads are coupled to each other, the second pad portion PDA2 and the printed circuit board 50 can be connected to each other, and a contact resistance (or FOG / FOP resistance) can occur due to such coupling.

[0067] Figure 1Embodiments in which the driving integrated circuit 30 and the printed circuit board 50 are disposed separately from each other are shown. However, the driving integrated circuit 30 can be formed in the printed circuit board 50, and the printed circuit board 50 including the driving integrated circuit 30 can be mounted on the display panel 10.

[0068] Figure 2 is a schematic cross-sectional view of a display area of a display apparatus according to one or more embodiments.

[0069] Referring to Figure 2 , the display panel 10 can include a substrate 100, a buffer layer 111, a pixel circuit layer PCL, a display element layer DEL, and a thin film encapsulation layer TFE. The display panel 10 can include a substrate 100 including a plurality of pixels, a pixel circuit layer PCL in which thin film transistors TFT are arranged, a display element layer DEL in which organic light emitting diodes OLED are arranged, and a thin film encapsulation layer TFE covering the organic light emitting diodes OLED. The pixel circuit layer PCL and the display element layer DEL can be located on the substrate 100, and the thin film encapsulation layer TFE can be located on the display element layer DEL. The pixel circuit layer PCL and the display element layer DEL can be arranged in a display area DA, and the thin film encapsulation layer TFE can cover the display area DA. In one or more embodiments, a functional film such as a polarizing layer, a touch sensing unit, a cover window, etc. can be located on the thin film encapsulation layer TFE.

[0070] The buffer layer 111 can include an inorganic insulating material such as SiN x , SiON, and SiO2, and can include a single layer or a plurality of layers including the above-described inorganic insulating material.

[0071] The pixel circuit layer PCL can be located on the buffer layer 111. The pixel circuit layer PCL can include thin film transistors TFT included in a pixel circuit PC, and can further include an inorganic insulating layer IIL, a first planarization layer 115, and a second planarization layer 116 arranged below and / or above elements of the thin film transistors TFT. The inorganic insulating layer IIL can include a first gate insulating layer 112, a second gate insulating layer 113, and an interlayer insulating layer 114.

[0072] The thin film transistor TFT can include a semiconductor layer Act, and the semiconductor layer Act can include polysilicon. Alternatively, the semiconductor layer Act can include amorphous silicon, an oxide semiconductor, or an organic semiconductor. The semiconductor layer Act can include a channel region, a drain region and a source region arranged at both sides of the channel region, respectively. A gate electrode GE can overlap the channel region.

[0073] The gate electrode GE can include a low-resistance metal material. The gate electrode GE can include a conductive material including Mo, Al, Cu, Ti, etc., and can include a single layer or multiple layers including the above-described conductive material.

[0074] The first gate insulating layer 112 between the semiconductor layer Act and the gate electrode GE can include an inorganic insulating material such as SiO x , SiN x , SiON, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide.

[0075] The second gate insulating layer 113 can be disposed to cover the gate electrode GE. Like the first gate insulating layer 112, the second gate insulating layer 113 can include an inorganic insulating material such as SiO x , SiN x , SiON, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide.

[0076] The upper electrode CE2 of the storage capacitor Cst can be located above the second gate insulating layer 113. The upper electrode CE2 can overlap the gate electrode GE thereunder. Here, the gate electrode GE and the upper electrode CE2, which overlap each other with the second gate insulating layer 113 therebetween, can form the storage capacitor Cst of the pixel circuit PC. That is, the gate electrode GE can serve as a lower electrode CE1 of the storage capacitor Cst.

[0077] As described above, the storage capacitor Cst and the thin film transistor TFT can be formed to overlap each other. According to some embodiments, the storage capacitor Cst can be formed not to overlap the thin film transistor TFT.

[0078] The upper electrode CE2 can include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W, and / or Cu, and can include a single layer or multiple layers including the above-described material.

[0079] The interlayer insulating layer 114 can cover the upper electrode CE2. The interlayer insulating layer 114 can include SiO x , SiN x , SiON, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zinc oxide. The interlayer insulating layer 114 can include a single layer or multiple layers including the above-described inorganic insulating material.

[0080] Each of the drain electrode DE and the source electrode SE can be located on the interlayer insulating layer 114. The drain electrode DE and the source electrode SE can include a highly conductive material. The drain electrode DE and the source electrode SE can include a conductive material including Mo, Al, Cu, Ti, or the like, and can include a multi-layer or a single layer including the above-described material. According to one or more embodiments, the drain electrode DE and the source electrode SE can have a multi-layer structure of Ti / Al / Ti.

[0081] The first planarization layer 115 can be disposed to cover the drain electrode DE and the source electrode SE. The first planarization layer 115 can include an organic insulating layer. The first planarization layer 115 can include an organic insulating material such as a general-purpose polymer (e.g., polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenolic group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

[0082] The first connection electrode CML1 can be disposed on the first planarization layer 115. Here, the first connection electrode CML1 can be connected to the drain electrode DE or the source electrode SE through a contact hole of the first planarization layer 115. The first connection electrode CML1 can include a highly conductive material. The first connection electrode CML1 can include a conductive material including Mo, Al, Cu, Ti, or the like, and can include a multi-layer or a single layer including the above-described conductive material. According to one or more embodiments, the first connection electrode CML1 can have a multi-layer structure of Ti / Al / Ti.

[0083] The second planarization layer 116 can cover the first connection electrode CML1. The second planarization layer 116 can include an organic insulating layer. The second planarization layer 116 can include an organic insulating material such as a general-purpose polymer (e.g., PMMA or PS), a polymer derivative having a phenolic group, an acryl-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

[0084] The display element layer DEL can be located on the pixel circuit layer PCL. The display element layer DEL can include an organic light emitting diode OLED, and a pixel electrode 211 of the organic light emitting diode OLED can be electrically connected to the first connection electrode CML1 through a contact hole of the second planarization layer 116.

[0085] The pixel electrode 211 can include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). According to one or more other embodiments, the pixel electrode 211 can include a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof. According to one or more other embodiments, the pixel electrode 211 can further include a layer including ITO, IZO, ZnO, or In2O3 above / below the reflective layer.

[0086] A bank layer (e.g., a pixel defining layer) 118 defining an opening 118OP of a central portion of the pixel electrode 211 can be located on the pixel electrode 211. The bank layer 118 can include an organic insulating material and / or an inorganic insulating material. The opening 118OP can define an emission area (hereinafter referred to as an emission area EA) from which light is emitted from the organic light emitting diode OLED. For example, a width of the opening 118OP can correspond to a width of the emission area EA.

[0087] A spacer 119 can be located on the bank layer 118. The spacer 119 can be disposed to reduce or prevent a possibility of the substrate 100 being broken when the display apparatus is manufactured. In a manufacturing process of the display panel 10, a mask sheet can be used. Here, because the mask sheet can be inserted into the opening 118OP of the bank layer 118 or can be adhered to the bank layer 118, a possibility of damage or breakage of a portion of the substrate 100 caused by the mask sheet when a material is deposited on the substrate 100 can be reduced or prevented.

[0088] The spacer 119 can include an organic insulating material such as polyimide. Alternatively, the spacer 119 can include an inorganic insulating material such as SiN x or SiO2, or can include an organic insulating material and an inorganic insulating material.

[0089] According to one or more embodiments, the spacer 119 can include a material different from a material of the bank layer 118. Alternatively, according to one or more other embodiments, the spacer 119 can include the same material as the material of the bank layer 118, and in this case, the bank layer 118 and the spacer 119 can be formed together through a mask process using a half-tone mask or the like.

[0090] An intermediate layer 212 can be located on the bank layer 118. The intermediate layer 212 can include an emission layer 212b disposed in the opening 118OP of the bank layer 118. The emission layer 212b can include a high molecular weight organic material or a low molecular weight organic material that emits light of a predetermined color.

[0091] The first functional layer 212a and the second functional layer 212c can be disposed below and above the emission layer 212b, respectively. The first functional layer 212a can include, for example, a hole transport layer (HTL), or include an HTL and a hole injection layer (HIL). The second functional layer 212c can be disposed above the emission layer 212b, and can be optionally disposed. The second functional layer 212c can include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first functional layer 212a and / or the second functional layer 212c can be a common layer(s) formed to completely cover the substrate 100, as a counter electrode 213 to be described below.

[0092] The counter electrode 213 can include a conductive material having a low work function. For example, the counter electrode 213 can include a (semi-)transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. Optionally, the counter electrode 213 can further include a layer including ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer including the above-described material.

[0093] According to some embodiments, a capping layer can be further disposed on the counter electrode 213. The capping layer can include LiF, an inorganic material, or / and an organic material.

[0094] A thin film encapsulation layer TFE can be located on the counter electrode 213. According to one or more embodiments, the thin film encapsulation layer TFE can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 2 It is shown that the thin film encapsulation layer TFE can include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330, which are sequentially stacked.

[0095] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can include at least one inorganic material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, ZnO, SiO x , SiN x , and SiON. The organic encapsulation layer 320 can include a polymer-based material. The polymer-based material can include an acryl-based resin, an epoxy-based resin, polyimide, polyethylene, etc. According to one or more embodiments, the organic encapsulation layer 320 can include an acrylate.

[0096] In one or more embodiments, a touch electrode layer can be disposed on a thin film encapsulation layer TFE, and an optical functional layer can be disposed on the touch electrode layer. The touch electrode layer can obtain coordinate information based on an external input such as a touch event. The optical functional layer can reduce reflectance of external light incident from the outside toward the display apparatus, and / or can improve color purity of light emitted from the display apparatus. According to one or more embodiments, the optical functional layer can include a phase retarder and a polarizer. The phase retarder can include a film type phase retarder or a liquid crystal coating type phase retarder, and can include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer can also include a film type polarizer or a liquid crystal coating type polarizer. The film type polarizer can include a stretched synthetic resin film, and the liquid crystal coating type polarizer can include liquid crystals disposed in a specific shape. The phase retarder and the polarizer can also include a protective film.

[0097] According to one or more other embodiments, the optical functional layer can include a black matrix and a color filter. The color filter can be disposed by considering colors of light emitted from each of the pixels of the display apparatus. Each of the color filters can include a red, green, or blue pigment or dye. Alternatively, each of the color filters can include a quantum dot in addition to the above-described pigments or dyes. Alternatively, some of the color filters can not include the above-described pigments or dyes, and can include scattering particles such as titanium oxide.

[0098] According to one or more other embodiments, the optical functional layer can include a destructive interference structure. The destructive interference structure can include a first reflection layer and a second reflection layer disposed on different layers from each other. First reflected light and second reflected light respectively reflected from the first reflection layer and the second reflection layer can destructively interfere, and thus, can reduce reflectance of external light.

[0099] A bonding member can be disposed between the touch electrode layer and the optical functional layer. The bonding member can not be limited to a specific type, and can be implemented as a general member known in the art. The bonding member can include a pressure sensitive adhesive (PSA).

[0100] Figure 3 A first pad of the first pad portion is shown according to one or more embodiments, and Figure 4 A second pad of the second pad portion is shown according to one or more embodiments.

[0101] Reference Figure 3 The first pad portion PDA1 can include a plurality of first pads PD1. The first pads PD1 can include a first signal pad PD1_S and a plurality of dummy pads DP.

[0102] The first signal pad PD1_S can be electrically connected to the pixel PX (see Figure 1The first signal pad PD1_S can be electrically connected to the signal line SL (see...). Figure 1 ), and can be directed to pixel PX (see Figure 1 Send from driver integrated circuit 30 (see...) Figure 1 The received signal. The first signal pad PD1_S can be directly connected to pixel PX (see...). Figure 1 Alternatively, it can be achieved by driving integrated circuit 30 (see...) Figure 1 ) Connected to pixel PX (see Figure 1 ).

[0103] The dummy pad DP can be configured to measure contact resistance. The dummy pad DP can be used with the pixel PX (see [link]). Figure 1 Insulation. Dummy pad DP can be left unconnected to signal line SL (see...). Figure 1 According to one or more other embodiments, dummy gate lines or dummy data lines may be formed on the display panel 10 (see [reference]). Figure 1 In the dummy pad DP, the dummy pad DP can be connected to a dummy gate line or a dummy data line. According to one or more other embodiments, the dummy pad DP can be connected to the display panel 10 (see [link to other embodiments]). Figure 1 ) signal line SL (see Figure 1 The switch can be set on the signal line SL connected to the dummy pad DP (see [link]). Figure 3 )middle.

[0104] The first signal pad PD1_S and the dummy pad DP can be formed using the same process. The first signal pad PD1_S and the dummy pad DP can include conductive materials. For example, the first signal pad PD1_S and the dummy pad DP can include transparent electrodes such as indium tin oxide (ITO).

[0105] Figure 3 The diagram shows a dummy pad DP positioned on one side of the first pad portion PDA1. However, the dummy pad DP is not limited to this and can be positioned at multiple different locations. For example, the dummy pad DP can be positioned between the first signal pads PD1_S. Furthermore,

[0106] Figure 4 The example shows three dummy pads (DP). However, the number of dummy pads (DP) is not limited to this, and can vary.

[0107] refer to Figure 1 The second pad portion PDA2 may include multiple second pads PD2. The second pads PD2 may include a second signal pad PD2_S and multiple test pads TP.

[0108] The second signal pad PD2_S can be electrically connected to the first signal pad PD1_S, and the test pad TP can be electrically connected to the dummy pad DP. The second signal pad PD2_S can transmit a signal transmitted from the printed circuit board 50 (see Figure 4 ) to the first signal pad PD1_S. The test pad TP can be used with the dummy pad DP to measure contact resistance.

[0109] The second signal pad PD2_S and the test pad TP can be formed by the same process. The second signal pad PD2_S and the test pad TP can include a conductive material.

[0110] Figure 4 It is shown that the test pad TP is disposed at one side of the second pad portion PDA2. However, the test pad TP is not limited thereto, and can be disposed at a different position. For example, the test pad TP can be disposed between the second signal pads PD2_S. Also, Figure 5 It is shown that four test pads TP are provided. However, the test pad TP is not limited thereto, and the number of test pads TP can vary.

[0111] According to one or more embodiments, the test dummy pad and the test test pad, which are contact resistance test objects, can be connected in series to each other, and a voltage of a node between the test dummy pad and the test test pad can be measured. Accordingly, contact resistance can be measured by using a reduced number of test pads TP. Detailed aspects will be described below.

[0112] Figure 1 is a schematic cross-sectional view of a display device of Figure 5 , taken along line II_II', and schematically shows a connection portion of the first pad PD1 and the driving integrated circuit 30. The first pad PD1 can be the first signal pad PD1_S or the dummy pad DP.

[0113] Referring to Figure 6 , the first pad PD1 can be located on the substrate 100 of the display panel 10. The driving integrated circuit 30 can include a base member SUB_30 and contact pads PD_30 below the base member SUB_30. One or more of the contact pads PD_30 can be short-circuited. One or more of the contact pads PD_30 can be connected to each other by an internal connection line ICL (see Figure 1 ) provided in the driving integrated circuit 30.

[0114] The first pad PD1 can be bonded to the driving integrated circuit 30 by a conductive adhesive film ACF. The first pad PD1 can be bonded to the contact pads PD_30 of the driving integrated circuit 30. The conductive adhesive film ACF can include an anisotropic conductive film.

[0115] The conductive adhesive film ACF can include a plurality of conductive balls BL and an insulating bonding member RN. Each of the plurality of conductive balls BL can include a conductive particle. The conductive particle can be conductive and can include a particle having conductivity such as a metal or a metal oxide, or can include a particle having a core including an insulating material and having a surface coated with a metal or a metal oxide. The metal can include Ni, Fe, Cu, Al, Sn, Zn, Cr, Co, Ag, or Au. The insulating bonding member RN can include an insulating polymer. The insulating polymer can include, for example, an epoxy resin, an acrylic resin, or the like. The epoxy resin has a repeating structure of bisphenol A and an ether (-C-O-C-) bond and can consist of a phenoxy polymer having an epoxy-reactive group at an end portion. The acrylic resin has an urethane bond (-NHCO-O) connecting structure and can consist of a urethane (meta)acrylate polymer having an acrylate or methacrylate reactive group at an end portion.

[0116] A contact resistance can be generated due to the coupling of the first pad PD1, the conductive ball BL, and the contact pad PD_30 of the driving integrated circuit 30. According to a method of mounting the driving integrated circuit 30 on the display panel 10, the contact resistance can be a COG resistance or a COP resistance (hereinafter referred to as a COG / COP resistance).

[0117] In one or more embodiments, the printed circuit board 50 (see Figure 1 ) can also include a base member and a contact pad under the base member, and the contact pad of the printed circuit board 50 (see Figure 1 ) can be bonded to the second pad PD2 (see Figure 1 ) through the conductive adhesive film ACF. A contact resistance can be generated due to the coupling of the second pad PD2 (see Figure 1 ), the conductive ball BL, and the contact pad of the printed circuit board 50 (see Figure 1 ). According to a method of mounting the printed circuit board 50 (see Figure 6 ) on the display panel 10, the contact resistance can be a FOG resistance or a FOP resistance (hereinafter referred to as a FOG / FOP resistance).

[0118] The COG / COP resistance in the pad portion generated due to the coupling of the driving integrated circuit 30 and the FOG / FOP resistance in the pad portion generated due to the coupling of the printed circuit board 50 can affect the performance of the display apparatus 1, and thus, a test of measuring the contact resistance can be required.

[0119] Figure 6 is a perspective view of a connection structure of a test terminal, a dummy pad, and a test pad configured to measure a contact resistance according to one or more embodiments.

[0120] In order to drive the visibility of the contact portion between the integrated circuit 30 and the display panel and the visibility of the contact portion between the printed circuit board 50 and the display panel, Figure 1 It is shown that the driving integrated circuit 30 is bonded above the display panel, and the printed circuit board 50 is bonded below the display panel. However, the printed circuit board 50 can be bonded on the same surface on which the driving integrated circuit 30 can be bonded. That is, as Figure 6 It is shown that the driving integrated circuit 30 and the printed circuit board 50 can be bonded on one surface of the display panel 10.

[0121] Figure 6 It is shown that the internal connection line ICL provided in the driving integrated circuit 30, the plurality of test terminals and the terminal line DT_L provided in the printed circuit board 50, the plurality of connection lines provided in the display panel, the dummy pads, and the test pads. For ease of explanation, Figure 5 It is shown that the dummy pads and the driving integrated circuit 30 are in direct contact with each other, and the test pads and the printed circuit board 50 are in direct contact with each other. However, in one or more embodiments, the contact pads PD_30 (see Figure 6 ) of the driving integrated circuit 30 can be located between the dummy pads and the driving integrated circuit 30, and the contact pads of the printed circuit board 50 can be located between the test pads and the printed circuit board 50.

[0122] Referring to Figure 1 , the first pad portion PDA1 can include a first dummy pad DP1, a second dummy pad DP2, and a third dummy pad DP3. The first dummy pad DP1, the second dummy pad DP2, and the third dummy pad DP3 can be arranged to be separated from each other. The first dummy pad DP1, the second dummy pad DP2, and the third dummy pad DP3 can be electrically connected to each other.

[0123] The second pad portion PDA2 can include a first test pad TP1, a second test pad TP2, a third test pad TP3, and a fourth test pad TP4. The first test pad TP1, the second test pad TP2, the third test pad TP3, and the fourth test pad TP4 can be arranged to be separated from each other.

[0124] The display panel can include a plurality of connection lines connecting the test pads and the dummy pads to each other. The plurality of connection lines can include a first connection line CL1 connecting the first test pad TP1 to the first dummy pad DP1, a second connection line CL2 connecting the second test pad TP2 to the first dummy pad DP1, a third connection line CL3 connecting the third test pad TP3 to the second dummy pad DP2, and a fourth connection line CL4 connecting the fourth test pad TP4 to the third dummy pad DP3.

[0125] The first connection line CL1, the second connection line CL2, the third connection line CL3, and the fourth connection line CL4 can be formed on the same layer on the substrate 100 (see Figure 1 ) of the display panel. The first connection line CL1, the second connection line CL2, the third connection line CL3, and the fourth connection line CL4 can be formed in synchronization with or substantially at the same time as each other. The first connection line CL1 and the second connection line CL2 can be integrally formed with each other.

[0126] The driving integrated circuit 30 can be mounted on the first pad portion PDA1. The driving integrated circuit 30 can be bonded to the first pad portion PDA1, and the contact pads of the driving integrated circuit 30 correspond to the dummy pads of the display panel on a one-to-one basis.

[0127] The driving integrated circuit 30 can include internal connection lines ICL. The internal connection lines ICL can be provided in the driving integrated circuit 30 to connect the contact pads of the driving integrated circuit 30 to each other. Accordingly, the internal connection lines ICL can electrically connect the dummy pads to each other. Through the internal connection lines ICL, the first dummy pad DP1, the second dummy pad DP2, and the third dummy pad DP3 can be electrically connected to each other.

[0128] The substrate 100 (see Figure 7 ) can be located on a surface of the first dummy pad DP1, the second dummy pad DP2, and the third dummy pad DP3, and the driving integrated circuit 30 can be located on the other surface thereof. The first connection line CL1 and / or the second connection line CL2 can be located on (e.g., can contact) a surface of the first dummy pad DP1, and the internal connection line ICL can be located on the other surface of the first dummy pad DP1. The third connection line CL3 can be located on (e.g., can contact) a surface of the second dummy pad DP2, and the internal connection line ICL can be located on the other surface of the second dummy pad DP2. The fourth connection line CL4 can be located on (e.g., can contact) a surface of the third dummy pad DP3, and the internal connection line ICL can be located on the other surface of the third dummy pad DP3. In this document, that an element A is located on a surface of an element B can mean not only that the element A is directly located on the surface of the element B, but also that an element C is located on the surface of the element B while the element A is located on the element C.

[0129] Printed circuit board 50 can be mounted on the second pad portion of PDA2. Printed circuit board 50 can be bonded to the second pad portion of PDA2, and the contact pads of printed circuit board 50 correspond one-to-one with the test pads of the display panel. Printed circuit board 50 may include multiple test terminals and terminal lines DT_L connecting the multiple test terminals to the test pads. The multiple test terminals can apply current to the test pads or measure voltage.

[0130] Figure 6 It is used to describe measurement Figure 8 A three-dimensional diagram of the method for contact resistance in the connection structure, and Figure 9A This is a schematic circuit diagram used to describe a method for measuring the contact resistance of a display device according to one or more embodiments. Figure 9B This is a perspective view illustrating a method for measuring contact resistance based on a comparative example, and Figure 9C and Figure 9A It is used to describe based on and Figure 7 Schematic circuit diagrams of methods for measuring contact resistance for one or more corresponding comparative examples.

[0131] refer to Figure 1 The multiple test terminals may include test terminal DT1-1 (1-1), test terminal DT1-2 (1-2), test terminal DT2 (2), test terminal DT3 (3), and test terminal DT4 (4). Test terminals DT1-1 (1-1) and DT1-2 (1-2) can be electrically connected to the first test pad TP1, test terminal DT2 can be electrically connected to the second test pad TP2, test terminal DT3 can be electrically connected to the third test pad TP3, and test terminal DT4 can be electrically connected to the fourth test pad TP4.

[0132] Substrate 100 (see Figure 1) can be located on a surface of the first test pad TP1, the second test pad TP2, the third test pad TP3, and the fourth test pad TP4, and the printed circuit board 50 can be located on the other surface thereof. The first connection line CL1 can be located on a surface of the first test pad TP1, and the terminal line DT_L can be located on (e.g., can contact) the other surface of the first test pad TP1. The second connection line CL2 can be located on a surface of the second test pad TP2, and the terminal line DT_L can be located on (e.g., can contact) the other surface of the second test pad TP2. The third connection line CL3 can be located on a surface of the third test pad TP3, and the terminal line DT_L can be located on (e.g., can contact) the other surface of the third test pad TP3. The fourth connection line CL4 can be located on a surface of the fourth test pad TP4, and the terminal line DT_L can be located on (e.g., can contact) the other surface of the fourth test pad TP4.

[0133] According to one or more embodiments, the driving integrated circuit 30 can be mounted on the first pad portion PDA1 by a COG method or a COP method, and the printed circuit board 50 can be mounted on the second pad portion PDA2 by a FOG method or a FOP method.

[0134] As described above, when the driving integrated circuit 30 and the printed circuit board 50 are respectively mounted on the pad portions of the display panel, a contact resistance can be generated. For example, the driving integrated circuit 30 and the first pad PD1 (see Figure 1 ) can contact each other, and thus a COG / COP resistance can be generated, and the printed circuit board 50 and the second pad PD2 (see Figure 7 ) can contact each other, and thus a FOG / FOP resistance can be generated.

[0135] Figure 7 is a view for describing a structure for testing a COG / COP resistance and a FOG / FOP resistance. In Figure 7 , a first contact resistance Rf as a FOG / FOP resistance and a second contact resistance Rc as a COG / COP resistance are tested. The first contact resistance Rf can be a contact resistance between the first test pad TP1 and the printed circuit board 50. The second contact resistance Rc can be a contact resistance between the first dummy pad DP1 and the driving integrated circuit 30.

[0136] Referring to Figure 7The test device for testing the first contact resistance Rf and the second contact resistance Rc can be connected to the plurality of test terminals. The first contact resistance Rf and the second contact resistance Rc can be connected in series to each other. According to one or more embodiments, a test current I can be applied to the 1-1 test terminal DT1-1, and the fourth test terminal DT4 can be grounded. For example, the fourth test terminal DT4 can be connected to the ground GND. The test current I can be about 1 mA. The test current I applied to the 1-1 test terminal DT1-1 can pass into the fourth test terminal DT4 by sequentially passing through the first test pad TP1, the first dummy pad DP1, the third dummy pad DP3, and the fourth test pad TP4. In other words, the test current I can flow through the terminal line DT_L connected to the 1-1 test terminal DT1-1, the first contact resistance Rf, the first connection line CL1, the second contact resistance Rc, the internal connection line ICL, the fourth connection line CL4, and the terminal line DT_L connected to the fourth test terminal DT4. Accordingly, the first contact resistance Rf and the second contact resistance Rc can be connected in series to each other.

[0137] Referring to Figure 8 and Figure 9A The 1-2 test terminal DT1-2 can be electrically connected to a first node N1 between the 1-1 test terminal DT1-1 and the first contact resistance Rf. The second test terminal DT2 can be electrically connected to a second node N2 between the first contact resistance Rf and the second contact resistance Rc. The third test terminal DT3 can be electrically connected to a third node N3 between the second contact resistance Rc and the fourth test terminal DT4.

[0138] The 1-2 test terminal DT1-2 can measure a voltage V11 of the first node N1, the second test terminal DT2 can measure a voltage V12 or V21 of the second node N2, and the third test terminal DT3 can measure a voltage V22 of the third node N3. In other words, the 1-2 test terminal DT1-2 and the second test terminal DT2 can measure a voltage across the first contact resistance Rf. The second test terminal DT2 and the third test terminal DT3 can measure a voltage across the second contact resistance Rc.

[0139] A potential difference V11-V12 between both ends of the first contact resistance Rf measured by the 1-2 test terminal DT1-2 and the second test terminal DT2 can be divided by a magnitude of the test current I to calculate a magnitude of the first contact resistance Rf. Likewise, a potential difference V21-V22 of both ends of the second contact resistance Rc measured by the second test terminal DT2 and the third test terminal DT3 can be divided by the magnitude of the test current I to calculate a magnitude of the second contact resistance Rc.

[0140] Figure 9Bis a view for describing a method of measuring a first contact resistance Rf and a second contact resistance Rc according to a comparative example, and Figure 9C and Figure 9A are circuit diagrams for describing a method of measuring a first contact resistance Rf and a method of measuring a second contact resistance Rc, respectively.

[0141] Referring to Figure 9B and Figure 9A , according to the comparative example, a circuit configured to measure the first contact resistance Rf and a circuit configured to measure the second contact resistance Rc can be provided separately from each other. According to the comparative example, a test current for measuring the first contact resistance Rf and a test current for measuring the second contact resistance Rc can be applied separately from each other. According to the comparative example, four test terminals can be used to measure the first contact resistance Rf. The four test terminals can include a terminal configured to apply a test current, a terminal configured to be grounded, and two terminals configured to measure a potential difference between both ends of the first contact resistance Rf. Likewise, another four test terminals can be used to measure the second contact resistance Rc. That is, referring to Figure 7 , according to the comparative example, a total of 8 test terminals and 7 test pads can be required in order to measure both the first contact resistance Rf and the second contact resistance Rc.

[0142] However, referring to Figure 10 , a display device according to one or more embodiments can measure the first contact resistance Rf and the second contact resistance Rc by using 5 test terminals DT1-1, DT1-2, DT2, DT3, and DT4 and 4 test pads TP1, TP2, TP3, and TP4. A test current for measuring the first contact resistance Rf and a test current for measuring the second contact resistance Rc can be commonly used. The display device according to one or more embodiments can measure a contact resistance by using a reduced number of test pads and test terminals, and thus, an area of a pad portion of a display panel and / or an area of a printed circuit board can be reduced, and a restriction on design can be reduced. Furthermore, a plurality of spare test pads or test terminals can be additionally used for a structure of a high potential difference pad, and thus, a robust design can be implemented.

[0143] Figure 11A is a perspective view of a connection structure of a test terminal, a dummy pad, and a test pad according to one or more embodiments, and Figure 11B and Figure 10 are perspective views for describing a method of measuring a contact resistance in the connection structure of Figure 10 . In Figure 6 , the same reference numerals as those of Figure 6 may denote the same elements as those of Figure 10elements identical to those of the first embodiment. Thus, repeated description thereof is omitted and differences are mainly described.

[0144] Referring to Figure 6 , according to one or more embodiments, the fifth test pad TP5, the fifth connection line CL5, and the fifth test terminal DT5 can further include a fifth node N5 between the second dummy pad DP2 and the third dummy pad DP3. The fourth connection line CL4 can be connected to the second dummy pad DP2, and the fifth connection line CL5 can be connected to the third dummy pad DP3. Figure 10 According to one or more embodiments corresponding to Figure 6 , unlike one or more embodiments corresponding to Figure 11A , the fourth connection line CL4 can be connected to the second dummy pad DP2, and the fifth connection line CL5 can be connected to the third dummy pad DP3. The third connection line CL3 and the fourth connection line CL4 can be integrally formed with each other.

[0145] Figure 10 is a view for describing a method of measuring the first contact resistance Rf according to one or more embodiments corresponding to Figure 11B , and Figure 10 is a view for describing a method of measuring the second contact resistance Rc according to one or more embodiments corresponding to Figure 11A .

[0146] First, referring to Figure 11B , to measure the first contact resistance Rf, the 1-1 test terminal DT1-1, the 1-2 test terminal DT1-2, the second test terminal DT2, and the third test terminal DT3 can be connected to a test device. A test current I can be applied to the second test terminal DT2, and the 1-1 test terminal DT1-1 can be grounded. The test current I applied to the second test terminal DT2 can pass into the 1-1 test terminal DT1-1 by sequentially passing through the second test pad TP2 and the first test pad TP1. In other words, the test current I can flow through a terminal line DT_L connected to the second test terminal DT2, the second connection line CL2, the first connection line CL1, the first contact resistance Rf, and the terminal line DT_L connected to the 1-1 test terminal DT1-1.

[0147] The third test terminal DT3 can be connected to a fourth node N4 between the second test terminal DT2 and the first contact resistance Rf. The 1-2 test terminal DT1-2 can be connected to a fifth node N5 between the 1-1 test terminal DT1-1 and the first contact resistance Rf. The third test terminal DT3 and the 1-2 test terminal DT1-2 can measure voltages V11 and V12 across the first contact resistance Rf. A potential difference V11-V12 across the first contact resistance Rf measured by the third test terminal DT3 and the 1-2 test terminal DT1-2 can be divided by a magnitude of the test current I to calculate a magnitude of the first contact resistance Rf.

[0148] Referring to Figure 10 to Figure 11B To measure the second contact resistance Rc, the 1-2 test terminal DT1-2, the third test terminal DT3, the fourth test terminal DT4, and the fifth test terminal DT5 can be connected to the test device. The test current I can be applied to the 1-2 test terminal DT1-2, and the third test terminal DT3 can be grounded. The test current I applied to the 1-2 test terminal DT1-2 can pass into the third test terminal DT3 by sequentially passing through the first test pad TP1, the first dummy pad DP1, the second dummy pad DP2, and the third test pad TP3. In other words, the test current I can flow through the terminal line DT_L connected to the 1-2 test terminal DT1-2, the first connection line CL1, the internal connection line ICL, the second contact resistance Rc, the third connection line CL3, and the terminal line DT_L connected to the third test terminal DT3.

[0149] The fifth test terminal DT5 can be electrically connected to a sixth node N6 between the 1-2 test terminal DT1-2 and the second contact resistance Rc. The fourth test terminal DT4 can be electrically connected to a seventh node N7 between the second contact resistance Rc and the third test terminal DT3. The fifth test terminal DT5 and the fourth test terminal DT4 can measure voltages V21 and V22 across the second contact resistance Rc. The potential difference V21-V22 across the second contact resistance Rc measured by the fifth test terminal DT5 and the fourth test terminal DT4 can be divided by the magnitude of the test current I to calculate the magnitude of the second contact resistance Rc.

[0150] Referring to ​ According to one or more embodiments, a display apparatus can measure both the first contact resistance Rf and the second contact resistance Rc by using six test terminals provided in a printed circuit board 50 and five test pads provided in a display panel. Accordingly, a design of a pad portion of the display panel can be improved, and an area of the printed circuit board can be reduced.

[0151] According to one or more embodiments described above, the number of pads for measuring contact resistance between a display panel and a driving integrated circuit or a printed circuit board can be reduced. However, the scope of the present disclosure is not limited to the above effects.

[0152] It is to be understood that the implementations described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each implementation should typically be considered as being applicable to other similar features or aspects in other implementations. While one or more implementations have been described with reference to the attached drawings, a person having ordinary skill in the art will appreciate that various changes in form and detail can be made thereto without departing from the spirit and scope of the disclosure as defined by the following claims and should include equivalents thereof.

Claims

1. A display device, characterized in that, include: A substrate defines a display area including pixels and a peripheral area surrounding at least a portion of the display area in a plan view; The first pad portion is located on one side of the substrate and includes a dummy pad; The second pad portion includes a test pad electrically connected to the dummy pad; The driver integrated circuit is electrically connected to the first pad portion; as well as A printed circuit board, electrically connected to the second pad portion and including test terminals electrically connected to the test pads. The dummy pads include a first dummy pad and a second dummy pad that are electrically connected to each other via internal interconnects in the driver integrated circuit. The test pads include a first test pad electrically connected to the first dummy pad via a first connection line, a second test pad electrically connected to the first dummy pad via a second connection line, and a third test pad electrically connected to the second dummy pad via a third connection line. The test terminals include test terminal 1-1 and test terminal 1-2, which are electrically connected to the first test pad.

2. The display device according to claim 1, characterized in that, The dummy pad also includes a third dummy pad electrically connected to the second dummy pad via the internal connection line, and The test pad also includes a fourth test pad that is electrically connected to the third dummy pad via a fourth connection line.

3. The display device according to claim 2, characterized in that, The internal connection wires are electrically connected to the surfaces of the first dummy pad, the second dummy pad, and the third dummy pad. The first connecting line and the second connecting line are electrically connected to the other surface of the first dummy pad. The third connecting line is electrically connected to the other surface of the second dummy pad, and The fourth connecting line is electrically connected to the other surface of the third dummy pad.

4. The display device according to claim 2, characterized in that, The test terminals also include a second test terminal electrically connected to the second test pad, a third test terminal electrically connected to the third test pad, and a fourth test terminal electrically connected to the fourth test pad.

5. The display device according to claim 4, characterized in that, The first-2 test terminals are electrically connected to the first node between the first-1 test terminal and the first test pad. Wherein, the second test terminal is electrically connected to the second node between the first test pad and the first dummy pad, and The third test terminal is electrically connected to a third node between the first dummy pad and the third dummy pad.

6. The display device according to claim 1, characterized in that, The dummy pad also includes a third dummy pad electrically connected to the second dummy pad via the internal connection line, and The test pads include a fourth test pad electrically connected to the second dummy pad via a fourth connection line and a fifth test pad electrically connected to the third dummy pad via a fifth connection line.

7. The display device according to claim 6, characterized in that, The internal connection wires are electrically connected to the surfaces of the first dummy pad, the second dummy pad, and the third dummy pad. The first connecting line and the second connecting line are electrically connected to the other surface of the first dummy pad. The third and fourth connecting lines are electrically connected to the other surface of the second dummy pad, and The fifth connecting line is electrically connected to the other surface of the third dummy pad.

8. The display device according to claim 6, characterized in that, The test terminals also include a second test terminal electrically connected to the second test pad, a third test terminal electrically connected to the third test pad, a fourth test terminal electrically connected to the fourth test pad, and a fifth test terminal electrically connected to the fifth test pad.

9. The display device according to claim 8, characterized in that, The second test terminal is connected to a fourth node between the first test pad and the second test pad, and The first-2 test terminals are connected to the fifth node between the first-1 test terminal and the first test pad.

10. The display device according to claim 8, characterized in that, The fifth test terminal is connected to the sixth node between the first dummy pad and the second dummy pad, and The fourth test terminal is connected to the seventh node between the second dummy pad and the third test terminal.

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