Wafer-level packaging structure adopting glass cover plate

Abstract

The utility model provides a wafer-level packaging structure adopting a glass cover plate, and relates to the technical field of semiconductor packaging. The structure comprises a glass cover plate layer, a chip, bonding glue and a conductive layer. The glass cover plate layer is provided with a first groove and a supporting side wall forming the circumferential wall face of the first groove. The chip comprises a functional area and a metal interconnection layer extending outwards from the functional area. The supporting side wall is fixed on the chip through bonding glue, so that the functional area is located in the first groove, and at least part of the metal interconnection layer extends out of the first groove. The conductive layer is arranged on the outer surface of the glass cover plate layer and is electrically connected with the metal interconnection layer. The structure is good in sealing performance, good in reliability, simple in process and high in production efficiency.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical field of semiconductor packaging, especially to a wafer level packaging structure using glass cover plate. BACKGROUND

[0002] The traditional packaging technology cuts the wafer into single chips first, and then packages each single chip. This packaging method is low in efficiency and high in cost. Wafer level packaging (WLP) is an advanced packaging technology currently used in discrete devices. Compared with the traditional packaging, WLP packages all the chips on the wafer before the wafer is cut into single chips. The wafer is cut into single chips after the packaging and internal circuit connection are completed. WLP has the advantages of smaller packaging size, higher efficiency, shorter production cycle, lower process cost, and easier integration. Therefore, WLP packaging has great advantages in the field of discrete devices and module integrated devices.

[0003] However, the current WLP packaging scheme with a cavity usually adds one or more layers of support structure between the wafer and the top cover plate to form a cavity. This structure not only increases the process steps and cost, but also increases the reliability risk due to the additional multi-layer structure. SUMMARY

[0004] The utility model aims at providing a wafer level packaging structure using glass cover plate, which has good structural sealing, good reliability, simple process, and high production efficiency.

[0005] In a first aspect, the utility model provides a wafer level packaging structure using glass cover plate, which comprises:

[0006] a glass cover plate layer, the glass cover plate layer having a first recess and a support side wall forming a circumferential wall surface of the first recess;

[0007] a chip; the chip comprising a functional area and a metal interconnection layer extending outward from the functional area;

[0008] a bonding glue;

[0009] the support side wall is fixed on the chip through the bonding glue, so that the functional area is located in the first recess, and the metal interconnection layer extends at least partially outside the first recess;

[0010] a conductive layer, the conductive layer being arranged on the outer surface of the glass cover plate layer and electrically connected with the metal interconnection layer.

[0011] In an optional embodiment, the chip comprises a coating area, the coating area being located at the periphery of the functional area, and the coating area being arranged correspondingly with the support side wall.

[0012] In an optional embodiment, the bonding glue is arranged between the coating area of the chip and the support side wall.

[0013] In an optional embodiment, the width of the coating area is equal to the width of the support side wall.

[0014] In an optional embodiment, the width of the bonding glue is not greater than the width of the coating area or the width of the support side wall.

[0015] In an optional embodiment, the coating area comprises an inner ring and an outer ring, the distance between the inner ring and the outer ring is the width of the coating area; the inner ring and the outer ring are both located on the metal interconnection layer.

[0016] In an optional embodiment, a part of the metal interconnection layer is located in the first groove, and another part of the metal interconnection layer extends to outside the first groove after passing through the coating area.

[0017] In an optional embodiment, the outer surface of the glass cover plate layer comprises a side surface and an upper surface connected with each other, the side surface is connected with the chip, and the upper surface is a side surface of the glass cover plate layer away from the chip; the conductive layer extends to the upper surface along the side surface.

[0018] In an optional embodiment, an electrical connection end is arranged on the conductive layer located on the upper surface.

[0019] In an optional embodiment, the electrical connection end is a solder ball.

[0020] In an optional embodiment, the conductive layer comprises a plurality of metal layers arranged in sequence.

[0021] The beneficial effects of the wafer level packaging structure with a glass cover plate provided by the utility model include:

[0022] The wafer level packaging structure with a glass cover plate provided by the utility model directly bonds the glass cover plate layer with the first groove with the chip on the wafer, so that the functional area of the chip is located in the cavity structure formed by the first groove, and the functional area of the chip can be effectively protected. The cavity structure formed has good sealing performance, high structural strength, and simple preparation operation, which improves the packaging reliability and also helps to improve the packaging efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the specific embodiment of the present application or the technical scheme in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiment or the prior art description, and obviously, the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0024] Figure 1 The schematic diagram of the wafer level packaging structure adopting the glass cover plate provided by the embodiment of the present application is shown in the figure.

[0025] Figure 2 The structure schematic diagram of the combination of the carrier plate and the glass cover plate layer in the preparation method of the wafer level packaging structure adopting the glass cover plate provided by the embodiment of the present application is shown in the figure.

[0026] Figure 3 The structure schematic diagram of forming the first groove and the second groove on the glass cover plate layer in the preparation method of the wafer level packaging structure adopting the glass cover plate provided by the embodiment of the present application is shown in the figure.

[0027] Figure 4 The structure schematic diagram of the wafer with multiple chips in the preparation method of the wafer level packaging structure adopting the glass cover plate provided by the embodiment of the present application is shown in the figure.

[0028] Figure 5 The structure schematic diagram of the first perspective view of a single chip in the wafer level packaging structure adopting the glass cover plate provided by the embodiment of the present application is shown in the figure.

[0029] Figure 6 The structure schematic diagram of forming the bonding glue on the wafer in the preparation method of the wafer level packaging structure adopting the glass cover plate provided by the embodiment of the present application is shown in the figure.

[0030] Figure 7 The structure schematic diagram of the bonding of the glass cover plate layer and the wafer in the preparation method of the wafer level packaging structure adopting the glass cover plate provided by the embodiment of the present application is shown in the figure.

[0031] Figure 8 The structure schematic diagram of removing the carrier plate after the bonding step of the wafer level packaging structure adopting the glass cover plate provided by the embodiment of the present application is shown in the figure. Figure 7

[0032] Figure 9 The structure schematic diagram of forming the conductive layer on the surface of the glass cover plate layer in the preparation method of the wafer level packaging structure adopting the glass cover plate provided by the embodiment of the present application is shown in the figure.

[0033] Figure 10 The structure schematic diagram of forming the electrical connection end on the conductive layer in the preparation method of the wafer level packaging structure adopting the glass cover plate provided by the embodiment of the present application is shown in the figure.​

[0034] Icon: 1 - carrier plate; 2 - adhesive film layer; 3 - glass cover plate layer; 4 - first groove; 5 - second groove; 31 - support side wall; 6 - chip; 7 - coating area; 8 - metal interconnection layer; 9 - functional area; 10 - cutting path; 11 - bonding adhesive; 12 - conductive layer; 13 - electrical connection end. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0036] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of the present application.

[0037] It should be noted that: similar reference numbers and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0038] In the description of the present application, it should be noted that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the orientations or positional relationships shown in the drawings, or the orientations or positional relationships commonly placed when the product of the present application is used, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third", etc. are only used for differentiation in description, and cannot be understood as indicating or implying relative importance.

[0039] In addition, the terms "horizontal", "vertical", "overhanging", etc. do not mean that the components must be absolutely horizontal or overhanging, but can be slightly inclined. For example, "horizontal" only means that its direction is relatively more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined.

[0040] In the description of the utility model, still need to explain, unless another explicit provision and limitation, term "arrangement", "installation", "link", "connection" should do broad sense understanding, for example, can be fixed connection, also can be detachable connection, or integrally connected;Can be mechanical connection, also can be electrical connection;Can be directly connected, also can pass through intermediate medium indirectly connected, can be two elements inside the intercommunication.For ordinary skilled in the art, can understand the specific meaning of the above terms in the utility model according to specific circumstances.

[0041] The utility model provides some implementation ways, which are described in detail below with reference to the drawings.In the case of no conflict, the following examples and features in examples can be combined with each other.

[0042] The wafer level packaging structure provided by the utility model embodiment can form a cavity structure with good sealing performance, has high reliability, simple process and is conducive to improving packaging efficiency.

[0043] In combination Figure 1 The wafer level packaging structure comprises a glass cover plate layer 3, a chip 6, a bonding glue 11 and a conductive layer 12.The glass cover plate layer 3 has a first groove 4 and a support side wall 31 forming a circumferential wall surface of the first groove 4.The chip 6 comprises a functional area 9 and a metal interconnection layer 8 extending outward from the functional area 9.The support side wall 31 is fixed on the chip 6 through the bonding glue 11, so that the functional area 9 is located in the first groove 4, and the metal interconnection layer 8 at least partially extends to outside the first groove 4.The conductive layer 12 is arranged on the outer surface of the glass cover plate layer 3 and is electrically connected with the metal interconnection layer 8.The wafer level packaging structure adopts the glass cover plate layer 3, has high structural strength, is convenient to process and has low cost.The glass cover plate layer 3 and the chip 6 are directly bonded, so that the process operation is simple and the efficiency is high.Because the cavity structure formed by the first groove 4 is integrally formed on the glass cover plate layer 3, the cavity has good sealing performance and prevents foreign matters from entering the functional area 9 of the chip 6 to affect the performance of the chip 6.Further, the integrally formed cavity structure omits the multilayer support structure for preparing the cavity in the traditional process, so that the process efficiency is higher, the structural reliability is better and the packaging quality is greatly improved.

[0044] It can be understood that the functional area 9 is provided with a circuit structure, and the metal interconnection layer 8 is used to connect the circuit of the functional area 9 and the pin outside the package.

[0045] Optionally, the chip 6 comprises a coating area 7, which is arranged in a ring shape at the periphery of the functional area 9. The coating area 7 is arranged in correspondence with the support side wall 31. The bonding glue 11 is arranged between the coating area 7 of the chip 6 and the support side wall 31, and is used to achieve the adhesive fixing of the support side wall 31 and the chip 6. It can be understood that the bonding glue 11 can be formed on the glass cover plate layer 3 or on the chip 6. Alternatively, the bonding glue 11 is formed on the glass cover plate layer 3 and the chip 6 respectively. As long as the bonding and fixing of the glass cover plate layer 3 and the chip 6 can be achieved. In the embodiment, the bonding glue 11 is formed on the chip 6, so that the dispensing precision is higher, and the bonding glue 11 can be effectively prevented from entering the functional area 9 of the chip 6 to contaminate the functional area 9 and reduce the performance of the chip 6.

[0046] Optionally, the width of the coating area 7 is substantially equal to the width of the support side wall 31. The width of the bonding glue 11 is not greater than the width of the coating area 7 or the width of the support side wall 31. In this way, the sealing connection can be achieved, and the risk of excessive glue pollution of the functional area 9 of the chip 6 can be reduced.

[0047] Optionally, the coating area 7 comprises an inner ring and an outer ring, the distance between the inner ring and the outer ring is the width of the coating area 7; the inner ring and the outer ring are both located on the metal interconnection layer 8. In other words, the width of the coating area 7 is less than the extension length of the metal interconnection layer 8. In this way, after the glass cover plate layer 3 and the chip 6 are bonded, part of the metal interconnection layer 8 is located in the first groove 4, and the other part extends to the outside of the first groove 4 after passing through the coating area 7. In this way, it is beneficial to subsequently form the conductive layer 12 electrically connected with the metal interconnection layer 8 on the glass cover plate layer 3.

[0048] Optionally, the outer surface of the glass cover plate layer 3 comprises a side surface and an upper surface connected with each other, the side surface is connected with the chip 6, and the upper surface is a side surface of the glass cover plate layer 3 away from the chip 6; the conductive layer 12 extends to the upper surface along the side surface, and part of the conductive layer 12 is arranged on the upper surface.

[0049] Optionally, the electrically connected end 13 is arranged on the conductive layer 12 on the upper surface. The electrically connected end 13 in the embodiment is a bump or a solder ball.

[0050] In combination with Figure 2 and Figure 3 , the wafer level packaging structure with the glass cover plate provided by the utility model roughly comprises the following steps in the packaging method:

[0051] S1: providing a combination of a carrier plate 1 and a glass cover plate layer 3. The glass cover plate layer 3 is spaced apart from the carrier plate 1 and is provided with a first groove 4 and a second groove 5 on the side away from the carrier plate 1. The depth of the first groove 4 is less than the thickness of the glass cover plate layer 3, and the second groove 5 penetrates the glass cover plate layer 3 in the thickness direction.

[0052] Optionally, the implementation of step S1 comprises steps S11, S12, S13 and S14.

[0053] Step S11: providing a carrier plate 1. The carrier plate 1 can be an organic carrier plate.

[0054] Step S12: pasting a film layer 2 on the carrier plate 1.

[0055] Step S13: pasting a glass cover plate layer 3 on the film layer 2. The glass cover plate layer 3 is fixed on the carrier plate 1 through the film layer 2, forming an integrated structure of the carrier plate 1 and the glass cover plate layer 3.

[0056] Step S14: forming a first groove 4 and a second groove 5 on the glass cover plate layer 3, respectively. The first groove 4 and the second groove 5 can be formed by etching, sandblasting or laser slotting, etc. The depth of the first groove 4 is shallower, and the depth of the first groove 4 is less than the thickness of the glass cover plate layer 3. The first groove 4 is used to accommodate the functional area 9 of the chip 6, so as to form a cavity structure above the functional area 9. It should be noted that the depth of the first groove 4 is used to form the cavity structure, so as to ensure that the chip can fully play its function, such as ensuring that the surface acoustic wave filter chip has good filtering performance. Therefore, the depth of the first groove 4 can be flexibly designed according to the size and type of the actual chip. Optionally, the depth of the first groove 4 accounts for 20% to 80% of the thickness of the glass cover plate layer 3. For example, the ratio of the depth of the first groove 4 to the thickness of the glass cover plate layer 3 is about 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, etc., which is not limited here. The depth of the second groove 5 is deeper, and the depth of the second groove 5 is equal to the thickness of the glass cover plate layer 3, that is, the second groove 5 penetrates the glass cover plate layer 3. The second groove 5 is used to form a separation groove between adjacent chips 6.

[0057] In some embodiments, the first groove 4 and the second groove 5 can be formed on the glass cover plate layer 3 first, and then the glass cover plate layer 3 is bonded to the carrier plate 1. Herein, no specific limitation is made.

[0058] In combination with Figure 4 , Figure 5 Step S2: providing a wafer with a plurality of chips 6. The wafer can be a single crystal wafer or a composite thin film wafer formed of a semiconductor material such as silicon Si, lithium tantalate LiTaO3 or lithium niobate LiNbO3, etc. A cutting channel 10 is formed between adjacent chips 6. Each chip 6 comprises a functional area 9 and a metal interconnection layer 8 extending outward from the functional area 9. Herein, extending outward means extending from the functional area 9 to the cutting channel 10.

[0059] In combination with Figure 6 , Figure 7Step S3: A bonding adhesive 11 is formed on the glass cover layer 3 and / or the chip 6, so that the glass cover layer 3 is covered on the wafer by the bonding adhesive 11. The functional area 9 is located within the first groove 4, which effectively protects the functional area 9 of the chip 6. The dicing channel 10 is located within the second groove 5; the bonding adhesive 11 is located between the first groove 4 and the second groove 5, and covers a portion of the metal interconnect layer 8.

[0060] Bonding adhesive 11 is applied to the coating area 7 of chip 6, and then the side of glass cover layer 3 away from the carrier 1 is fixed to the wafer by bonding adhesive 11. The bonding adhesive 11 can be a solid adhesive.

[0061] Combination Figure 8 Step S4: Remove carrier plate 1. Optionally, carrier plate 1 can be removed after the bonding adhesive 11 has hardened and stabilized. For example, carrier plate 1 can be removed by grinding. Alternatively, depending on the characteristics of the adhesive film layer 2, carrier plate 1 and glass cover layer 3 can be peeled apart by chemical cleaning, heating, or light irradiation. At this time, adhesive film layer 2 is also removed. The peeled carrier plate 1 can be reused, reducing encapsulation costs.

[0062] Optionally, after removing the carrier plate 1, the surface of the glass cover layer 3 needs to be cleaned to remove organic residues. This step includes, but is not limited to, cleaning the upper surface and sides of the glass cover layer 3 to ensure better adhesion of the conductive layer 12 subsequently formed on the surface and to prevent detachment and delamination.

[0063] Combination Figure 9 Step S5: A conductive layer 12 is formed on the sidewall of the second groove 5 of the glass cover layer 3 and on the surface of the glass cover layer 3 away from the wafer. The conductive layer 12 is electrically connected to the metal interconnect layer 8. That is, the conductive layer 12 is formed by metallization on the upper surface and side surface of the glass cover layer 3 so as to lead the metal interconnect layer 8 to the top of the glass cover layer 3.

[0064] Optionally, the conductive layer 12 includes multiple metal layers to improve adhesion and conductivity. In this embodiment, multiple metal layers are sequentially formed on the sidewall of the second groove 5 of the glass cover layer 3 and on the surface of the glass cover layer 3 away from the wafer. The conductive layer 12 can be formed by surface metallization using vapor deposition, which is efficient and low-cost. The multiple metal layers include four layers: an aluminum layer, a copper layer, a titanium layer, and a gold layer formed sequentially, with the aluminum layer in contact with the surface of the glass cover. This configuration not only improves adhesion and conductivity but also enhances heat dissipation.

[0065] Of course, in other embodiments, the conductive layer 12 can also be a one-layer, two-layer, three-layer, five-layer or more layer structure. The conductive material of each layer structure is not limited, and can be a single metal or an alloy, etc. The way of metallization to form the conductive layer 12 can also be electroplating, sputtering or pasting a conductive film, etc., which is not specifically limited here.

[0066] In combination Figure 10 Optionally, the electrical connection end 13 can be a bump or a solder ball, etc., and can be realized by using a conventional ball planting process. Finally, the wafer is cut along the cutting path 10 to form a single product. In this way, the wafer level packaging with the cavity structure is completed.

[0067] In the embodiment, the organic carrier plate and the glass cover plate layer 3 are bonded through the adhesive film layer 2, and the cavity structure is realized by sandblasting or laser process on the glass cover plate layer 3. After the groove is opened on the glass cover plate layer 3, the chip 6 configured with the circuit and the metal interconnection layer 8 is bonded and sealed to the wafer through the bonding glue 11, so that the functional area 9 with the circuit structure on the chip 6 which needs to be isolated and protected corresponds to the first groove 4 on the glass cover plate layer 3, so that the relatively sensitive circuit structure is protected in the glass cover plate layer 3. After the glass cover plate layer 3 and the wafer are bonded as a whole, the carrier plate 1 on the glass cover plate layer 3 is peeled off, so that each chip 6 has a corresponding independent cavity formed by the glass cover plate layer 3 on the whole wafer. Then, the metal conductive layer 12 is evaporated on the top and side of the glass cover plate layer 3 by using the metal evaporation technology, so as to lead out the circuit of the bottom chip 6 to the top of the glass cover plate layer 3, and realize the pin interconnection. Finally, the solder bump is formed on the conductive layer 12 area on the top of the glass cover plate layer 3, and the spherical electrical connection end 13 is formed.

[0068] The above process realizes the integration of the cavity structure, enhances the sealing performance and structural strength of the wafer level packaging structure without increasing the process complexity and cost. Moreover, in the embodiment of the utility model, after the groove structure is realized on the whole glass cover plate layer 3, the bonding of the multiple chips 6 and the groove cavity on the glass cover plate layer 3 is directly carried out. In the whole process, the process on the wafer surface is very little, which greatly reduces the risk of damage to the circuit layer on the wafer surface in the packaging process, and improves the reliability of the packaging quality.

[0069] In summary, the wafer level packaging structure with the glass cover plate provided by the embodiment of the utility model has the following beneficial effects:

[0070] The wafer level packaging structure with the glass cover plate provided by the utility model has the advantages of large structural strength, convenient processing, direct bonding of the glass cover plate layer 3 with the first groove 4 on the chip 6 on the wafer, positioning of the functional area 9 of the chip 6 in the cavity structure formed by the first groove 4, effective protection of the functional area 9 of the chip 6, good sealing performance of the cavity structure, large structural strength, simple preparation operation, improvement of packaging reliability, improvement of packaging efficiency, few process procedures on the wafer surface, great reduction of the risk of damage to the surface circuit layer of the chip 6 in the packaging process, and improvement of packaging quality and yield.

[0071] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the utility model, and not to limit them; although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; any modification, equivalent replacement, improvement, etc. should be included in the protection scope of the utility model.

Claims

1. A wafer level packaging structure employing a glass cover plate, characterized by, The application relates to a chip structure, which comprises: a glass cover plate layer (3) having a first groove (4) and a supporting side wall (31) forming a circumferential wall surface of the first groove (4); a chip (6) comprising a functional area (9) and a metal interconnection layer (8) extending outward from the functional area (9); bonding glue (11); the supporting side wall (31) is fixed on the chip (6) through the bonding glue (11) so that the functional area (9) is located in the first groove (4) and the metal interconnection layer (8) extends at least partially out of the first groove (4); a conductive layer (12) arranged on an outer surface of the glass cover plate layer (3) and electrically connected with the metal interconnection layer (8). 2.The wafer level package structure with glass cover plate according to claim 1, wherein, The chip (6) comprises a coating area (7) located at the periphery of the functional area (9), and the coating area (7) is arranged correspondingly with the supporting side wall (31). 3.The wafer level package structure with glass cover plate according to claim 2, wherein, The bonding glue (11) is arranged between the coating area (7) of the chip (6) and the supporting side wall (31). 4.The wafer level package structure with glass cover plate according to claim 2, wherein, The width of the coating area (7) is equal to the width of the supporting side wall (31). 5.The wafer level package structure with glass cover plate according to claim 4, wherein, The width of the bonding glue (11) is not greater than the width of the coating area (7) or the width of the supporting side wall (31). 6.The wafer level package structure with glass cover plate according to claim 2, wherein, The coating area (7) comprises an inner ring and an outer ring, the distance between the inner ring and the outer ring is the width of the coating area (7), and the inner ring and the outer ring are both located on the metal interconnection layer (8). 7.The wafer level package structure with glass cover plate of claim 2, wherein, Part of the metal interconnection layer (8) is located in the first groove (4), and the other part extends out of the first groove (4) after passing through the coating area (7). 8.The wafer level package structure with glass cover plate of claim 1, wherein, The outer surface of the glass cover plate layer (3) comprises a side surface and an upper surface, the side surface is connected with the chip (6), the upper surface is a side surface of the glass cover plate layer (3) far away from the chip (6), and the conductive layer (12) extends to the upper surface along the side surface. 9.The wafer level package structure with glass cover plate according to claim 8, wherein, An electrical connection end (13) is arranged on the conductive layer (12) located on the upper surface.

10. The wafer level package structure with glass cover plate according to any one of claims 1 to 9, wherein, The conductive layer (12) comprises a plurality of metal layers arranged in sequence.

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