SDRAM (Synchronous Dynamic Random Access Memory) high-capacity three-dimensional packaging memory module
By using a design that integrates circuit board stacking and gold plating layers, the stability and space utilization issues of large-capacity memory modules in planar packaging are solved, achieving an efficient and reliable three-dimensional packaging structure.
Patent Information
- Application Number
- CN202522082551.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-28
- Publication Date
- 2025-11-25
- Estimated Expiration
- 2035-09-28
AI Technical Summary
Existing high-capacity memory modules are difficult to package stably and reliably in planar packaging, and there are risks of flying wire connections and space waste in the manufacturing process.
The circuit boards are stacked and fixedly connected by a first epoxy resin layer, interconnected by a gold plating layer, and encapsulated by an outer second epoxy resin layer, achieving three-dimensional packaging and stable connection of the chips, avoiding flying wire connections.
This achieves the goals of saving planar space, improving manufacturing efficiency, ensuring the stability and reliability of connections, and reducing manufacturing difficulty and the risk of wire breakage.
Smart Images
Figure CN223598715U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to the technical field of memory module, especially relates to a SDRAM large capacity three -dimensional package memory module. BACKGROUND
[0002] At present, large capacity memory generally adopts imported device, adopts plane package technology, is difficult to realize plane package in compact scene, often requires compression circuit board area, this requirement leads to the chip interconnection of large capacity memory when plane package is difficult to realize. Although the existing memory package structure also exists through the stack realizes three -dimensional package, however, generally needs to be connected through the flying wire between the memory chip, and the connection needs to be carried out before packaging, needs to reserve space and leads to the increase of volume, there is also the risk of cutting off the flying wire when packaging, cannot realize stable reliable and efficient three -dimensional package structure.
[0003] Therefore, a SDRAM large capacity three -dimensional package memory module capable of saving plane space, stable and reliable connection and convenient manufacturing is needed. UTILITY MODEL CONTENTS
[0004] The utility model solves the technical problem that the prior art lacks, and provides a SDRAM large capacity three -dimensional package memory module capable of saving plane space, stable and reliable connection and convenient manufacturing.
[0005] The utility model adopts the technical scheme: the utility model discloses a plurality of circuit boards and a plurality of SDRAM memory chips, a plurality of circuit boards are stacked, a plurality of SDRAM memory chips are correspondingly arranged on the plurality of circuit boards, a filling gap is arranged between the two adjacent circuit boards, and the two adjacent circuit boards are fixedly connected through the first epoxy resin layer filled in the filling gap, and the two adjacent circuit boards are conductively connected through the gold plating layer arranged on the side wall of the first epoxy resin layer;The outer side of the circuit board at the end is provided with a second epoxy resin layer.
[0006] From the above scheme, the circuit boards are stacked and the SDRAM memory chips are arranged on the circuit boards, the three -dimensional package of the SDRAM memory chips is realized, the large capacity memory is interconnected, the plane space is saved, the gold plating layer arranged on the side wall of the first epoxy resin layer is used for interconnection, the flying wire connection is avoided, the production efficiency is improved, and the risk of flying wire disconnection in the manufacturing process is avoided, which is safer and more reliable. The second epoxy resin layer on the outer side realizes the packaging of the circuit board, and the reliability and stability of the overall structure are ensured.
[0007] A preferred scheme is that the circuit board at the end is also provided with a plurality of through pins, and the plurality of through pins are in conduction with the gold plating layer through the printed circuit of the circuit board.
[0008] A preferred scheme is that the SDRAM memory chip is in conduction with the gold plating layer through the printed circuit of the circuit board.
[0009] A further preferred scheme is that the edge of the circuit board is provided with a through contact, the through contact is in conduction with the gold plating layer, and the printed circuit of the circuit board is in communication with the through contact.
[0010] A further preferred scheme is that a plurality of the circuit boards are packaged into one after being cut at the edges to form cutting parts, and the gold plating layer connects the exposed printed circuits of the cutting parts to realize mutual conduction.
[0011] A preferred scheme is that a plurality of the SDRAM memory chips are connected in parallel with each other through the gold plating layer.
[0012] A further preferred scheme is that address buses, Bank address lines, row and column selection lines, clock lines, clock enable lines, byte mask lines, and write enable signal lines of a plurality of the SDRAM memory chips are respectively compounded, and chip selection signal lines and data buses of a plurality of the SDRAM memory chips are juxtaposed. BRIEF DESCRIPTION OF DRAWINGS
[0013] Figure 1 is a structural schematic diagram of the utility model;
[0014] Figure 2 is a circuit principle diagram of the utility model. DETAILED DESCRIPTION
[0015] As shown in Figure 1 and Figure 2 , in the embodiment, the utility model includes a plurality of circuit boards 1 and a plurality of SDRAM memory chips 2, the plurality of circuit boards 1 are stacked, the plurality of SDRAM memory chips 2 are correspondingly arranged on the plurality of circuit boards 1, two adjacent circuit boards 1 are provided with a filling gap and are fixedly connected with each other through the first epoxy resin layer 3 filled in the filling gap, and the two adjacent circuit boards 1 are in conduction with each other through the gold plating layer arranged on the side wall of the first epoxy resin layer 3.
[0016] In the embodiment, the circuit board 1 at the end is also provided with a plurality of through pins 4, and the plurality of through pins 4 are in conduction with the gold plating layer through the printed circuit of the circuit board 1. The through pins 4 are used for connecting and conducting with external circuit boards. And the through pins 4 are in conduction with each circuit board 1 through the gold plating layer.
[0017] In the embodiment, the SDRAM memory chip 2 is connected with the gold-plated layer through the printed circuit of the circuit board 1. The connection of the chip through the printed circuit of the circuit board 1 avoids the flying wire connection, saves the space, greatly reduces the manufacturing difficulty, and effectively improves the production efficiency.
[0018] In one specific embodiment, the edge of the circuit board 1 is provided with a conductive contact, the conductive contact is matched with the gold-plated layer to realize the conduction, and the printed circuit of the circuit board 1 is communicated with the conductive contact. The conductive contact is reserved, and the SDRAM memory chip 2 is connected with the conductive contact through the printed circuit, so that the late assembly process is reduced, and the rapid and stable assembly effect is realized.
[0019] In another specific embodiment, the circuit boards 1 are encapsulated into one through the first epoxy resin layer 3, and then the edge is cut to form a cutting part, and the gold-plated layer connects the exposed printed circuit of the cutting part to realize the mutual conduction. The exposed printed circuit is cut, and the conduction of the circuit is realized. At the same time, the synchronous processing of the circuit board 1 and the first epoxy resin layer 3 is realized through the cutting form, so that the process requirement of the epoxy resin pouring is reduced, and the reliable connection and conduction of the circuit are ensured.
[0020] In the embodiment, the outer side of the circuit board 1 at the end is provided with a second epoxy resin layer 5. The second epoxy resin layer 5 on the outer side encapsulates the circuit board 1, so as to ensure the reliability and stability of the overall structure.
[0021] In the embodiment, the SDRAM memory chips 2 are connected in parallel through the gold-plated layer. The address bus, the Bank address line, the row and column selection line, the clock line, the clock enable line, the low (high) byte mask line and the write enable signal line of the SDRAM memory chips 2 are respectively compounded, and the chip selection signal line and the data bus of the SDRAM memory chips 2 are juxtaposed.
[0022] In the embodiment, the gold-plated layer is formed into a gold-plated connecting line through engraving, so as to realize the one-to-one conduction of different lines and the mutual isolation between the lines.
[0023] In the embodiment, the circuit board 1 is packaged by SOP, and the SDRAM memory chip 2 is a plastic packaged SDRAM chip with a storage capacity of 32 MB and a data bus width of 16 bits.
[0024] Although the embodiments of the utility model are described in actual schemes, but do not constitute the limitation to the meaning of the utility model, for the person skilled in the art, according to the modification of the embodiments thereof in the specification and the combination with other schemes are obvious.
Claims
1. A SDRAM high capacity three-dimensional package memory module, comprising a plurality of circuit boards (1) and a plurality of SDRAM memory chips (2), the plurality of circuit boards (1) are stacked, and the plurality of SDRAM memory chips (2) are correspondingly arranged on the plurality of circuit boards (1), characterized in that: The two adjacent circuit boards (1) are provided with a filling gap and are fixed and connected with each other by a first epoxy resin layer (3) filled in the filling gap, and the two adjacent circuit boards (1) are conducted with each other through a gold-plated layer provided on the side wall of the first epoxy resin layer (3); the outer side of the circuit board (1) at the end is provided with a second epoxy resin layer (5). 2. The SDRAM high-capacity stacked package memory module of claim 1, wherein: The circuit board (1) at the end is further provided with a plurality of conducting pins (4), and the plurality of conducting pins (4) are conducted with the gold-plated layer through the printed circuit of the circuit board (1).
3. The SDRAM high-capacity stacked package memory module of claim 1, wherein: The SDRAM memory chip (2) is conducted with the gold-plated layer through the printed circuit of the circuit board (1).
4. A SDRAM high capacity stacked memory module according to claim 2 or 3, wherein: The edge of the circuit board (1) is provided with a conducting contact, the conducting contact is matched with the gold-plated layer for conduction, and the printed circuit of the circuit board (1) is communicated with the conducting contact.
5. A SDRAM high-capacity stacked memory module according to claim 2 or 3, wherein: After the plurality of circuit boards (1) are packaged into one body through the first epoxy resin layer (3) and then cut at the edge to form a cutting part, the gold-plated layer connects the exposed printed circuit of the cutting part to realize mutual conduction.
6. The SDRAM high-capacity stacked package memory module of claim 1, wherein: The plurality of SDRAM memory chips (2) are connected in parallel with each other through the gold-plated layer.
7. The SDRAM high-capacity stacked package memory module of claim 6, wherein: The address bus, the Bank address line, the row and column gating line, the clock line, the clock enable line, the byte mask line and the write enable signal line of the plurality of SDRAM memory chips (2) are respectively compounded, and the chip select signal line and the data bus of the plurality of SDRAM memory chips (2) are juxtaposed.