Wafer structure and chip

Abstract

The utility model relates to the technical field of wafer manufacturing, and discloses a wafer structure and a chip. The wafer structure comprises a wafer body, the wafer body comprises a cutting channel and crystal grains, and the cutting channel is located between two adjacent crystal grains; wherein the crystal grains comprise functional crystal grains and test crystal grains, and the test crystal grains are used for process testing of the wafer structure; wherein the sum of the areas of all the test crystal grains included in the wafer body is smaller than or equal to 10% of the area of the wafer body. According to the wafer structure disclosed by the invention, the test crystal grains are arranged, so that the Testkey arranged in the cutting channel in the related technology is eliminated, the width of the cutting groove can be reduced, the available area of the wafer body is increased, the number of single functional crystal grains is increased, the utilization rate of the wafer body is increased, and the production cost is reduced. By controlling the proportion of the area occupied by the test crystal grains, the utilization rate of the wafer main body is improved, the test requirement of the wafer structure can be met, the utilization rate of the wafer main body can be improved, and the production cost is reduced.

Description

Technical Field

[0001] This application relates to the field of wafer manufacturing technology, such as a wafer structure and a chip. Background Technology

[0002] In chip manufacturing, a wafer is divided into multiple dies using dicing lines. Individual dies are then obtained by cutting along the dicing lines, and each die is packaged to form a chip. Figure 1 and Figure 2 The diagram shows the distribution of the grains 13 and the dicing channels 12 within a single exposure area 11 of a wafer structure in the related art.

[0003] In related technologies, combined Figure 1 and Figure 2 As shown, according to the requirements of the wafer process, test keys 14 need to be arranged inside the dicing track 12 to meet the requirements for test pin settings within the dicing track. In order to set up the test keys, the width of the dicing track needs to be designed to be between 50um and 60um to meet the arrangement requirements of the test keys 14.

[0004] Furthermore, the insulating layer of the wafer in this technology uses Low-K (low dielectric constant) material. Due to the low mechanical strength and thermal stability of Low-K materials, Low-K marking technology is limited to laser grooving combined with blade marking. To ensure that the chip is not damaged during the marking process, the width of the dicing track needs to be further increased. A wider dicing track results in a smaller usable area on the wafer, thus reducing wafer utilization. Conversely, a dicing track that is too small increases the risk of damaging the die. Utility Model Content

[0005] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0006] This disclosure provides a wafer structure and chip to address the risk of excessively wide dicing channels reducing wafer utilization.

[0007] In some embodiments, a wafer structure is provided, comprising: a wafer body, the wafer body including dicing channels and dies, the dicing channels being located between two adjacent dies; wherein the dies include functional dies and test dies, the test dies being used for process testing of the wafer structure; wherein the sum of the areas of the test dies is less than or equal to 10% of the area of ​​the wafer body.

[0008] Optionally, the test die comprises: a test die body; a plurality of functional test pins arranged on the test die body and configured to be connected to the functional die; and a plurality of wafer test pins arranged on the test die body and configured to be connected to the circuit layer of the wafer body, wherein the wafer test pins are arranged on both sides of the functional test pins.

[0009] Optionally, the functional die comprises: a functional die body; and a die pin arranged on the functional die body and configured to be connected to an external circuit, wherein the wafer pin and the die test pin have the same size.

[0010] Optionally, the width of the cutting groove ranges from 15 um to 30 um.

[0011] Optionally, the size of the single test die is the same as the size of the single functional die.

[0012] Optionally, the sum of the areas of all the test dies included in the wafer body is less than or equal to 10% of the area of the wafer body.

[0013] Optionally, the wafer structure further comprises: a reinforcement groove arranged on the peripheral side wall of the die and located in the cutting groove.

[0014] Optionally, the width of the reinforcement groove ranges from D×20% to D×50%, where d is the width of the reinforcement groove and D is the width of the cutting groove.

[0015] Optionally, the wafer structure further comprises: a protective ring arranged on the peripheral side of the die, the protective ring being located between the reinforcement groove and the side wall of the die.

[0016] Optionally, the wafer structure further comprises: an isolation layer arranged on the peripheral side wall of the die, the reinforcement groove being located between the isolation layer and the cutting groove.

[0017] Optionally, in the depth direction of the cutting groove, the height of the isolation layer is greater than or equal to the height of the die.

[0018] Optionally, the thickness of the isolation layer ranges from 1 um to 2 um.

[0019] Optionally, the wafer body comprises a plurality of shots, each shot comprising a plurality of functional dies, wherein each shot is provided with one or more test dies, or the plurality of shots share one or more test dies for process testing.

[0020] In some embodiments, a die is provided, which is obtained by laser hidden cutting along the cutting groove of the wafer structure according to any of the above embodiments.

[0021] The wafer structure and the chip provided by the embodiments of the present disclosure can achieve the following technical effects:

[0022] The wafer structure provided by the embodiments of the present disclosure cancels the Test-key arranged in the scribe lane in the related art by arranging the test dies, so as to realize the reduction of the width of the scribe lane. In this way, the process test of the wafer structure can be realized by using the test dies, and the area of the scribe lane occupying the main body of the dies is reduced by reducing the width of the scribe lane, so as to increase the available area of the wafer main body, improve the single piece quantity of the functional dies, improve the utilization rate of the wafer main body, and reduce the production cost.

[0023] The utilization rate of the wafer main body is improved by controlling the proportion of the area occupied by the test dies. In this way, the test demand of the wafer structure can be met, and the utilization rate of the wafer main body is improved, and the production cost is reduced. By setting the sum of the areas of all the test dies included in the wafer main body to be less than or equal to 10% of the area of the wafer main body, the area saved by reducing the width of the scribe lane is much larger than the area of the test die position, so as to effectively improve the quantity of the functional dies and reduce the production cost.

[0024] The foregoing general description and the following description are only exemplary and explanatory, and are not used to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0025] One or more embodiments are exemplarily illustrated by the corresponding drawings, which do not constitute a limitation on the embodiments, and the elements with the same reference numerals in the drawings are shown as similar elements, the drawings do not constitute a proportional limitation, and wherein:

[0026] Figure 1 is a structure schematic diagram of a single shot in the wafer structure in the related art;

[0027] Figure 2 is a structure schematic diagram of a single shot in the wafer structure in the related art; Figure 1 is a distribution schematic diagram of part of the dies and the scribe lane in the related art;

[0028] Figure 3 is a structure schematic diagram of the wafer structure provided by the embodiments of the present disclosure;

[0029] Figure 4 is a structure schematic diagram of a single shot in the wafer structure provided by one embodiment of the present disclosure;

[0030] Figure 5 is a structure schematic diagram of a single shot in the wafer structure provided by one embodiment of the present disclosure; Figure 4 is a distribution schematic diagram of part of the dies and the scribe lane in one embodiment shown in the related art;

[0031] Figure 6 is a distribution schematic diagram of part of the dies and the scribe lane in another embodiment shown in the related art; Figure 4 ​

[0032] Figure 7 is Figure 6 an enlarged schematic view of A in the embodiment shown in FIG. 1;

[0033] Figure 8 is Figure 4 a structural schematic view of a test die in one embodiment shown in FIG. 2;

[0034] Figure 9 is Figure 4 a structural schematic view of a functional die in one embodiment shown in FIG. 3;

[0035] Figure 10 is a sectional view of a cutting lane in one embodiment of the present disclosure;

[0036] Figure 11 is a sectional view of a cutting lane in another embodiment of the present disclosure;

[0037] Figure 12 is a schematic view of multiple shots sharing multiple test dies in one embodiment of the present disclosure.

[0038] Reference signs in related art:

[0039] 11 exposure area; 12 cutting lane; 13 die; 14 Test-key;

[0040] Reference signs in embodiments of the present disclosure:

[0041] 1 wafer structure;

[0042] 100 wafer body; 102 exposure area; 110 cutting lane; 120 die; 130 functional die; 132 functional die body; 134 die pin; 140 test die; 150 test die body; 160 functional test pin; 161 first pin; 162 second pin; 170 wafer test pin; 171 first PAD; 172 second PAD; 173 third PAD; 174 fourth PAD; 175 fifth PAD; 180 circuit layer;

[0043] 200 reinforcing lane; 300 protection ring; 400 isolation layer; 410 protrusion. DETAILED DESCRIPTION

[0044] In order to enable a more detailed understanding of the features and technical content of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the drawings, which are only used for reference and do not limit the embodiments of the present disclosure. In the following technical description, in order to facilitate explanation, a plurality of details are provided to provide a full understanding of the disclosed embodiments. However, one or more embodiments can still be implemented without these details. In other cases, well-known structures and wafer structures can be simplified for illustration.

[0045] The terms "first", "second", and the like in the specification and claims of the embodiments of the present disclosure and the above drawings are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present disclosure described herein can be implemented. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion.

[0046] In the embodiments of the present disclosure, the terms "upper", "lower", "inner", "middle", "outer", "front", "back", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. These terms are mainly used to better describe the embodiments of the present disclosure and its embodiments, and are not used to limit the indicated wafer structure, element or component must have a specific orientation, or be constructed and operated in a specific orientation. In addition, in addition to being used to indicate the orientation or positional relationship, the above-mentioned terms can also be used to represent other meanings, for example, the term "upper" can also be used to represent a certain attachment relationship or connection relationship in some cases. For those skilled in the art, the specific meaning of these terms in the embodiments of the present disclosure can be understood according to the specific circumstances.

[0047] In addition, the terms "set", "connected", "fixed" should be broadly understood. For example, "connected" can be fixedly connected, detachably connected, or integrally configured; can be mechanically connected, or electrically connected; can be directly connected, or indirectly connected through an intermediate medium, or internal communication between two wafer structures, elements or components. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present disclosure can be understood according to the specific circumstances.

[0048] Unless otherwise specified, the term "a plurality of" means two or more.

[0049] In the embodiments of the present disclosure, the character " / " represents a "or" relationship between the objects before and after. For example, A / B represents: A or B.

[0050] The term "and / or" is a description of the association between objects, which means that there can be three relationships. For example, A and / or B, which means: A or B, or, A and B, the three relationships.

[0051] It should be noted that the embodiments in the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0052] In some embodiments, in combination with Figures 3 to 11 As shown in FIG. 1, a wafer structure 1 is provided, comprising: a wafer body 100 and a reinforcement path 200. The wafer body 100 comprises a cutting path 110 and a plurality of dies 120, the cutting path 110 being located between two adjacent dies 120. Wherein, the die 120 comprises a functional die 130 and a test die 140, the test die 140 being used for process testing of the wafer structure 1. The sum of the areas of the test dies 140 is less than or equal to 10% of the area of the wafer body 100.

[0053] The wafer structure 1 provided by the embodiments of the present disclosure cancels the Test-key arranged in the cutting path 110 in the related art by arranging the test die 140, so as to realize the reduction of the width of the cutting groove. In this way, the process testing of the wafer structure 1 can be realized by using the test die 140, and by reducing the width of the cutting groove, the area of the cutting groove occupying the main body of the die 120 is reduced, thereby increasing the available area of the wafer body 100, improving the number of single pieces of the functional die 130, improving the utilization rate of the wafer body 100, and reducing the production cost.

[0054] Further, the sum of the areas of all the test dies 140 included in the wafer body 100 is less than or equal to 10% of the area of the wafer body 100. By controlling the proportion of the area occupied by the test die 140, the utilization rate of the wafer body is improved. In this way, the test requirement of the wafer structure 1 can be met, and the utilization rate of the wafer body is improved, and the production cost is reduced. By setting the sum of the areas of all the test dies 140 included in the wafer body 100 to be less than or equal to 10% of the area of the wafer body 100, the area saved by reducing the width of the cutting groove is much larger than the area of the test die 140, so as to effectively improve the number of functional dies 130 and reduce the production cost.

[0055] Optionally, in combination with Figure 8 As shown in FIG. 1, the test die 140 comprises: a test die main body 150; a plurality of functional test pins 160 arranged in the test die main body 150 and used for connecting with the functional die 130; and a plurality of wafer test pins 170 arranged in the test die main body 150 and used for connecting with a circuit layer 180 of the wafer body. Wherein, the wafer test pins 170 are distributed on both sides of the functional test pins 160.

[0056] In this embodiment, the test chip includes functional test pins 160 and wafer test pins 170. The test die 140 includes the wafer test pins 170 for testing the wafer test pins 170 of the wafer process. The functional test pins 160 are used for testing the function of the individual die 120. In this way, by setting the functional test pins 160 and the wafer test pins 170, the performance of the functional die 130 and the connection reliability of the wafer main circuit layer 180 can be comprehensively evaluated.

[0057] Optionally, in combination with Figure 8 The test die main body 150 shown includes a first end and a second end, which are opposite sides of the test die main body 150. Among them, part of the plurality of wafer test pins 170 is arranged in the region close to the first end of the test die main body 150. Part of the plurality of wafer test pins 170 is arranged in the region close to the second end of the test die main body 150. The plurality of functional test pins 160 is located in the middle region. By arranging different types of test pins in the two ends and the middle region respectively, comprehensive testing of different functional regions on the wafer structure 1 can be realized, and the test coverage rate can be improved.

[0058] Optionally, in combination with Figure 8 The functional test pin 160 shown includes a first pin 161 and a second pin 162, which are arranged in a spaced manner. By connecting the first pin 161 and the second pin 162 with the pins of the functional die 130 respectively, the performance of the functional die 130 can be tested.

[0059] Optionally, in combination with Figure 8 As shown, the wafer test pin 170 includes a first PAD 171, a second PAD 172, a third PAD 173, a fourth PAD 174, and a fifth PAD 175. Among them, the number of the first PAD 171, the second PAD 172, the third PAD 173, the fourth PAD 174, and the fifth PAD 175 is two respectively, and they are symmetrically distributed on the first end and the second end of the test die main body 150. The first PAD 171 is connected to the wafer test first circuit layer 180, the second PAD 172 is connected to the wafer test second circuit layer 180, the third PAD 173 is connected to the wafer test third circuit layer 180, the fourth PAD 174 is connected to the wafer test fourth circuit layer 180, and the fifth PAD 175 is connected to the wafer test fifth circuit layer 180. By setting a plurality of PADs, and each PAD connecting different circuit layers 180, the plurality of circuit layers 180 of the wafer structure 1 can be tested independently, so as to more comprehensively evaluate the performance of the wafer structure 1 and ensure the quality and function of each circuit layer 180.

[0060] Optionally, in combination with Figure 9As shown, the functional die 130 includes a functional die body 132 and a die pin 134 disposed on the functional die body 132. The die pin 134 of the functional die body 132 is used to connect the internal circuit of the die 120 with an external circuit.

[0061] Optionally, the die pin 134 and the die test pin 170 are of the same size.

[0062] In this embodiment, by setting the die pin 134 and the die test pin 170 to be of the same size, on the one hand, the manufacturing of the wafer structure is facilitated; on the other hand, the consistent pin arrangement facilitates the testing operation.

[0063] It should be noted that, in the case where the die test pin 170 includes multiple PADs, the same size referred to herein means that the die pin 134 and a single PAD are of the same size.

[0064] Optionally, the die pin 134 and the die test pin 170 can also be of different sizes, which can be designed according to the specific application scenario of the wafer structure.

[0065] Optionally, the width D of the cutting groove 110 is in the range of 15um to 30um.

[0066] In this embodiment, by setting the test die 140 to replace the Test-key in the related art, the width of the cutting groove can be in the range of 15um to 30um. In this way, the available area of the die 120 body can be provided, and thus the production cost can be reduced.

[0067] Optionally, the width of the cutting groove 110 includes, but is not limited to, 15um, 16um, 17um, 18um, 19um, 20um, 21um, 22um, 23um, 24um, 25um, 26um, 27um, 28um, 29um or 30um.

[0068] Optionally, in combination with Figure 4 As shown, the size of a single test die 140 is the same as that of a single functional die 130.

[0069] In this embodiment, by setting the size of a single test die 140 to be the same as that of a single functional die 130, the division of the die 120 on the die 120 body is facilitated, and the subsequent cutting and manufacturing are facilitated, and the production cost is reduced.

[0070] Optionally, the fewer the number of test dies 140, the better, which reduces the occupancy rate of the wafer body. The specific number can meet the safety testing requirements of the wafer process, and the number is not limited herein.

[0071] Optionally, in combination with Figure 6 , Figure 7 and Figure 9 As shown, a reinforcing path 200 is provided on the side wall of the die 120 and located in the cutting groove. By providing the reinforcing path 200, the structural strength of the die 120 is enhanced, the stress resistance of the wafer after cutting is ensured, and the stress suffered by the chip during cutting and subsequent operation is reduced, thereby reducing the risk of cracks and damage. Moreover, during the cutting of the wafer, the reinforcing path 200 can prevent the cutting crack from spreading from the cutting groove 110 to the functional area, thereby protecting the integrity of the chip. This helps to reduce the short circuit or open circuit problem caused by cracks and improve the electrical performance of the chip. In addition, the circuit layer 180 of the die 120 is prevented from being cut during the cutting process, thereby improving the protection of the die 120.

[0072] Optionally, in combination with Figure 10 As shown, the width of the reinforcing path 200 is in the range of D x 20% ≤ d ≤ D x 50%, where d is the width of the reinforcing path 200, and D is the width of the cutting groove.

[0073] In this embodiment, by reasonably setting the width of the reinforcing path 200, sufficient mechanical strength is provided to support the side wall of the die 120 on the wafer, especially during deep trench isolation or cutting, which helps to prevent the side wall from collapsing or cracking. In addition, it helps to evenly disperse the stress generated during processing or use, reducing local stress concentration and thereby reducing the risk of damage to the die 120. A wider reinforcing path 200 can prevent over-etching during deep trench etching and protect the side wall of the die 120 from excessive erosion.

[0074] Optionally, the specific value of the width of the reinforcing path 200 includes, but is not limited to, D x 20%, D x 25%, D x 30%, D x 35%, D x 40%, D x 45%, or D x 50%.

[0075] Optionally, a Poly dummy (polysilicon structure) is used to set the reinforcing path 200 on the side wall of the die 120. Poly dummy is a virtual polysilicon structure that is not related to actual electronic components and is inserted into different areas of the wafer to fill empty space or adjust process steps. Using Poly dummy as the reinforcing path 200 reduces defects caused by mechanical stress during manufacturing, thereby improving overall yield. In addition, under the action of long-term use or environmental stress (such as temperature changes, vibrations, etc.), the reinforcing path 200 helps to maintain the stability of the chip structure, thereby improving the reliability of the product. In different areas of the wafer, due to process deviation or design reasons, uneven stress may occur. The polysilicon reinforcing path 200 can help balance these stresses and reduce defects caused by stress concentration.

[0076] Optionally, the width of the reinforcement path 200 can be set according to the size of the die 120 and process requirements.

[0077] Optionally, in combination with Figure 7 and Figure 9 As shown in the figure, the wafer structure 1 further comprises a protection ring 300 arranged on the periphery of the die 120, and the protection ring 300 is located between the reinforcement path 200 and the side wall of the die 120.

[0078] In this embodiment, the protection ring 300 is used to protect the edge of the die 120, and is located between the die 120 and the cutting groove, so as to prevent the die 120 from being mechanically damaged during cutting, thereby improving the protection effect of the die 120. And the protection ring 300 can block the moisture from the cutting side to invade the inside of the die 120, so as to protect the die 120 from the influence of the environmental humidity.

[0079] Optionally, the protection ring 300 (Sealring) comprises a ring-shaped diffusion region (Diff) and a ring-shaped metal contact via (Metal Contact Via). The ring-shaped diffusion region is usually composed of a doped silicon layer, which surrounds the edge of the die 120 to form a continuous ring structure. The ring-shaped metal contact via (Metal Contact Via) is a through hole formed on the silicon wafer, which is used to connect different levels of metal. The ring-shaped metal contact via connects the ring-shaped diffusion region with the upper metal to form a closed electrical connection ring, thereby enhancing the mechanical and electrical integrity of the protection ring 300.

[0080] Optionally, in combination with Figure 6 , Figure 7 and Figure 11 As shown in the figure, the wafer structure 1 further comprises an isolation layer 400 arranged on the periphery of the die 120, and the reinforcement path 200 is located between the isolation layer 400 and the cutting path 110.

[0081] In this embodiment, the isolation layer 400 is arranged around the periphery of each die 120, and the isolation layer 400 is in close contact with the side wall of the cutting groove.

[0082] Optionally, in combination with Figure 7 and Figure 9 As shown in the figure, the protection ring 300 is arranged on the periphery of the die 120, and the reinforcement path 200 is located between the protection ring 300 and the isolation layer 400, so as to set up a three-layer protection structure to enhance the protection effect of the die 120, thereby improving the reliability of the die 120.

[0083] In combination with Figure 7 and Figure 11As shown, by adopting the wafer structure 1 provided by the present disclosure, the isolation layer 400 is arranged on the side of the die 120 and located on the sidewall of the cutting groove. The isolation layer 400 can isolate the die 120 and prevent short circuit that may occur during cutting or subsequent use, so as to protect the circuit layer 180 of the die 120, improve the reliability and safety of the PI material removed in the cutting groove part, and protect the reliability of the circuit layer 180. In addition, the protection of the die 120 by the isolation layer 400 can improve the stability of the wafer scribing process and the safety of the die 120.

[0084] Optionally, the isolation layer 400 is a PI (Polyimide, polyimide) isolation layer 400. The PI isolation layer 400 has good mechanical strength and flexibility, and can withstand high temperature treatment in the wafer manufacturing process. In this way, it can not only prevent external moisture from entering the circuit layer 180 of the die 120, but also protect the circuit layer 180 from being damaged during the scribing process.

[0085] Optionally, in combination with Figure 11 As shown, along the depth direction of the cutting path 110, the height of the isolation layer 400 is greater than or equal to the height of the die 120.

[0086] In this embodiment, by setting the height of the isolation layer 400 to be greater than or equal to the height of the die 120, the isolation layer 400 can extend from the bottom of the die 120 to the top of the die 120 or beyond, thereby improving the coverage effect of the entire sidewall of the die 120 to prevent debris, dust or other contaminants generated during cutting from contacting the sidewall of the die 120, thereby avoiding potential electrical short circuit or functional damage and improving the protection of the die 120.

[0087] Optionally, the thickness of the isolation layer 400 is in the range of 1um to 2um.

[0088] In this embodiment, the isolation layer 400 with a thickness of 1um to 2um can not only ensure good electrical insulation performance, but also maintain the stability of the structure.

[0089] In the specific implementation process, the thickness of the isolation layer 400 can be reasonably set according to different application environments to meet the isolation requirements, which will not be described here.

[0090] Optionally, the specific value of the thickness of the isolation layer 400 includes but is not limited to 1um, 1.2um, 1.5um, 1.6um or 2um.

[0091] In some embodiments, in combination with Figure 11 As shown, the isolation layer 400 includes a protrusion 410 located on one side of the cutting groove opening.

[0092] In this embodiment, the protrusions 410 are arranged on the side wall of the opening of the cutting groove at one end of the cutting groove. In this way, there are protrusions 410 extending along the length direction of the cutting groove on both sides of the opening of the cutting groove. By arranging the protrusions 410, the protrusions 410 play a protective role for the crystal grains 120 during the scribing process.

[0093] Optionally, the shape of the protrusions 410 includes but is not limited to a circle, an ellipse, a square, a triangle, etc., and is selected according to the material properties and manufacturing process of the isolation layer 400.

[0094] Optionally, the protrusions 410 are uniformly distributed or arranged in a specific pattern along the extension direction of the cutting groove, for example, the density of the protrusions 410 is increased in the stress concentration area to improve the local strength.

[0095] In some embodiments, the height of the protrusions 410 ranges from 1 um to 3 um along the width direction of the opening of the cutting groove.

[0096] In this embodiment, the height of the protrusions 410 is set to 1 um to 3 um. On the one hand, by arranging the protrusions 410 with appropriate height, the strength and stability of the structure are improved. On the other hand, the space with the height of the protrusions 410 removed at the opening of the cutting groove can meet the requirements of the cutting process, so that the crystal grains 120 can be smoothly cut.

[0097] The height of the protrusions 410 can be adjusted according to different cutting process requirements to adapt to different production requirements.

[0098] Optionally, the specific value of the height of the protrusions 410 includes but is not limited to 1 um, 1.5 um, 2 um, 2.5 um, or 3 um.

[0099] In some embodiments, the width of the opening of the cutting groove ranges from 8 um to 14 um.

[0100] In this embodiment, the width of the opening of the cutting groove is set to 8 um to 14 um to meet the implementation of the cutting process.

[0101] Specifically, the width of the opening of the cutting groove can be adjusted according to the precision of the cutting equipment and the size of the crystal grains 120.

[0102] Optionally, the specific value of the width L of the opening of the cutting groove includes but is not limited to 8 um, 9 um, 10 um, 11 um, 12 um, 13 um, or 14 um.

[0103] Optionally, the wafer body 100 includes a plurality of shots, and each shot includes a plurality of functional crystal grains 130.

[0104] Optionally, a single shot may be configured with one or more test dies 140.

[0105] In this embodiment, combined with Figure 3 As shown, the wafer body 100 includes multiple exposure areas 102 (shots), combined with Figure 3 and Figure 4 As shown, each shot includes multiple functional dies 130 and test dies 140. The number of test dies 140 is one or more. Wafer process testing within a single shot is achieved using the test dies 140.

[0106] Optionally, if a single shot includes multiple test dies 140, the multiple test dies 140 are distributed at the vertices of the single shot. For example, if a single shot includes two test dies 140, the two test dies 140 are distributed at the two vertices of the diagonal of the single shot. If a single shot includes four test dies 140, then one test die 140 is provided at each vertices of the single shot.

[0107] Optionally, multiple shots may share one or more test dies 140 for process testing.

[0108] In this embodiment, combined with Figure 1 As shown, the wafer body 100 includes multiple exposure areas 102 (shots), and each shot includes multiple functional dies 130. Multiple shots share one or more test dies 140 for process testing. This allows the position and number of test dies 140 to be set according to testing requirements, thereby improving wafer utilization. In wafer structure 1, multiple shots sharing one or more test chips for process testing can reduce the area occupied by the test chips and improve wafer utilization.

[0109] Combination Figure 12 As shown, when multiple shots share one or more test dies 140, the test die 140 is set at the apex of the connection between the multiple shots.

[0110] In some embodiments, a chip is provided, which is obtained by laser slicing along the cutting groove of the wafer structure 1 as described in any of the above embodiments to obtain a die 120, and each die 120 is individually packaged to obtain a chip.

[0111] In this embodiment, the laser hidden cutting method is adopted to obtain a plurality of dies along the cutting groove of the wafer structure 1, and the single die is independently packaged to obtain a chip. Since the too small cutting groove cannot realize the safe dicing method, the laser hidden cutting method is adopted to cut, so that the packaging process dicing can be realized in the case of the narrow cutting groove. In this way, the utilization rate of the wafer structure is improved by reducing the width of the cutting groove. Moreover, the effect of the packaging process dicing can be improved.

[0112] The above description and drawings suffice to fully illustrate the embodiments of the present disclosure to enable a person skilled in the art to practice them. Other embodiments can include structural and other changes. The embodiments only represent possible changes. Unless explicitly required, individual components and functions are optional, and the order of operations can be changed. Some embodiments can include or replace the parts and features of other embodiments. The embodiments of the present disclosure are not limited to the structures that have been described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A wafer structure, characterized by, The wafer structure comprises: a wafer body comprising a plurality of dies and a plurality of streets, wherein each street is located between two adjacent dies; the plurality of dies comprises functional dies and test dies, wherein the test dies are used for process testing of the wafer structure; a sum of areas of the test dies is less than or equal to 10% of an area of the wafer body.

2. The wafer structure of claim 1, wherein, The test die comprises: a test die body; a plurality of functional test pins arranged on the test die body and used for connecting with the functional dies; a plurality of wafer test pins arranged on the test die body and used for connecting with a circuit layer of the wafer body; the wafer test pins are distributed on two sides of the functional test pins.

3. The wafer structure of claim 2, wherein, The functional die comprises: a functional die body; a die pin arranged on the functional die body, wherein the die pin is used for connecting with an external circuit; the wafer pin and the die test pin have the same size.

4. The wafer structure according to any one of claims 1 to 3, wherein: a size of a single test die is the same as a size of a single functional die; and / or a width of the street ranges from 15 um to 30 um.

5. The wafer structure of any one of claims 1 to 3, wherein, The wafer structure further comprises: a reinforcement street arranged on a peripheral side wall of the die and located in the street.

6. The wafer structure of claim 5, wherein, The wafer structure further comprises: a protection ring arranged on a peripheral side of the die, wherein the protection ring is located between the reinforcement street and the side wall of the die.

7. The wafer structure according to claim 5, wherein: an isolation layer is arranged on the peripheral side wall of the die, and the reinforcement street is located between the isolation layer and the street.

8. The wafer structure according to claim 7, wherein: a width of the reinforcement street ranges from D×20% to D×50%, wherein d is the width of the reinforcement street, and D is the width of the street; and / or a height of the isolation layer is greater than or equal to a height of the die along a depth direction of the street; and / or a thickness of the isolation layer ranges from 1 um to 2 um.

9. The wafer structure according to any one of claims 1 to 3, wherein: the wafer body comprises a plurality of shots, and each shot comprises a plurality of functional dies; each shot is provided with one or more test dies; or the plurality of shots share one or more test dies for process testing.

10. A chip, comprising: a plurality of dies obtained by laser hidden cutting along a street of the wafer structure according to any one of claims 1 to 9, and packaging the plurality of dies to obtain the chip.

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