Ring oscillator circuit and ring oscillator

Abstract

The utility model discloses ring shape oscillation circuit and ring shape oscillator, ring shape oscillation circuit includes ring shape oscillation module, and ring shape oscillation module includes 2n+1 head -to -tail cascaded inverter unit, and every inverter unit is correspondingly provided with current pull -up unit and current pull -down unit, and current pull -up unit is connected with first current output end and corresponding inverter unit respectively, and current pull -down unit is connected with second current output end and corresponding inverter unit respectively, and 2n inverter units are connected in the mode that the first end of two adjacent inverter units corresponds and meets, and the second end of another two adjacent inverter units corresponds and meets, starting from the inverter unit of first position, and the connecting end of the inverter unit of last position and current pull -down unit is connected to the connecting end of the inverter unit of first position and current pull -down unit. Because the size of first bias current and second bias current on same inverter unit is different, and the steady state operating point of negative feedback loop is broken down equivalent, thereby continuous oscillation.

Description

TECHNICAL FIELD

[0001] The utility model relates to oscillator technical field especially relates to a ring oscillator circuit and ring oscillator. BACKGROUND

[0002] In order to ensure normal work in many electronic equipment, usually set up ring oscillator. In a commonly used ring oscillator, design has odd number of inverter, and odd number of inverter head-to-tail connection constitutes ring formation feedback, the output of certain stage inverter is exported after filtering, generates high frequency oscillation signal, such as Figure 3 As shown in the figure, it is each stage waveform diagram that the ring oscillator in the prior art outputs under normal circumstances, such as Figure 4 As shown in the figure, it is the partial waveform enlarged view in each stage waveform that the ring oscillator in the prior art outputs under normal circumstances.

[0003] At present, the ring oscillator circuit composed of odd number of inverters uses fixed current source for each inverter, since the ring oscillator circuit composed of odd number of inverters has negative feedback structure, therefore, under abnormal circumstances, there is a degenerate operating point in the ring oscillator circuit composed of odd number of inverters in the prior art, so that the output voltage of each inverter is in a steady-state analog voltage state, so that the ring oscillator circuit also outputs fixed voltage, resulting in that the ring oscillator circuit does not oscillate, such as Figure 5 As shown in the figure, it is the waveform diagram that the ring oscillator in the prior art outputs under abnormal circumstances, from Figure 5 The waveform diagram can be seen that there is no oscillation in some positions.

[0004] Therefore, the prior art still needs to be improved and developed. INVENTION CONTENTS

[0005] In view of the above deficiencies of the prior art, the purpose of the utility model is to provide a ring oscillator circuit and ring oscillator, to solve the problem that there is a degenerate operating point in the ring oscillator circuit composed of odd number of inverters in the prior art, so that the output voltage of each inverter is in a steady-state analog voltage state, so that the ring oscillator circuit also outputs fixed voltage, resulting in that the ring oscillator circuit does not oscillate.

[0006] The utility model provides a ring oscillator circuit, comprising:

[0007] Bias module, the bias module includes the first current output end for outputting first bias current and the second current output end for outputting second bias current;

[0008] The ring-shaped oscillation module comprises 2n+1 inverter units connected in a head-to-tail manner, n is a positive integer, each inverter unit is provided with a current pull-up unit and a current pull-down unit, the current pull-up unit is connected with the first current output end and the corresponding inverter unit respectively, and the current pull-down unit is connected with the second current output end and the corresponding inverter unit respectively, wherein the connection end of each inverter unit and the corresponding current pull-up unit is a first end, the connection end of each inverter unit and the corresponding current pull-down unit is a second end, the 2n inverter units are connected in a mode that the first ends of two adjacent inverter units are connected and the second ends of the other two adjacent inverter units are connected, the connection end of the last inverter unit and the current pull-down unit is connected to the connection end of the first inverter unit and the current pull-down unit, and the last inverter unit is used for outputting a first voltage signal.

[0009] The oscillation signal output module is connected with the last inverter unit, the oscillation signal output module is used for receiving the first voltage signal and an enable signal, and outputs an oscillation signal according to the first voltage signal and the enable signal.

[0010] The first bias current is equal to the second bias current in the further setting of the utility model.

[0011] The inverter unit comprises a first switch tube and a second switch tube, the gate of the first switch tube is connected with the gate of the second switch tube, the drain of the first switch tube is connected with the drain of the second switch tube, the source of the first switch tube is connected with the corresponding current pull-up unit, the source of the second switch tube is connected with the current pull-down unit, the connection end of the gate of the first switch tube and the gate of the second switch tube is the voltage input end of the inverter unit, and the connection end of the drain of the first switch tube and the drain of the second switch tube is the voltage output end of the inverter unit.

[0012] The current pull-up unit comprises a third switch tube, the source of the third switch tube is connected with a first power supply end, the gate of the third switch tube is connected with the first current output end, and the drain of the third switch tube is connected with the source of the corresponding first switch tube.

[0013] The current pull-down unit comprises a fourth switch tube, the drain of the fourth switch tube is connected with the source of the corresponding second switch tube, the gate of the fourth switch tube is connected with the second current output end, and the source of the fourth switch tube is grounded.

[0014] The further setting of the utility model discloses, the bias module includes first current mirror, the first current mirror includes first end, second end, third end and fourth end, the first end is connected with first power supply end, the second end is grounded, the third end is the first current output end, the fourth end is the second current output end.

[0015] The further setting of the utility model discloses, the first current mirror includes: first current source, fifth switch tube, sixth switch tube and seventh switch tube;

[0016] The gate of fifth switch tube is connected with the drain of fifth switch tube, and the drain of fifth switch tube is also connected with the first current source, the source of fifth switch tube is connected with the source of sixth switch tube, and the gate of five switch tube is connected with the gate of sixth switch tube;

[0017] The drain of sixth switch tube is connected with the drain of seventh switch tube, the source of seventh switch tube is connected with the first current source, and the gate of seventh switch tube is connected with the drain of seventh switch tube;

[0018] Among them, the source of fifth switch tube is the first end of the first current mirror, the gate of sixth switch tube is the third end of the first current mirror, the gate of seventh switch tube is the fourth end of the first current mirror, and the source of seventh switch tube is the second end of the first current mirror.

[0019] The further setting of the utility model discloses, the oscillation signal output module includes:

[0020] The first inverter for accessing the enable signal;

[0021] The gate of eighth switch tube is connected with the output end of the first inverter, the source of eighth switch tube is grounded, and the drain of eighth switch tube is connected with the last inverter unit.

[0022] The first NAND gate, the first input end of the first NAND gate is connected with the input end of the first inverter, and the second input end of the first NAND gate is connected with the last inverter unit.

[0023] The utility model discloses still provide a kind of ring oscillator, comprising: ring oscillator circuit as described above.

[0024] Beneficial effects:

[0025] In the ring-shaped oscillation circuit, 2n+1 inverter units are connected in cascade, and 2n inverter units are connected in sequence from the first inverter unit, with the first ends of two adjacent inverter units connected and the second ends of the other two adjacent inverter units connected; the second end of the last inverter unit is connected to the second end of the first inverter unit; the current source of the two current pull-up units connected through the first end is increased, the current source of the two current pull-down units corresponding to the two current pull-up units is unchanged, the current source of the two current pull-down units connected through the second end is increased, and the current source of the two current pull-up units corresponding to the two current pull-down units is unchanged; therefore, the first bias current and the second bias current on the same inverter unit are different in size, the first bias current and the second bias current of adjacent two inverter units are different in proportion, the steady-state working point of the negative feedback loop is equivalent to be destroyed, the degenerate working point is avoided, and continuous oscillation is achieved. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical scheme in the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained according to the structures shown in the drawings without creative labor.

[0027] Figure 1 is a circuit structure diagram of the ring-shaped oscillation circuit of the present application.

[0028] Figure 2 is an output waveform diagram of the ring-shaped oscillation circuit in an embodiment of the present application.

[0029] Figure 3 is an output waveform diagram of the ring-shaped oscillation circuit of the prior art of the present application.

[0030] Figure 4 is a partial enlarged view of the output waveform diagram of the ring-shaped oscillation circuit of the prior art of the present application.

[0031] Figure 5 is an output waveform diagram of the ring-shaped oscillation circuit of the prior art of the present application

[0032] In the drawings: 100, biasing module; 200, ring oscillator module; 201, inverter unit; 202, current pull-up unit; 203, current pull-down unit; 300, oscillation signal output module; 301, first NAND gate; 302, first inverter; I1, first current source; M1, first switch tube; M2, second switch tube; M3, third switch tube; M4, fourth switch tube; M5, fifth switch tube; M6, sixth switch tube; M7, seventh switch tube; M8, eighth switch tube; VDD, first power supply terminal. DETAILED DESCRIPTION

[0033] In order to have a clearer understanding of the technical features, objects and effects of the present application, the specific embodiments of the present application will be described in detail with reference to the drawings. In the following description, it should be understood that the directions or positional relationships indicated by "front", "back", "upper", "lower", "left", "right", "vertical", "horizontal", "vertical", "horizontal", "top", "bottom", "inner", "outer", "head", "tail" and the like are based on the directions or positional relationships shown in the drawings, constructed and operated in a particular direction, and are only for the convenience of describing the present technical solution, and cannot be understood as indicating that the devices or elements indicated must have a particular direction, therefore cannot be understood as limiting the present application.

[0034] As shown in Figure 1 The present application provides a ring oscillator, which can include a biasing module 100, a ring oscillator module 200 and an oscillation signal output module 300.

[0035] The bias module 100 comprises a first current output end for outputting a first bias current and a second current output end for outputting a second bias current. The ring oscillation module 200 comprises 2n+1 inverter units 201 connected in a head-to-tail manner, n being a positive integer, each inverter unit 201 being provided with a current pull-up unit 202 and a current pull-down unit 203, the current pull-up unit 202 being connected with the first current output end and the corresponding inverter unit 201 respectively, and the current pull-down unit 203 being connected with the second current output end and the corresponding inverter unit 201 respectively, wherein the connection end of each inverter unit 201 and the corresponding current pull-up unit 202 is a first end, the connection end of each inverter unit 201 and the corresponding current pull-down unit 203 is a second end, the 2n inverter units 201 are connected in a manner that the first ends of two adjacent inverter units 201 are connected and the second ends of the other two adjacent inverter units 201 are connected, the second end of the last inverter unit 201 is connected with the second end of the first inverter unit 201, and the last inverter unit 201 is used for outputting a first voltage signal. The oscillation signal output module 300 is connected with the last inverter unit 201, and the oscillation signal output module 300 is used for receiving the first voltage signal and an enable signal and outputting an oscillation signal according to the first voltage signal and the enable signal.

[0036] Specifically, n can be 1, 2, 3, 4, 5, 6, and the like. Figure 2 As shown, when the enable signal is accessed, the square wave signal can be accessed as the enable signal, Figure 2 The INPUT in the figure indicates the waveform of the enable signal. The connection of the first ends of two adjacent inverter units 201 means that in the two adjacent inverter units 201, the first end on one inverter unit 201 is connected with the first end on the other inverter unit 201; similarly, the connection of the second ends of two adjacent inverter units 201 means that in the two adjacent inverter units 201, the second end on one inverter unit 201 is connected with the second end on the other inverter unit 201.

[0037] In order to illustrate the connection mode of the two first ends and the two second ends, the following examples are further illustrated.

[0038] Example one: as Figure 1As shown, it is a structural diagram of the ring-shaped oscillation module 200 when n is 1, that is, there are 3 inverter units 201 in the ring-shaped oscillation module 200, wherein the 2n inverter units 201 refer to the first inverter unit 201 and the second inverter unit 201 counted from the first inverter unit 201, and when the first ends are connected, the first end corresponding to the first inverter unit 201 is connected with the first end corresponding to the second inverter unit 201, and the second end corresponding to the third inverter unit 201 is connected with the second end corresponding to the first inverter unit 201.

[0039] As shown, it is a structural diagram of the ring-shaped oscillation module 200 when n is 1, that is, there are 3 inverter units 201 in the ring-shaped oscillation module 200, wherein the 2n inverter units 201 refer to the first inverter unit 201 and the second inverter unit 201 counted from the first inverter unit 201, and when the first ends are connected, the first end corresponding to the first inverter unit 201 is connected with the first end corresponding to the second inverter unit 201, and the second end corresponding to the third inverter unit 201 is connected with the second end corresponding to the first inverter unit 201.

[0040] As shown, it is a structural diagram of the ring-shaped oscillation module 200 when n is 1, that is, there are 3 inverter units 201 in the ring-shaped oscillation module 200, wherein the 2n inverter units 201 refer to the first inverter unit 201 and the second inverter unit 201 counted from the first inverter unit 201, and when the first ends are connected, the first end corresponding to the first inverter unit 201 is connected with the first end corresponding to the second inverter unit 201, and the second end corresponding to the third inverter unit 201 is connected with the second end corresponding to the first inverter unit 201.

[0041] In this example, in the ring-shaped oscillation circuit, 2n+1 inverter units 201 are connected in cascade, from the first inverter unit 201, in order, the first ends of two adjacent inverter units 201 are connected, and the second ends of the other two adjacent inverter units 201 are connected, the second end corresponding to the last inverter unit 201 is connected with the second end corresponding to the first inverter unit 201, the current source of the two current pull-up units 202 connected through the first end is larger, the current source of the two current pull-down units 203 corresponding thereto is unchanged, the current source of the two current pull-down units 203 connected through the second end is larger, the current source of the two current pull-up units 202 corresponding thereto is unchanged, therefore, the first bias current and the second bias current on the same inverter unit 201 are different in size, and the first bias current and the second bias current of adjacent inverter units 201 are different in proportion, which equivalently destroys the steady-state working point of the negative feedback loop, thereby continuously oscillating, in other words, the change of the current source is equivalent to the change of the flip threshold voltage, and the change direction of the current source of adjacent inverter units 201 is opposite, and the change direction of the flip threshold voltage is also opposite, which helps the ring-shaped oscillation circuit to avoid the degenerate working point, so that the ring-shaped oscillation circuit continuously oscillates, as shown in Figure 2The waveforms of each stage generated by the ring oscillator circuit are shown in FIG. 3. In FIG. 3, INPUT is the waveform of the enable signal, and OSC_OUT is the waveform of the output of the ring oscillator circuit. Figure 2

[0042] In some embodiments, the current value of the first bias current is equal to the current value of the second bias current.

[0043] In this example, since the current value of the first bias current is equal to the current value of the second bias current, in the two inverter units 201 connected to the first end, the current value of the first bias current of the two inverter units 201 is twice the current value of the second bias current of the two inverter units 201; similarly, in the inverter unit 201 connected to the second end, the current value of the second bias current of the two inverter units 201 is twice the current value of the first bias current of the two inverter units 201.

[0044] In some embodiments, the inverter unit 201 can include a first switch tube M1 and a second switch tube M2, the gate of the first switch tube M1 is connected to the gate of the second switch tube M2, the drain of the first switch tube M1 is connected to the drain of the second switch tube M2, the source of the first switch tube M1 is connected to the corresponding current pull-up unit 202, the source of the second switch tube M2 is connected to the current pull-down unit 203, and the connection end of the gate of the first switch tube M1 and the gate of the second switch tube M2 is the voltage input end of the inverter unit 201, and the connection end of the drain of the first switch tube M1 and the drain of the second switch tube M2 is the voltage output end of the inverter unit 201.

[0045] ​In the embodiment, the first switch tube M1 is a P-MOS tube, and the second switch tube M2 is an N-MOS tube. One inverter unit 201 corresponds to a first end of the source of the first switch tube M1 and a connection end of the current pull-up unit 202. One inverter unit 201 corresponds to a second end of the source of the second switch tube M2 and a connection end of the current pull-down unit 203. When two adjacent inverter units 201 are connected, the drain of the first switch tube M1 in a previous inverter unit 201 is connected to the gate of the first switch tube M1 in a subsequent inverter unit 201. Alternatively, the drain of the second switch tube M2 in the previous inverter unit 201 is connected to the gate of the second switch tube M2 in the subsequent inverter unit 201. The previous inverter unit 201 refers to the inverter unit 201 close to the first position among the two adjacent inverter units 201, and the subsequent inverter unit 201 refers to the inverter unit 201 close to the last position among the two adjacent inverter units 201. When the first inverter unit 201 is connected to the last inverter unit 201, the drain of the first switch tube M1 in the last inverter unit 201 is connected to the gate of the first switch tube M1 in the first inverter unit 201. Alternatively, the drain of the second switch tube M2 in the last inverter unit 201 is connected to the gate of the second switch tube M2 in the first inverter unit 201. The drain of the second switch tube M2 in the last inverter unit 201 is the output end of the first voltage signal.

[0046] As shown in Figure 1 , Figure 1 INV1 in the figure is the voltage signal output by the last inverter unit 201, that is, the first voltage signal. INV2 is the voltage signal output by the first inverter unit 201. INV3 is the voltage signal output by the second inverter unit 201. When INV1 is a high-level signal, INV2 outputs a low-level signal, and INV3 outputs a high-level signal. At this time, INV1 is pulled down to form an oscillation loop.

[0047] In some embodiments, as shown in Figure 1 , the current pull-up unit 202 includes a third switch tube M3. The source of the third switch tube M3 is connected to the first power supply end VDD. The gate of the third switch tube M3 is connected to the first current output end. The drain of the third switch tube M3 is connected to the source of the corresponding first switch tube M1.

[0048] In the embodiment, the third switch tube M3 is a P-MOS tube. The first bias current output by the first current output end is output to the first switch tube M1 in the corresponding inverter unit 201 through the third switch tube M3. The third switch tube M3 as a P-MOS tube plays a role in stabilizing the current.

[0049] In some embodiments, as shown inFigure 1 As shown, the current pull-down unit 203 includes a fourth switch tube M4, the drain of the fourth switch tube M4 is connected with the source of the corresponding second switch tube M2, the gate of the fourth switch tube M4 is connected with the second current output end, and the source of the fourth switch tube M4 is grounded.

[0050] In the embodiment, the fourth switch tube M4 is an N-MOS tube, the second bias current output by the second current output end is output to the second switch tube M2 in the corresponding inverter unit 201 through the fourth switch tube M4, and the fourth switch tube M4 as an N-MOS tube plays a role of stabilizing current.

[0051] In some embodiments, as shown in FIG. 2, the bias module 100 includes a first current mirror, the first current mirror includes a first end, a second end, a third end and a fourth end, the first end is connected with the first power supply end, the second end is grounded, the third end is the first current output end, and the fourth end is the second current output end. Figure 1

[0052] In the embodiment, the current mirror mode is adopted when the first bias current and the second bias current are generated, so that the structure of the bias module 100 is simpler; and the first bias current and the second bias current generated by the first current mirror are fixed and equal currents, so that the mode of providing bias current by the first current mirror makes the flip threshold voltage of each inverter unit 201 in the ring oscillator circuit also fixed.

[0053] In some embodiments, as shown in FIG. 2, the first current mirror can include a first current source I1, a fifth switch tube M5, a sixth switch tube M6 and a seventh switch tube M7; the gate of the fifth switch tube M5 is connected with the drain of the fifth switch tube M5, the drain of the fifth switch tube M5 is also connected with the first current source I1, the source of the fifth switch tube M5 is connected with the source of the sixth switch tube M6, and the gate of the fifth switch tube M5 is connected with the gate of the sixth switch tube M6; the drain of the sixth switch tube M6 is connected with the drain of the seventh switch tube M7, the source of the seventh switch tube M7 is connected with the first current source I1, and the gate of the seventh switch tube M7 is connected with the drain of the seventh switch tube M7; wherein the source of the fifth switch tube M5 is the first end of the first current mirror, the gate of the sixth switch tube M6 is the third end of the first current mirror, the gate of the seventh switch tube M7 is the fourth end of the first current mirror, and the source of the seventh switch tube M7 is the second end of the first current mirror. Figure 1

[0054] ​​In this example, the fifth switch M5 is a P-MOS transistor, the sixth switch M6 is a P-MOS transistor, and the seventh switch M7 is an N-MOS transistor. When the fifth switch M5, the sixth switch M6, and the seventh switch M7 are turned on, the first current output terminal outputs a first bias current, and the second current output terminal outputs a second bias current. That is, the gate of the sixth switch M6 outputs the first bias current, and the gate of the seventh switch M7 outputs the second bias current.

[0055] In some embodiments, such as Figure 1 As shown, the oscillation signal output module 300 may include a first inverter 302, an eighth switch M8, and a first NAND gate 301; wherein, the first inverter 302 is used to receive an enable signal; the gate of the eighth switch M8 is connected to the output terminal of the first inverter 302, the source of the eighth switch M8 is grounded, and the drain of the eighth switch M8 is connected to the last inverter unit 201; the first input terminal of the first NAND gate 301 is connected to the input terminal of the first inverter 302, and the second input terminal of the first NAND gate 301 is connected to the last inverter unit 201.

[0056] Specifically, the eighth switch M8 is an N-MOS transistor, and the output of the first NAND gate 301 is the output of the ring oscillator circuit. The enable signal is a square wave signal, which is input through the input of the first inverter 302. Figure 2 As shown, when the enable signal is a high-level signal, the first NAND gate 301 outputs a high-level signal, and when the enable signal is a low-level signal, the first NAND gate 301 outputs a low-level signal. Therefore, when the enable signal is a square wave signal, the ring oscillator circuit can generate an oscillation signal.

[0057] In some embodiments, the present invention also provides a ring oscillator, including the ring oscillator circuit described above.

[0058] In this embodiment, the ring oscillation circuit may include a bias module 100, a ring oscillation module 200, and an oscillation signal output module 300.

[0059] The bias module 100 includes a first current output terminal for outputting a first bias current and a second current output terminal for outputting a second bias current. The ring oscillation module 200 includes 2n+1 cascaded inverter units 201, where n is a positive integer. Each inverter unit 201 is equipped with a current pull-up unit 202 and a current pull-down unit 203. The current pull-up unit 202 is connected to the first current output terminal and the corresponding inverter unit 201, respectively. The current pull-down unit 203 is connected to the second current output terminal and the corresponding inverter unit 201, respectively. The connection terminal between each inverter unit 201 and the corresponding current pull-up unit 202 is the first... Each inverter unit 201 is connected to its corresponding current pull-down unit 203 at a second terminal. Starting from the first inverter unit 201, 2n inverter units 201 are connected sequentially by connecting the first terminals of two adjacent inverter units 201 together and the second terminals of two other adjacent inverter units 201 together. The second terminal of the last inverter unit 201 is connected to the second terminal of the first inverter unit 201. The last inverter unit 201 is used to output a first voltage signal. The oscillation signal output module 300 is connected to the last inverter unit 201. The oscillation signal output module is used to receive the first voltage signal and an enable signal, and output an oscillation signal according to the first voltage signal and the enable signal.

[0060] Specifically, n can be a positive integer such as 1, 2, 3, 4, 5, 6, etc. For example... ​ As shown, when the enable signal is input, a square wave signal can be used as the enable signal. The connection of the first terminals of two adjacent inverter units 201 means that the first terminal of one inverter unit 201 is connected to the first terminal of the other inverter unit 201; similarly, the connection of the second terminals of two adjacent inverter units 201 means that the second terminal of one inverter unit 201 is connected to the second terminal of the other inverter unit 201.

[0061] In the ring-shaped oscillation circuit, 2n+1 inverter units 201 are connected in cascade, and 2n inverter units 201 are connected in sequence from the first inverter unit 201, with the first ends of two adjacent inverter units 201 connected and the second ends of another two adjacent inverter units 201 connected, and the second end of the last inverter unit 201 connected to the second end of the first inverter unit 201. The current source of the two current pull-up units 202 connected through the first end is increased, the current source of the two current pull-down units 203 corresponding to the two current pull-up units 202 is unchanged, the current source of the two current pull-down units 203 connected through the second end is increased, and the current source of the two current pull-up units 202 corresponding to the two current pull-down units 203 is unchanged. Therefore, the first bias current and the second bias current on the same inverter unit 201 are different in size, the first bias current and the second bias current of adjacent two inverter units 201 are different in proportion, the steady-state working point of the negative feedback loop is equivalent to be destroyed, and continuous oscillation is achieved.

[0062] Here, it should be pointed out that the description of the above ring-shaped oscillator embodiment is similar to the description of the above ring-shaped oscillation circuit embodiment, and has similar beneficial effects as the above ring-shaped oscillation circuit. For technical details not disclosed in the ring-shaped oscillator embodiment, please refer to the description of the ring-shaped oscillation circuit embodiment of the utility model for understanding.

[0063] In summary, the ring-shaped oscillation circuit and the oscillator provided by the utility model have the following effects:

[0064] In the ring-shaped oscillation circuit, 2n+1 inverter units 201 are connected in cascade, and 2n inverter units 201 are connected in sequence from the first inverter unit 201, with the first ends of two adjacent inverter units 201 connected and the second ends of another two adjacent inverter units 201 connected, and the second end of the last inverter unit 201 connected to the second end of the first inverter unit 201. The current source of the two current pull-up units 202 connected through the first end is increased, the current source of the two current pull-down units 203 corresponding to the two current pull-up units 202 is unchanged, the current source of the two current pull-down units 203 connected through the second end is increased, and the current source of the two current pull-up units 202 corresponding to the two current pull-down units 203 is unchanged. Therefore, the first bias current and the second bias current on the same inverter unit 201 are different in size, the first bias current and the second bias current of adjacent two inverter units 201 are different in proportion, the steady-state working point of the negative feedback loop is equivalent to be destroyed, and continuous oscillation is achieved.

[0065] It can be understood that the above embodiments only express the preferred embodiments of the present application, the description is more specific and detailed, but it cannot be understood as the limitation of the scope of the present application patent; it should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, the above technical features can be freely combined, and some deformations and improvements can be made, which belong to the protection scope of the present application; therefore, any equivalent transformation and modification within the scope of the claims of the present application shall belong to the scope of the claims of the present application.

Claims

1. A ring oscillator circuit, characterized by, The application relates to a ring oscillator circuit. The bias module comprises a first current output end for outputting a first bias current and a second current output end for outputting a second bias current; The ring oscillation module comprises 2n+1 in-line invertor units, n is a positive integer, each of the invertor units is provided with a current pull-up unit and a current pull-down unit, the current pull-up unit is connected with the first current output end and the corresponding invertor unit, the current pull-down unit is connected with the second current output end and the corresponding invertor unit, wherein the connection end of each invertor unit and the corresponding current pull-up unit is a first end, the connection end of each invertor unit and the corresponding current pull-down unit is a second end, 2n invertor units are connected in sequence by connecting two adjacent invertor units in the first end and connecting another two adjacent invertor units in the second end, the connection end of the last invertor unit and the current pull-down unit is connected to the connection end of the first invertor unit and the current pull-down unit, and the last invertor unit is used for outputting a first voltage signal; The oscillation signal output module is connected with the last invertor unit, the oscillation signal output module is used for receiving the first voltage signal and an enable signal and outputting an oscillation signal according to the first voltage signal and the enable signal.

2. The ring oscillator circuit of claim 1, wherein, The current value of the first bias current is equal to that of the second bias current.

3. Ring oscillator circuit according to claim 1 or 2, characterized in that The invertor unit comprises a first switch tube and a second switch tube, the gate of the first switch tube is connected with the gate of the second switch tube, the drain of the first switch tube is connected with the drain of the second switch tube, the source of the first switch tube is connected with the corresponding current pull-up unit, the source of the second switch tube is connected with the current pull-down unit, the connection end of the gate of the first switch tube and the gate of the second switch tube is a voltage input end of the invertor unit, and the connection end of the drain of the first switch tube and the drain of the second switch tube is a voltage output end of the invertor unit.

4. The ring oscillator circuit of claim 3, wherein, The current pull-up unit comprises a third switch tube, the source of the third switch tube is connected with a first power supply end, the gate of the third switch tube is connected with the first current output end, and the drain of the third switch tube is connected with the source of the corresponding first switch tube.

5. The ring oscillator circuit of claim 4, wherein, The current pull-down unit comprises a fourth switch tube, the drain of the fourth switch tube is connected with the source of the corresponding second switch tube, the gate of the fourth switch tube is connected with the second current output end, and the source of the fourth switch tube is grounded.

6. The ring oscillator circuit of claim 1, wherein, The bias module comprises a first current mirror, the first current mirror comprises a first end, a second end, a third end and a fourth end, the first end is connected with a first power supply end, the second end is grounded, the third end is the first current output end, and the fourth end is the second current output end.

7. The ring oscillator circuit of claim 6, wherein, The first current mirror comprises a first current source, a fifth switch tube, a sixth switch tube and a seventh switch tube. The gate of the fifth switch tube is connected with the drain of the fifth switch tube, the drain of the fifth switch tube is also connected with the first current source, the source of the fifth switch tube is connected with the source of the sixth switch tube, and the gate of the fifth switch tube is connected with the gate of the sixth switch tube; The drain of the sixth switch tube is connected with the drain of the seventh switch tube, the source of the seventh switch tube is connected with the first current source, and the gate of the seventh switch tube is connected with the drain of the seventh switch tube; The source of the fifth switch tube is the first end of the first current mirror, the gate of the sixth switch tube is the third end of the first current mirror, the gate of the seventh switch tube is the fourth end of the first current mirror, and the source of the seventh switch tube is the second end of the first current mirror.

8. The ring oscillator circuit of claim 1, wherein, The oscillation signal output module comprises: a first inverter for accessing an enable signal; an eighth switch tube, the gate of the eighth switch tube being connected with the output end of the first inverter, the source of the eighth switch tube being grounded, and the drain of the eighth switch tube being connected with the last inverter unit; a first NAND gate, the first input end of the first NAND gate being connected with the input end of the first inverter, and the second input end of the first NAND gate being connected with the last inverter unit.

9. A ring oscillator characterized by, comprise: the ring-shaped oscillation circuit according to any one of claims 1-8.

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