Device for superimposing OSD on video stream based on FPGA

Abstract

The utility model relates to a device of video stream superposition OSD based on FPGA relates to video monitoring processing technical field has solved the problem that the flexibility of existing device of video stream superposition OSD based on FPGA is inferior. The device of video stream superposition OSD based on FPGA is composed of line field synchronism separator, FPGA, SRAM and FLASH device, wherein, the input of line field synchronism separator is connected with the output of camera, and the output of line field synchronism separator is connected with the input of FPGA, line field synchronism separator is connected with FPGA communication, and FPGA is bidirectionally connected with SRAM, FLASH device communication respectively.

Description

TECHNICAL FIELD

[0001] The utility model relates to video monitoring processing technical field especially relates to a device of video stream superposition OSD based on FPGA. BACKGROUND

[0002] OSD (On Screen Display) is a kind of electronic device applied on TV or monitor, which can superimpose character information or special graphics on screen, and can provide users with some information.In recent years, with the rapid development of market economy, video monitoring system plays more and more important role in bank, road bridge monitoring, water conservancy, shipping traffic control, large enterprise, public security, fire control, community security, visual intercommunication, intelligent community information release and other fields.OSD provides friendly man-machine interface for users, and is widely used in video monitoring system, data acquisition and display, information release and other fields.

[0003] The OSD scheme realized by Xilinx FPGA has the characteristics of low cost and high reliability.However, the solution of FPGA is usually customized for specific application, which limits the portability of design to some extent, and reduces the reusability between different projects or products.

[0004] Therefore, how to customize different communication interfaces and the number of video superposition channels according to the composition of different OSD devices to realize the flexibility of video stream superposition OSD device based on FPGA is a technical problem to be solved at present. CONTENT OF UTILITY MODEL

[0005] In view of the above analysis, the utility model aims at providing a kind of device of video stream superposition OSD based on FPGA to solve the poor flexibility of the existing device of video stream superposition OSD based on FPGA.

[0006] The utility model mainly aims at realizing the following technical scheme:

[0007] A kind of device of video stream superposition OSD based on FPGA, the device is composed of line field synchronizer separator, FPGA, SRAM and FLASH device;Wherein,

[0008] The input end of line field synchronizer separator is connected with the output end of camera, and the output end of line field synchronizer separator is connected with the input end of FPGA;Line field synchronizer separator is communicated with FPGA connection;

[0009] FPGA is bidirectionally communicated with SRAM and FLASH device.

[0010] On the basis of the above scheme, the utility model further makes the following improvements:

[0011] Further, the FPGA communicates with the SRAM through address lines and data lines.

[0012] Further, the FLASH device is connected with the FPGA through an SPI interface.

[0013] Further, the FPGA is an Xilinx FPGA with a third-generation FLASH architecture and a capacity of 60,000 gates.

[0014] Further, a line field sync separator is used to separate a line sync signal and a field sync signal from a video signal output by the camera.

[0015] Further, the FPGA is used to determine screen coordinates according to the line sync signal and the field sync signal output by the line field sync separator, and to superimpose the character information to be superimposed stored in the SRAM at the determined screen coordinates.

[0016] Further, the SRAM is used as a display cache to store the character information to be superimposed, and to display the characters according to the data stream output by the line counter and the field counter.

[0017] Further, the SRAM comprises a basic storage unit, an address decoder, and a buffer / drive circuit.

[0018] The basic storage unit of the SRAM is usually composed of six transistors, forming two cross-coupled inverters, constituting a bistable circuit, for stably maintaining the state of the stored data.

[0019] The address decoder is used to convert the address signal of the stored data into corresponding row selection signals and column selection signals, so as to select a specific storage unit.

[0020] The buffer / drive circuit is used to drive the data bus, realizing the transmission of data between the SRAM and the FPGA.

[0021] Further, the FLASH device is used to store a font library, and the number of character dot matrices stored in the font library determines the number of characters that can be superimposed.

[0022] The FLASH device is a NOR Flash.

[0023] Compared with the prior art, the utility model has at least one of the following beneficial effects:

[0024] The device for superimposing OSD on video stream based on FPGA comprises a horizontal field synchronism separator, an FPGA, an SRAM and a FLASH device, wherein the horizontal field synchronism separator and the SRAM are in communication connection with the FPGA, and the FLASH device is in communication connection with the FPGA through an SPI interface.

[0025] The above technical solutions can be combined with each other to realize more preferred combination solutions. BRIEF DESCRIPTION OF DRAWINGS

[0026] The drawings are only for the purpose of illustrating specific embodiments and are not considered as limiting the present application, and the same reference signs represent the same components throughout the drawings.

[0027] Figure 1 The device for superimposing OSD on video stream based on FPGA provided by the present application is shown in the structural schematic view. DETAILED DESCRIPTION

[0028] The preferred embodiments of the present application will be described in detail below with reference to the drawings, wherein the drawings form a part of the present application and are used to explain the principles of the present application together with the embodiments of the present application, and are not used to limit the scope of the present application.

[0029] One specific embodiment of the present application discloses a device for superimposing OSD on video stream based on FPGA, and a structural schematic view is shown in figure 1. In the embodiment, the device for superimposing OSD on video stream based on FPGA comprises a horizontal field synchronism separator, an FPGA, an SRAM and a FLASH device; wherein the input end of the horizontal field synchronism separator is connected with the output end of a camera, and the output end of the horizontal field synchronism separator is connected with the input end of the FPGA; the horizontal field synchronism separator is in communication connection with the FPGA; and the FPGA is in bidirectional communication connection with the SRAM and the FLASH device. The connection relationship constitutes the core architecture of the device for superimposing OSD on video stream based on FPGA, so that the device can flexibly process video signals and dynamically superimpose character information on video stream.

[0030] Line field sync separator, for separating line sync signal and field sync signal from the video signal output by the camera, to ensure the synchronization of the video signal.

[0031] FPGA, for determining the screen coordinates according to the line sync signal and the field sync signal output by the line field sync separator; and superimposing the character information to be superimposed stored in the SRAM at the determined screen coordinates; to perform the actions of clearing the screen, flashing, etc. When the line counter and the field counter inside the FPGA count to the specified line and column, the data stream in the SRAM is output, and the corresponding character information is displayed on the screen.

[0032] SRAM, as a display cache, stores the character information to be superimposed, and displays the characters according to the data stream output by the line counter and the field counter. Specifically, the FPGA communicates with the SRAM through address lines and data lines, and reads data from the SRAM and superimposes characters at the specified position on the screen according to the timing of the line sync signal and the field sync signal. The SRAM has a basic storage unit, an address decoder, and a buffer / drive circuit built-in. The basic storage unit of the SRAM is usually composed of 6 transistors, forming two cross-coupled inverters, constituting a bistable circuit, for stably maintaining the state of the stored data; the address decoder is used to convert the address signal of the stored data into corresponding row selection signal and column selection signal, to select a specific storage unit; the buffer / drive circuit is used to drive the data bus, to realize the transmission of data between the SRAM and the FPGA.

[0033] FLASH device, for storing the font library, the number of character matrices stored in the font library determines the number of characters that can be superimposed. The FLASH device is connected to the FPGA in communication through an SPI interface. The SPI interface is a kind of serial communication protocol, usually including MISO (master data input / slave data output), MOSI (master data output / slave data input), SCLK (clock signal) and CS (chip select signal). The FPGA exchanges data with the FLASH device through these signals, and reads the font library information stored in the FLASH. Preferably, the FLASH device is NOR Flash.

[0034] In the embodiment, the FPGA adopts the third generation FLASH architecture of Actel Company, Xilinx FPGA with a capacity of 60,000 gates, which has good flexibility, and can customize the communication interface, the number of video superposition channels and the font size according to the user demand. At the same time, the firmware immune characteristics of Xilinx FPGA make the system can work in outdoor, industrial control occasions and in harsh environment. The application requirement is used to customize the font and size of the display character. The FPGA receives the data from the MCU, and determines the screen coordinates according to the line field synchronization signal, and executes the character superposition, screen clearing, flickering and other actions. The logic inside the FPGA can be customized according to the need to adapt to different communication interfaces, video superposition channel numbers and font sizes.

[0035] In the implementation process, the operation timing of the FLASH with SPI interface is simple, and the I / O resources of the FPGA can be saved. When the font library needs to be replaced, the font library can be directly downloaded into the FLASH or the FLASH device storing the font library information can be directly replaced, which can meet the needs of different applications and costs, and has good expansibility. In the OSD device, the font library is stored in the FLASH with SPI interface in the format of binary BIN file. The user can customize the font library size, the character dot matrix size in the font library and other icons and special symbols according to different needs. The embodiment also provides font library generation software, and the user can generate the font library file through the software.

[0036] In the television system, in order to correctly reproduce the image, the receiving end and the sending end need to be synchronized. As long as the scanning frequency of the receiving end and the sending end is the same, and the starting phase is the same, the receiving end can reproduce the image of the sending end. Therefore, it is necessary to add the line field synchronization signal in the image signal to ensure that the receiving end and the sending end can be synchronized. In the implementation process, in order to superimpose characters on the video signal output by the camera, it is necessary to obtain the synchronization signal with the same frequency and phase as the sending end, so it is necessary to separate the synchronization signal of the sending end by the line field synchronization separator, and the video signal output by the camera is separated into line synchronization signal and field synchronization signal by the line field synchronization separator.

[0037] The SRAM can also select different capacities according to different application requirements to meet the needs of different applications and costs. The font library is an important part of the OSD device, and the number of characters stored in the font library and the organization form of the characters determine whether the font library is simple and easy to use.

[0038] OSD is widely used in video monitoring and information publishing field, such as character superimposition in high-speed ball, closed-circuit television monitoring system, data acquisition display and information display in industrial control video monitoring, video matrix, character superimposition of intelligent cloud platform decoder, character superimposition of point counting machine, character superimposition of toll station video, character superimposition of temperature and humidity video, character superimposition of digital compass, video advertisement of passenger car and short message publishing of visual system of intelligent community, etc. The OSD scheme realized by the Xilinx FPGA has the characteristics of high flexibility, low cost, high reliability and customization. The Xilinx FPGA adopts FLASH architecture and has the characteristics of non-volatile power failure. Once programming is completed, the configuration data will become the inherent part of the FPGA structure, and the chip is not required, so that the system cost is more low. The FPGA of Xilinx architecture has good immunity to firmware errors, so that the system can work in a relatively harsh environment or a high stability requirement occasion. The customization feature is a highlight of the OSD scheme realized by the Xilinx FPGA, which can reflect the flexibility of the FPGA video stream superposition OSD device. At the same time, the flexibility of the product is one of the survival standards of the product in the market. When the OSD scheme is realized by the Xilinx FPGA, different communication interfaces and video superposition channel numbers can be customized according to different OSD device compositions, user requirements, and font library size, character size and video channel.

[0039] The above is only a preferred specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any skilled person in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application.

Claims

1. A device for overlaying OSD onto a video stream based on an FPGA, characterized in that, The device consists of a horizontal and vertical synchronization separator, an FPGA, SRAM, and FLASH devices; wherein... The input of the horizontal and vertical sync splitter is connected to the output of the camera, and the output of the horizontal and vertical sync splitter is connected to the input of the FPGA; the horizontal and vertical sync splitter is communicatively connected to the FPGA. The FPGA has bidirectional communication connections with both SRAM and FLASH devices.

2. The device for overlaying OSD onto a video stream based on FPGA according to claim 1, characterized in that, FPGAs communicate with SRAM via address lines and data lines.

3. The device for overlaying OSD onto a video stream based on FPGA according to claim 2, characterized in that, The FLASH device communicates with the FPGA via the SPI interface.

4. The device for overlaying OSD onto a video stream based on FPGA according to claim 3, characterized in that, The FPGA uses a third-generation FLASH architecture and is a Xilinx FPGA with a capacity of 60,000 gates.

5. The apparatus for overlaying OSD onto a video stream based on FPGA according to any one of claims 1-4, characterized in that, A line and field sync separator is used to separate line sync signals and field sync signals from the video signal output by a camera.

6. The device for overlaying OSD onto a video stream based on FPGA according to claim 5, characterized in that, The FPGA is used to determine the screen coordinates based on the horizontal and vertical synchronization signals output by the horizontal and vertical synchronization splitter; and to overlay the character information to be overlaid stored in SRAM at the determined screen coordinates.

7. The device for overlaying OSD onto a video stream based on FPGA according to claim 6, characterized in that, SRAM serves as a display buffer, storing the character information to be overlaid and displaying the characters based on the data stream output from the line counter and field counter.

8. The device for overlaying OSD onto a video stream based on FPGA according to claim 7, characterized in that, SRAM integrates the basic SRAM storage cells, address decoder, and buffer / drive circuitry; among which... The basic storage cell of SRAM consists of 6 transistors, forming two cross-coupled inverters, which together form a bistable circuit to stably maintain the state of the stored data. Buffer / Driver Circuit: Used to drive the data bus and enable data transfer between SRAM and FPGA.

9. The device for overlaying OSD onto a video stream based on FPGA according to claim 8, characterized in that, FLASH devices are used to store character sets, and the number of character dot matrices stored in the character set determines the number of characters that can be superimposed.

10. The device for overlaying OSD onto a video stream based on FPGA according to claim 9, characterized in that, The FLASH device used is NOR Flash.

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