Plane gate silicon carbide VDMOS integrated with JBS

Abstract

The utility model provides a planar gate silicon carbide VDMOS integrated with a JBS. The planar gate silicon carbide VDMOS is characterized in that a first drift layer is connected to a silicon carbide substrate; the current sharing layer is connected to the first drift layer, and the current sharing layer is provided with a protruding part; the second drift layer is connected to the current equalizing layer, and the inner side surface of the second drift layer is connected to the outer side surface of the lug boss; the first P-type well region is connected to the second drift layer, and the inner side surface of the first P-type well region is connected to the outer side surface of the lug boss; an N-type source region is arranged on the first P-type well region; the Schottky region is connected to the second drift layer, a plurality of second P-type well regions are uniformly arranged in the Schottky region at intervals, and the second P-type well regions are connected to the second drift layer; the insulating dielectric layer is connected to the first P-type well region and the lug boss; the source metal layer is respectively connected with the Schottky region, the second P-type well region, the first P-type well region and the N-type source region; the gate metal layer is connected to the insulating dielectric layer; the drain metal layer is connected to the silicon carbide substrate, the freewheeling capability of the body diode is improved, and the loss of the body diode is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of plane grid silicon carbide VDMOS integrated JBS. BACKGROUND

[0002] Silicon carbide VDMOS is the typical representative of silicon carbide power device, and has wide application in electric vehicle, aerospace, power conversion and other fields.For silicon carbide power VDMOS, its performance requirements in different fields are different, but the general requirements are higher withstand voltage, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), lower body diode conduction loss.

[0003] Especially in the field of switching power supply, with the increase of switching speed, the proportion of body diode freewheeling time in the total on-time of the device is higher and higher, and reducing the loss of body diode freewheeling of the device and improving the reverse recovery speed of the device are more and more important to reduce the loss of the device, and the body diode needs to be optimized. INVENTION CONTENTS

[0004] The technical problem to be solved by the utility model is to provide a plane grid silicon carbide VDMOS integrated JBS, which improves the body diode freewheeling capability, reduces the body diode loss and improves the reliability of the device.

[0005] In the first aspect, the utility model provides a plane grid silicon carbide VDMOS integrated JBS, which comprises:

[0006] Silicon carbide substrate,

[0007] First drift layer, the lower side of the first drift layer is connected to the upper side of the silicon carbide substrate;

[0008] Current sharing layer, the lower side of the current sharing layer is connected to the first drift layer, and the current sharing layer is provided with a protruding portion on the upper side;

[0009] Second drift layer, the lower side of the second drift layer is connected to the upper side of the current sharing layer, and the inner side of the second drift layer is connected to the outer side of the protruding portion;

[0010] First P-type well region, the lower side of the first P-type well region is connected to the upper side of the second drift layer, and the inner side of the first P-type well region is connected to the outer side of the protruding portion; the first P-type well region is provided with an N-type source region on the upper side;

[0011] Schottky region, the lower side of the Schottky region is connected to the upper side of the second drift layer, and a plurality of second P-type well regions are uniformly and spacedly arranged in the Schottky region; the lower side of the second P-type well region is connected to the upper side of the second drift layer;

[0012] An insulating medium layer, a lower side of which is connected to an upper side of the first P-type well region and an upper side of the protruding part;

[0013] A source metal layer, which is connected to the Schottky region, the second P-type well region, the first P-type well region and the N-type source region respectively;

[0014] A gate metal layer, a lower side of which is connected to an upper side of the insulating medium layer;

[0015] And a drain metal layer, which is connected to a lower side of the silicon carbide substrate.

[0016] The utility model has the advantages of:

[0017] First, the Schottky region and the second P-type well region of the utility model cross and contact the source metal layer, which can realize the JBS structure of the Schottky junction and the pn junction of the device body diode on the basis of ensuring the voltage resistance capability of the device, the mode realizes the Schottky low voltage freewheeling of the body diode freewheeling, and can ensure the large current freewheeling capability of the body diode, reduces the conduction loss, reduces the number of hole conduction of the device body diode freewheeling at the same time, and can inhibit the bipolar degradation effect of the device caused by hole conduction;

[0018] Second, the depth of the second P-type well region of the utility model is greater than the depth of the Schottky region, which can realize the wrapping of the Schottky region in the device reverse voltage resistance, thereby ensuring the reverse voltage resistance capability of the device;

[0019] Third, the current sharing layer of the utility model is used for distributing the electrons moving from the JFET region of the device horizontally, reducing the on-resistance of the device and shielding the capacitance from the gate to the drain of the device, reducing the Miller capacitance, reducing the driving loss of the device and improving the switching speed of the device; the protruding part is used for reducing the on-resistance of the JFET region of the device;

[0020] Fourth, the protruding part, the first P-type well region and the second P-type well region of the utility model are matched, which can effectively inhibit the voltage impact when the drain is connected to high voltage on the basis of reducing the on-resistance of the device, and improve the reliability of the device;

[0021] Fifth, the N-type current sharing layer and the first P-type well region of the utility model have a second drift layer of 500nm-1um, which is used for decoupling the gate structure and the current sharing layer of the device, and ensuring the high reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0022] The utility model will be further described in connection with the embodiments with reference to the drawings.

[0023] Figure 1The utility model discloses a kind of integrated JBS's plane grid silicon carbide VDMOS's schematic diagram.

[0024] Figure 2 The utility model discloses a kind of integrated JBS's plane grid silicon carbide VDMOS's process section view Figure 1 .

[0025] Figure 3 The utility model discloses a kind of integrated JBS's plane grid silicon carbide VDMOS's process section view Figure 2 .

[0026] Figure 4 The utility model discloses a kind of integrated JBS's plane grid silicon carbide VDMOS's process section view Figure 3 .

[0027] Figure 4 The utility model discloses a kind of integrated JBS's plane grid silicon carbide VDMOS's process section view Figure 5 .

[0028] Figure 4 The utility model discloses a kind of integrated JBS's plane grid silicon carbide VDMOS's process section view Figure 5 .

[0029] Figure 6 The utility model discloses a kind of integrated JBS's plane grid silicon carbide VDMOS's process section view Figure 5 .

[0030] Figure 6 The utility model discloses a kind of integrated JBS's plane grid silicon carbide VDMOS's process section view Figure 7 .

[0031] Figure 6 The utility model discloses a kind of integrated JBS's plane grid silicon carbide VDMOS's process section view Figure 7 .

[0032] Figure 8 The utility model discloses a kind of integrated JBS's plane grid silicon carbide VDMOS's process section view Figure 7 .

[0033] Figure 8 The utility model discloses a kind of integrated JBS's plane grid silicon carbide VDMOS's process section view Figure 9 . Specific embodiment

[0034] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.

[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0038] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof. Also, in the present specification, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] As shown in Figure 8 The embodiment of the present application provides a planar gate silicon carbide VDMOS integrated with JBS, which comprises:

[0040] a silicon carbide substrate 101,

[0041] a first drift layer 102, a lower side of the first drift layer 102 being connected to an upper side of the silicon carbide substrate 101;

[0042] a current sharing layer 103, a lower side of the current sharing layer 103 being connected to an upper side of the first drift layer 102, and the current sharing layer 103 being provided with a protruding part 1031;

[0043] a second drift layer 104, a lower side of the second drift layer 104 being connected to an upper side of the current sharing layer 103, and an inner side of the second drift layer 104 being connected to an outer side of the protruding part 1031;

[0044] a first P-type well region 105, a lower side of the first P-type well region 105 being connected to an upper side of the second drift layer 104, and an inner side of the first P-type well region 105 being connected to an outer side of the protruding part 1031, and the first P-type well region 105 being provided with an N-type source region 1051;

[0045] a Schottky region 106, a lower side of the Schottky region 106 being connected to an upper side of the second drift layer 104, and a plurality of second P-type well regions 1061 being uniformly and spacedly arranged in the Schottky region 106, and a lower side of each of the second P-type well regions 1061 being connected to an upper side of the second drift layer 104;

[0046] an insulating medium layer 107, a lower side of the insulating medium layer 107 being connected to an upper side of the first P-type well region 105 and an upper side of the protruding part 1031;

[0047] a source metal layer 108, the source metal layer 108 being connected to the Schottky region 106, the second P-type well regions 1061, the first P-type well region 105 and the N-type source region 1051 respectively;

[0048] a gate metal layer 109 connected to the upper side of the insulating medium layer 107;

[0049] and a drain metal layer 110 connected to the lower side of the silicon carbide substrate 101.

[0050] In this embodiment, preferably, the doping concentration of the current sharing layer 103 is greater than that of the first drift layer 102 and the second drift layer 104.

[0051] In this embodiment, preferably, the doping concentration of the second P-type well region 1061 is greater than that of the first P-type well region 105.

[0052] In this embodiment, preferably, the thickness of the Schottky region 106 is less than that of the second P-type well region 1061, and the second P-type well region 1061 is arranged in the recesses in the second drift layer 104.

[0053] In this embodiment, preferably, the thickness of the second drift layer 104 is 500 nm-1 μm.

[0054] In this embodiment, preferably, the silicon carbide substrate 101, the first drift layer 102, the second drift layer 104, the current sharing layer 103 and the Schottky region 106 are all N-type.

[0055] As shown in Figure 9 Figure 10 Figure 9 Figure 10 Figure 11 Figure 10 Figure 11 Figure 1 Figures 1 to 11 the preparation method of the silicon carbide VDMOS includes the following steps:

[0056] Step 1, depositing a metal layer on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110, and epitaxially growing a drift region 111 on the upper side of the silicon carbide substrate 101;

[0057] Step 2, forming a current sharing layer 103, a first drift layer 102 and a second drift layer 104 by ion implantation on the drift region 111;

[0058] Step 3, forming a barrier layer 112 on the second drift layer 104, etching the barrier layer 112 to form a through hole, and ion implantation on the second drift layer 104 to form a second P-type well region 1061;

[0059] Step 4, removing the original barrier layer 112, re-forming the barrier layer 112, etching the barrier layer 112 to form a through hole, and ion implantation on the second drift layer 104 to form a Schottky region 106;

[0060] Step 5, removing the original barrier layer 112, re-forming the barrier layer 112, etching the barrier layer 112 to form a via hole, ion implantation to the second drift layer 104, forming the protrusion 1031;

[0061] Step 6, removing the original barrier layer 112, re-forming the barrier layer 112, etching the barrier layer 112 to form a via hole, ion implantation to the second drift layer 104, forming the first P-type well region 105;

[0062] Step 7, removing the original barrier layer 112, re-forming the barrier layer 112, etching the barrier layer 112 to form a via hole, ion implantation to the first P-type well region 105, forming the N-type source region 1051;

[0063] Step 8, removing the original barrier layer 112, re-forming the barrier layer 112, etching the barrier layer 112 to form a via hole, depositing to form the insulating medium layer 107;

[0064] Step 9, removing the original barrier layer 112, re-forming the barrier layer 112, etching the barrier layer 112 to form a via hole, depositing metal to form the gate metal layer 109;

[0065] Step 10, removing the original barrier layer 112, re-forming the barrier layer 112, etching the barrier layer 112 to form a via hole, depositing metal to form the source metal layer 108, removing the barrier layer 112, completing the preparation.

[0066] In another embodiment of the utility model, the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm -3 The doping concentration of the first drift layer 102 and the second drift layer 104 is 1-5e16cm -3 The doping concentration of the N-type current sharing layer 103 is 1-5e17cm -3 The doping concentration of the second P-type well region 1061 is 1-2e19cm -3 The doping concentration of the first P-type well region 105 is 1-5e17cm -3 The doping concentration of the N-type Schottky region 106 is 1-5e17cm -3 The material of the gate insulating layer 107 can be silicon dioxide, and the doping concentration of the N-type source region 1051 is 2-8e18cm -3The doping concentration of the N-type silicon carbide substrate 101 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 109, and to reduce the overall on-resistance of the device; the doping concentration of the first drift layer 102 and the second drift layer 104 is a compromise between the reverse voltage withstand capability and the on-resistance of the device; the doping concentration of the N-type current-sharing layer 103 is designed with two considerations, one is to achieve current sharing in the body of the device and reduce the on-resistance of the device, which requires a relatively high doping concentration, and the other is to ensure that the formation of a pn junction with the first P-type well region 105 does not affect the reverse voltage withstand capability of the device, which requires that the doping concentration not be too high; the second P-type well region 1061 can effectively withstand the pn junction voltage of the device when the drain of the device is subjected to a high voltage, and the second P-type well region 1061 and the N-type Schottky region 106 together form a body JBS diode of the device, which can improve the body diode freewheeling capability of the device, reduce the on-resistance of the device, reduce the reverse recovery loss, and suppress the bipolar degradation effect of the device. The relatively low doping of the first P-type well region 105 can reduce the gate reverse voltage of the device, thereby reducing the drive loss of the device.

[0067] The thickness of the N-type silicon carbide substrate 101 is 1 μm, the thickness of the first drift layer 102 is 30-100 μm, which is adjusted within the above range according to different requirements for the voltage withstand capability of the device, the thickness of the N-type current-sharing layer 103 is 500-1000 nm, the thickness of the protruding portion 1031 is 2-3 μm, the thickness of the contact area of the first P-type well region 105 with the insulating medium layer 107 and the source metal layer 108 is 1 μm, the thickness of the contact area with the N-type source region 1051 is 800 nm, and the thickness of the N-type source region 1051 is 200 nm; the thickness of the N-type Schottky region 106 is 600 nm, the thickness of the second P-type well region 1061 is 1 μm, the thickness of the insulating medium layer 107 is 50 nm, the thickness of the gate metal layer 109 is 200 nm, the thickness of the source metal layer 108 is 200-300 nm, the width of the N-type source region 1051 is 50-70% of the width of the first P-type well region 105, the total width of the first P-type well region 105 and the second P-type well region 1061 accounts for 50-60% of the device cell, and the width ratio of the second P-type well region 1061 to the N-type Schottky region 106 is 1:2 to 2:2. This width range is designed to balance the voltage withstand capability and the body diode voltage drop of the device. When the Schottky diode accounts for a large proportion, the body diode voltage drop is low; when the second P-type well region 1061 accounts for a large proportion, the voltage withstand capability of the device can be guaranteed;

[0068] The N-type Schottky region 106 and the second P-type well region 1061 cross and contact the source metal layer 108, can guarantee the JBS structure of the Schottky junction and the pn junction of the device body diode on the basis of realizing the device voltage withstand capability, reduce the hole conduction quantity during the freewheeling of the device body diode, can inhibit the device bipolar degradation effect caused by hole conduction, and can also increase the freewheeling capability of the device body diode, and can also reduce the body diode freewheeling loss of the device;

[0069] The N-type current uniform layer 103 is used for distributing the electrons moving from the device JFET area in a horizontal direction, reducing the on-resistance of the device and shielding the capacitance from the gate to the drain of the device, reducing the Miller capacitance, reducing the device driving loss and improving the switching speed of the device; the protruding part 1031 is used for reducing the on-resistance of the device JFET area; the cooperation of the protruding part 1031, the first P-type well region 105 and the second P-type well region 1061 reduces the on-resistance of the device, effectively inhibits the voltage impact when the drain is connected to high voltage and improves the reliability of the device.

[0070] The second drift layer 104 is arranged between the N-type current uniform layer 103, the first P-type well region 105 and the second P-type well region 1061, the thickness of the second drift layer 104 is 500nm-1μm, the second drift layer 104 realizes the decoupling of the device gate structure and the N-type current uniform layer 103 and guarantees the high reliability of the device.

[0071] Although the specific embodiments of the utility model are described above, those skilled in the art should understand that the specific examples described by us are only illustrative, and are not used to limit the scope of the utility model, and equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the utility model should be covered in the scope of protection of the claims of the utility model.

Claims

1. A planar gate silicon carbide VDMOS with integrated JBS, characterized in that: include: silicon carbide substrate, A first drift layer, wherein the lower side of the first drift layer is connected to the upper side of the silicon carbide substrate; A flow equalization layer, the lower side of which is connected to the first drift layer, and a protrusion is provided on the flow equalization layer; The second drift layer has its lower side connected to the upper side of the flow equalization layer, and its inner side connected to the outer side of the protrusion. A first P-type well region, the lower side of the first P-type well region is connected to the upper side of the second drift layer, and the inner side of the first P-type well region is connected to the outer side of the protrusion; an N-type source region is provided on the first P-type well region. A Schottky region, the lower side of which is connected to the upper side of the second drift layer, and a plurality of second P-type well regions are uniformly spaced within the Schottky region, the lower side of which is connected to the upper side of the second drift layer; An insulating dielectric layer, the lower side of which is connected to the upper side of the first P-type well region and the upper side of the protrusion; A source metal layer, wherein the source metal layer is respectively connected to the Schottky region, the second P-type well region, the first P-type well region and the N-type source region; A gate metal layer, wherein the lower side of the gate metal layer is connected to the upper side of the insulating dielectric layer; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

2. The planar gate silicon carbide VDMOS with integrated JBS as described in claim 1, characterized in that: The doping concentration of the current equalization layer is greater than that of the first drift layer and the second drift layer.

3. The planar gate silicon carbide VDMOS with integrated JBS as described in claim 1, characterized in that: The doping concentration of the second P-type well region is greater than that of the first P-type well region.

4. The planar gate silicon carbide VDMOS with integrated JBS as described in claim 1, characterized in that: The thickness of the Schottky region is less than the thickness of the second P-type well region. The second drift layer has multiple grooves, and the lower part of the second P-type well region is located in the grooves.

5. The planar gate silicon carbide VDMOS with integrated JBS as described in claim 1, characterized in that: The thickness of the second drift layer is 500 nm to 1 μm.

6. The planar gate silicon carbide VDMOS with integrated JBS as described in claim 1, characterized in that: The silicon carbide substrate, the first drift layer, the second drift layer, the current equalization layer, and the Schottky region are all N-type.

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