Semiconductor structure

Abstract

A semiconductor structure in which a p-type doped region surrounding an isolation structure provides additional electrical isolation between pixel sensors of a pixel array. As a result, current leakage from a floating node of one pixel sensor to another pixel sensor is reduced. Therefore, the dark current can be reduced, and the efficiency of the pixel array can be improved. In addition, pixel noise caused by electrons captured in the isolation structure can be reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of semiconductor structure. BACKGROUND

[0002] Complementary metal-oxide-semiconductor (CMOS) image sensors can include a plurality of pixel sensors. A pixel sensor of a CMOS image sensor can include a transfer gate, the pixel sensor can include a photodiode configured to convert photons of incident light into a photo current of electrons and a transfer gate configured to control a flow of the photo current between the photodiode and a drain region. The drain region can be configured to receive the photo current such that the photo current can be measured and / or transferred to other regions of the CMOS image sensor. SUMMARY

[0003] According to an embodiment of the utility model, a semiconductor structure includes a photodiode in a substrate and a floating node including an n-type doped region. The semiconductor structure includes an isolation structure surrounding the photodiode. The semiconductor structure includes a p-type doped region between the n-type doped region of the floating node and the isolation structure and is configured to absorb excess charge from the isolation structure.

[0004] According to another embodiment of the utility model, a semiconductor structure includes a photodiode in a substrate and a transfer gate associated with a drain region. The semiconductor structure includes an isolation structure surrounding the photodiode. The semiconductor structure includes a p-type doped region between the drain region and the isolation structure and is configured to absorb excess charge from the isolation structure. BRIEF DESCRIPTION OF DRAWINGS

[0005] The details of the disclosure can best be understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to the standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion. It is also to be emphasized that the drawings merely illustrate typical embodiments of the utility model and should not be construed as limiting the scope as the utility model can be equally well suited to other embodiments. Moreover, the drawings can implicitly show features which are not explicitly described in the detailed description.

[0006] Figures 1A-1B is a diagram of an example two-chip implementation described herein.

[0007] Figures 1C-1D is a diagram of an example three-chip implementation described herein.

[0008] Figures 2A-2C is a diagram of an example two-pixel implementation described herein.

[0009] Figures 2D-2E is a diagram of an example four-pixel implementation described herein.

[0010] Figure 3 is a diagram of an example isolation structure described herein.

[0011] Figures 4A-4K is a diagram of an example implementation described herein.

[0012] Figures 5A-5I is a diagram of an example implementation described herein.

[0013] Figures 6A-6I is a diagram of an example implementation described herein.

[0014] Figure 7 is a flow diagram of an example process related to forming a semiconductor structure described herein. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments, or examples, for implementing different features of the present application. Specific examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature can include embodiments in which the first feature is formed directly on the second feature, as well as embodiments in which additional features can be formed between the first and second features such that the first and second features are not directly in contact with each other. In addition, the present disclosure can repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0016] Also for ease of description, spatial terms such as "below," "under," "lower," "above," "upper," and the like can be used with respect to the illustrations as shown in the figures. Unless specifically stated otherwise, spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

[0017] Optical crosstalk can occur between adjacent pixel regions in a pixel array. Optical crosstalk is a pixel array performance issue where incident light passes through the pixel sensor at a non-orthogonal angle and is at least partially absorbed by the photodiodes of adjacent pixel sensors. Optical crosstalk in the pixel array of an image sensor reduces the spatial resolution of the image sensor, decreases the overall sensitivity of the image sensor, causes color mixing between pixel sensors, and / or results in image noise after color correction.

[0018] To reduce optical crosstalk, isolation structures such as deep trench isolation (DTI) can be used to surround the pixel sensor. However, any damage caused during the formation of the DTI structure can cause current to leak from the floating diffusion (FD) node of one pixel sensor to another. Some damage can be corrected by thermal annealing; however, the remaining damage will still cause current leakage.

[0019] Some embodiments described herein provide techniques and apparatus for p-type doping around an isolation structure. P-type doping provides additional electrical isolation between pixel sensors. As a result, current leakage from the FD node of one pixel sensor to another is reduced. Therefore, dark current can be reduced, and the performance of the pixel array can be improved. Additionally, pixel noise caused by electrons trapped in the isolation structure can be reduced.

[0020] Figure 1A This is a diagram of the example circuit 100 described herein. Example circuit 100 is shown for use in an image sensor formed across two chips. The image sensor may be a CMOS image sensor, a back-illuminated (BSI) CMOS image sensor, or another type of image sensor.

[0021] like Figure 1A As shown, the first chip 102 includes the front-end components of an image sensor. Signals from the photodiode 104 are controlled by the transmission transistor 106 and transmitted to the floating node (also called the FD node) 108. Additionally, the reset gate 110 uses a voltage represented by Vdd to reset the floating node 108 to zero charge. The first chip 102 also includes back-end wiring (…). Figure 1A (Not shown in the image). For example... Figure 1A As shown, the second chip 116 includes an application-specific integrated circuit (ASIC) 118. The first chip 102 and the second chip 116 can be connected using back-end metal wiring and MM and DD junctions. A source follower (SF) transistor 112 and a row selector (RS) transistor 114 control signals from the floating node 108 to the output of the ASIC 118.

[0022] Figure 1B yes Figure 1A A cross-sectional view of example circuit 100. (See diagram below.)Figure 1B As shown, light is incident on the first chip 102 (e.g., on the back side of the first chip 102). The front side of the chip is bonded to the second chip 116. As a result, the SF transistor 112 and RS transistor 114 formed in the first chip 102 can be electrically connected to the ASIC 118 formed in the second chip 116.

[0023] As mentioned above, providing Figures 1A-1B As an example. Other examples can be found related to... Figures 1A-1B The descriptions differ. For example, to store additional charge from photodiode 104 in a brighter environment, a double conversion gain (DCG) capacitor can be included near floating node 108.

[0024] Figure 1C This is a diagram of the example circuit 150 described herein. Example circuit 150 illustrates an image sensor formed across three chips. The image sensor can be a CMOS image sensor, a BSI CMOS image sensor, or other types of image sensors.

[0025] Example circuit 150 is similar to example circuit 100, except that the first chip 102 includes only a photodiode 104, a transfer transistor 106, and a floating node 108. Therefore, a reset gate 110, an SF transistor 112, and an RS transistor 114 are incorporated into the third chip 152. The third chip 152 is located between the first chip 102 and the second chip 116 and thus connects the photodiode 104 to the ASIC 118.

[0026] Figure 1D yes Figure 1C A cross-sectional view of example circuit 150. (See diagram below.) Figure 1D As shown, light is incident on the first chip 102 (e.g., on the back side of the first chip 102). The front side of the first chip 102 is bonded to the third chip 152, which in turn is bonded to the second chip 116. As a result, the transfer transistor 106 formed in the first chip 102 can be electrically connected to the floating node 108, and then connected via the back end to the SF transistor 112 and RS transistor 114 formed in the third chip 152. Furthermore, the SF transistor 112 and RS transistor 114 can be electrically connected to the ASIC 118 formed in the second chip 116.

[0027] As mentioned above, providing Figures 1C-1D As an example. Other examples may be related to... Figures 1C-1D The descriptions differ. For example, to store additional charge from photodiode 104 under brighter conditions, a DCG capacitor may be included near floating node 108 in first chip 102 or near third chip 152.

[0028] Figure 2A A cross-sectional view of a pixel sensor 200 is shown. As shown, the pixel sensor 200 can include a substrate 202. The substrate 202 can include a semiconductor chip, a semiconductor wafer, or another type of substrate in which a semiconductor pixel can be formed. In some embodiments, the substrate 202 is formed of silicon (Si) (e.g., a silicon substrate), a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), silicon-on-insulator (SOI), or another type of semiconductor material capable of generating an electric charge from a photon of incident light. In some implementations, the substrate 202 is formed of a doped material such as doped silicon (e.g., a p-doped material or an n-doped material). Figure 2A The pixel sensor 200 can include a photodiode 104 contained in the substrate 202. The photodiode 104 can include multiple regions doped with various types of ions to form a pn junction or a PIN junction (e.g., a junction between a p-type site, an intrinsic (or un-doped) type site, and an n-type site). For example, the substrate 202 can be doped with an n-type dopant to form one or more n-type regions of the photodiode 104, and the substrate 202 can be doped with a p-type dopant to form a p-type region of the photodiode 104. The photodiode 104. The photodiode 104 can be configured to absorb photons of incident light. Absorption of the photons causes the photodiode 104 to accumulate an electric charge (referred to as a photo current) due to the photoelectric effect. The photons can bombard the photodiode 104, which can cause emission of electrons in the photodiode 104.

[0029] The pixel sensor 200 can also include a p-type well 204. In some embodiments, the p-type well 204 can allow for formation of an n-type doped region (also referred to as an “n-type source / drain region”) 206 including a floating node 108. Additionally, the pixel sensor 200 can include a drain extension region 208 coupled and / or electrically connected to the n-type doped region 206. The drain extension region 208 can include a lightly doped n-type region that facilitates transfer of the photo current from the photodiode 104 to the n-type doped region 206. Conceptually, the n-type doped region 206 including the floating node 108 and the drain extension region 208 is associated with (and enabled by) a transfer gate 210 (e.g., including a portion of the transfer transistor 106).

[0030]

[0031] ​The transfer gate 210 controls the transfer of photo current between the photodiode 104 and the n-type doped region 206 of the floating node 108. The transfer gate 210 can be energized (e.g., by applying a voltage or current to the transfer gate 210) to cause a conductive channel to form in the substrate 202 between the photodiode 104 and the drain extension region 208. The conductive channel can be removed or turned off by de-energizing the transfer gate 210, which can block and / or prevent the flow of photo current between the photodiode 104 and the drain extension region 208. In some embodiments, the transfer gate 210 includes a polysilicon gate including polysilicon, doped polysilicon (e.g., n-doped polysilicon), or a combination thereof. In some embodiments, the transfer gate 210 includes a metal gate including one or more metals.

[0032] The transfer gate 210 can be included in a dielectric layer 212 over the substrate 202. The dielectric layer 212 can include an intermetallic dielectric (IMD) formed of an oxide material such as silicon oxide (SiO x (e.g., silicon dioxide (SiO2)), silicon nitride (SiN x ), silicon carbide (SiC x ), silicon oxynitride (SiC x ), or another type of dielectric material. x , tantalum nitride (TaN x ), hafnium oxide (HfO x ), tantalum oxide (TaO x ), aluminum oxide (AlO x ), or another type of dielectric material.

[0033] The conductive structure 214 can be electrically connected to the n-type doped region 206 of the floating node 108 so as to allow the transfer of photo current out of the pixel sensor 200 and to the back end of line (BEOL). Similarly, as described above, the conductive structure 216 can be electrically connected to the transfer gate 210 to allow the energizing (and de-energizing) of the transfer gate 210. The conductive structures 214 and 216 can include contact plugs, vias, and / or other types of structures. The conductive structures 214 and 216 can each be filled with a conductive material such as tungsten, cobalt, ruthenium, and / or another type of conductive material.

[0034] A gate dielectric (also referred to as a “gate oxide”) 218 can be included over and / or on a top surface of the substrate 202. The gate dielectric 218 can include a dielectric material such as tetraethyl orthosilicate (TEOS) or another type of dielectric material.

[0035] The photodiode 104 of the pixel sensor 200 can be electrically and optically isolated from an adjacent photodiode through an isolation structure 220 (e.g., a DTI structure). The isolation structure 220 can extend around the photodiode 104 as well as the p-type well 204, the n-type doped region 206, and the drain extension region 208. The isolation structure 220 can include a plurality of interconnecting trenches that extend into the substrate 202. The isolation structure 220 can provide optical isolation between the pixel sensor 200 and an adjacent pixel sensor to reduce an amount of optical cross-talk between the adjacent pixel sensors. In particular, the isolation structure 220 can absorb, refract, and / or reflect incident light, which can reduce an amount of incident light that passes through the pixel sensor 200 into the adjacent pixel sensor and is absorbed by the adjacent pixel sensor. Further, the isolation structure 220 can reflect incident light toward the photodiode 104, which increases an amount of incident light that is absorbed by the photodiode 104 (which increases a quantum efficiency (QE) of the pixel sensor 200).

[0036] The isolation structure 220 can be filled with a first dielectric material 222a. The first dielectric material 222a can be a high-k material that exhibits a dielectric constant of at least 7. For example, the first dielectric material 222a can be aluminum oxide (e.g., AI2O3), zirconium oxide (e.g., ZrO2), hafnium oxide (e.g., HfO2), and / or another type of oxide material. Similarly, the isolation structure 220 can be filled with a second dielectric material 222b. The second dielectric material 222b can be a high-k material that exhibits a dielectric constant of at least 7. For example, the second dielectric material 222b can be aluminum oxide (e.g., AI2O3), zirconium oxide (e.g., ZrO2), hafnium oxide (e.g., HfO2), and / or another type of oxide material. By selecting a dielectric constant of at least 7, the optical isolation provided by the isolation structure 220 is increased - selecting a dielectric constant lower than 7 would decrease performance of the pixel sensor 200 by increasing optical cross-talk and decreasing the QE of the pixel sensor 200.

[0037] The isolation structure 220 can be a full DTI structure in that the isolation structure 220 extends through an entire height of the substrate 202 from a first side (e.g., a top surface or front side) to a second side (e.g., a bottom surface or back surface) of the substrate 202. As such, the isolation structure 220 can absorb, refract, and / or reflect incident light along an entire height or thickness of the substrate 202, which further reduces optical cross-talk and further increases the QE of the pixel sensor 200.

[0038] As Figure 2A As further shown, the film 224 can act as a buffer between the isolation structure 220 and the gate dielectric 218. For example, the film 224 can protect the gate dielectric 218 during formation of the isolation structure 220 (e.g., as described in connection with FIG. 2B). In particular, the film 224 can prevent the gate dielectric 218 from being damaged during formation of the isolation structure 220. Figure 4J(As described). Film 224 may include silicon dioxide, undoped polysilicon, and / or nitride materials, etc. Therefore, film 224 can be used as an etch stop layer (ESL) to prevent etching to the gate dielectric 218.

[0039] To provide additional electrical isolation between the n-type doped region 206 of the floating node 108 and the adjacent pixel sensor, a p-type doped region 226 can be formed between the isolation structure 220 and the n-type doped region 206 (of the floating node 108). The p-type doped region 226 is also located between the isolation structure 220 and the drain extension region 208 (as associated with the transmission gate 210). The p-type doped region 226 prevents photocurrent from flowing through the isolation structure 220 (e.g., because the remaining dangling silicon bonds after the formation of the isolation structure 220 allow such flow). In addition, the p-type doped region 226 absorbs additional electrons from the remaining dangling silicon bonds after the formation of the isolation structure 220, which reduces noise caused by these additional electrons, which would otherwise alter the photocurrent.

[0040] p-type doped region 226 can be formed using boron (B) as a dopant. The concentration associated with p-type doped region 226 can range from approximately 1.0 × 10⁻⁶. 17 cubic centimeters (cm) -3 ) to approximately 1.0 × 10 21 cm -3 Within the range. Select at least 1.0 × 10. 17 cm -3 A concentration of 220 μm provides sufficient electrical isolation – choosing a lower concentration will allow photocurrent to flow through the isolation structure. Select a concentration not exceeding 1.0 × 10⁻⁶. 21 cm -3 The concentration can reduce noise caused by additional holes in the p-type doped region 226, which alters the photocurrent—choosing a higher concentration will make the p-type doped region 226 alter the photocurrent more significantly than the additional electrons from the remaining dangling silicon bonds after the formation of the isolation structure 220.

[0041] Figure 2B A top view of the pixel sensor 200 is shown. (As shown) Figure 2B As shown, the two photodiodes (associated with transmission gates 210a and 210b) can share the n-type doped region 206 (and therefore share the floating node 108). An isolation structure 220 surrounds the photodiodes and isolates them from adjacent pixel sensors. Figure 2A The cross-section shown can be along Figure 2B The AB line is shown.

[0042] Figure 2C A cross-sectional view of pixel sensor 230 is shown. Pixel sensor 230 is similar. Figure 2AThe pixel sensor 200, except for pixel sensor 230, includes a first film 232 and a second film 234. Films 232 and 234 serve as buffers between the isolation structure 220 and the gate dielectric 218. Both the first film 232 and the second film 234 can comprise silicon dioxide, undoped polysilicon, and / or nitride materials, etc. Therefore, films 232 and 234 can serve as a multilayer ESL to prevent etching to the gate dielectric 218. A top view of pixel sensor 230 will resemble... Figure 2B The pixel sensor 200 shown is a top view.

[0043] As mentioned above, providing Figures 2A-2C As an example. Other examples can be found related to... Figures 2A-2C The descriptions are different.

[0044] Figure 2D A cross-sectional view of pixel sensor 260 is shown. Pixel sensor 260 is similar. Figure 2B The pixel sensor 230, except that the first film 232 of the pixel sensor 260 is part of the n-type doped region 206, therefore, the second film 234 is used as a buffer between the isolation structure 220 and the first film 232. Among other examples, the first film 232 may comprise n-type doped polysilicon (e.g., phosphorus doped) or epitaxial silicon with n-type doping (e.g., phosphorus doped). The concentration associated with the first film 232 can range from about 1.0 × 10⁻⁶. 18 cm -3 From approximately 1.0 × 10 22 cm -3 Within the range. Select at least 1.0 × 10. 18 cm -3 The concentration provides sufficient drain functionality—choosing a lower concentration will impede photocurrent flow through the n-type doped region 206. A concentration not exceeding 1.0 × 10⁻⁶ is recommended. 22 cm -3 The concentration increases stability and reduces electrons migrating to other parts of the pixel sensor 260—choosing a larger concentration will cause electrons to migrate to other parts of the pixel sensor 260 and degrade the performance of the pixel sensor 260 (e.g., by migrating to the photodiode 104 and thus reducing the QE of the photodiode 104).

[0045] Figure 2E A top view of the pixel sensor 260 is shown. (As shown) Figure 2E As shown, the four photodiodes (associated with transmission gates 210a, 210b, 210c, and 210d) can share the n-type doped region 206 (and therefore the floating node 108). An isolation structure 220 surrounds the photodiodes and isolates them from adjacent pixel sensors. Figure 2D The cross section depicted in the middle can be along Figure 2EA-B line shown.

[0046] As described above, providing Figures 2D-2E as an example. Other examples can differ from what is described with respect to Figures 2D-2E the described.

[0047] Figure 3 A cross-section 300 of the isolation structure is shown. Referring to Figure 2A the pixel sensor 200, the isolation structure 220 is shown; however, the isolation structure 220 can similarly be contained in the pixel sensor 230 or Figure 2C the pixel sensor 260. Figure 2D

[0048] As shown in Figure 3 , the ratio of the depth associated with the isolation structure 220 (e.g., represented by hi) to the depth of the p-type doped region 226 (e.g., represented by h2) can be in a range of about 2.50 to about 266.67. For example, the depth hi can be in a range from about 2.5 micrometers (pm) to about 8.0 pm, and the depth h2 can be in a range from about 30 nanometers (nm) to about 1.0 pm. Selecting a ratio of at least 2.50 reduces (or even eliminates) the migration of electrons from the n-type doped region 206 to the photodiode 104 (not shown)— selecting a smaller ratio would cause the electrons to migrate and degrade the performance of the pixel sensor (e.g., via migration to the photodiode 104 and thus reducing the QE of the photodiode 104). Selecting a ratio of no more than 266.67 reduces the thickness of the substrate 202 (not shown)— using a thicker substrate would reduce the QE of the pixel sensor because this causes the light path of the incident light to the photodiode 104 to be longer and / or the electrical path of the photo current to the floating node 108 (not shown) to be longer.

[0049] Additionally, the ratio of the width associated with the isolation structure 220 (e.g., represented by Figure 3 in the pixel sensor 200) to the width of the p-type doped region (e.g., represented by Figure 3 in the pixel sensor 200) is in a range of about 1.0 to about 60.0. For example, the width wi can be in a range from about 50 nm to about 300 nm, and the width w2 can be in a range from about 5 nm to about 50 nm. Selecting a ratio of at least 1.0 reduces the noise caused by the additional holes in the p-type doped region 226 that can alter the photo current— selecting a larger ratio would cause the p-type doped region 226 to alter the photo current more significantly than the additional electrons from the dangling silicon bonds remaining after the isolation structure 220 is formed. Selecting a ratio of no more than 60.0 isolates the n-type doped region 206 (not shown) from the adjacent pixel sensor— selecting a smaller ratio would allow the photo current to flow through the isolation structure 220.

[0050] ​In some embodiments, the film 224 can have a depth equal to or less than a depth of the p-type doped region 226. For example, the film 224 can have a depth ranging from about 25 nm to about 200 nm.

[0051] As described above, Figure 3 are provided by way of example. Other examples can differ from those described Figure 3 in this detailed description. For example, the film 224 can be replaced with a first film 232 and a second film 234, as described in connection with Figure 2C Thus, the films 232 and 234 can have a joint depth equal to or less than a depth of the film 224 and a width about equal to (e.g., within 1%, 10%, or similar error range) the width of the film 224. Alternatively, the film 224 can be replaced with a first film 232 and a second film 234, as described in connection with Figure 2D Thus, the width of the first film 232 can be equal to or greater than a combined width of the isolation structure 220 and the p-type doped region 226. For example, the width can range from about 60 nm to about 500 nm. Selecting a width of at least 60 nm allows electrons to flow from the photodiode 104 (not shown) to the n-type doped region 206 (not shown) including the first film 232 - selecting a smaller width would prevent the photo current from flowing through the n-type doped region 206. Selecting a width of no more than 500 nm reduces the migration of electrons to other portions of the pixel sensor - selecting a larger width would allow the electrons to migrate to other portions of the pixel sensor and degrade the performance of the pixel sensor (e.g., by migrating to the photodiode 104, thereby reducing the QE of the photodiode 104).

[0052] Figures 4A-4K is a diagram of an example implementation 400 described herein. The example implementation 400 can be an example process for forming a pixel sensor 200 having a p-type doped region adjacent to an isolation structure. Figure 2A The pixel sensor formed using the example implementation 400 can be included in a CMOS image sensor, a BSi CMOS image sensor, or another type of image sensor.

[0053] As described above, Figure 4AAs shown, an exemplary process for forming a pixel sensor can be performed in conjunction with substrate 202. As described above, substrate 202 may include a semiconductor chip, a semiconductor wafer, a stacked semiconductor wafer, or another type of substrate in which semiconductor pixels can be formed. For example, substrate 202 may be formed from silicon (Si) (e.g., a silicon substrate), a material including silicon, a III-V compound semiconductor material such as gallium arsenide (GaAs), SOI, or another type of semiconductor to form a material capable of generating charge from photons of incident light. In some embodiments, substrate 202 is formed from a doped material such as doped silicon (e.g., a p-doped material or an n-doped material).

[0054] like Figure 4A As further shown, a hard mask (HM) 402 can be formed over the substrate 202. For example, a deposition tool can form the HM 402 over and / or on the front surface of the substrate 202. In some embodiments, the deposition tool uses spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or another deposition technique to form the HM 402. Furthermore, an exposure tool can expose the HM 402 to a radiation source to form a pattern on the HM 402, and a developing tool can develop and remove portions of the HM 402 to expose the pattern. An etching tool can etch a portion of the substrate 202 according to the pattern to form a recess 404. For example, the etching tool can use wet etching, dry etching, plasma-enhanced etching, and / or another type of etching technique to etch the substrate 202.

[0055] To repair some of the damage caused by the formation of the groove 404, an annealing process can be performed. For example, an annealing tool can heat the substrate 202 for a certain amount of time to meet a threshold (e.g., associated with DTI damage repair). The annealing process can reduce the number of dangling silicon bonds caused by etching the substrate 202.

[0056] like Figure 4B As shown, the p-type doped region 226 can be formed adjacent to the top portion of the recess 404. For example, an ion implantation tool can dope the top surface of the recess 404 to form the p-type doped region 226. The ion implantation tool can implant an n-type dopant (e.g., boron) using implantation, plasma doping, and / or laser doping (e.g., using borosilicate glass).

[0057] like Figure 4CAs shown, the recess 404 can be filled with a dummy material 406. The dummy material 406 may include an oxide material and / or another type of dielectric material. Deposition tools can be used to deposit the dummy material 406 using spin coating, CVD, PVD, ALD, and / or another deposition technique. In some embodiments, the recess 404 is only partially filled (e.g., such that the top surface of the dummy material 406 is below the top surface of the substrate 202 but above the bottom boundary of the p-type doped region 226, as shown). Figure 4C (As shown). Alternatively, the dummy material 406 can overflow the groove 404, and the excess dummy material can be removed with a planarization tool (e.g., using chemical mechanical planarization (CMP) technology), and the dummy material 406 can be etched back with an etching tool (e.g., such that the top surface of the dummy material 406 is below the top surface of the substrate 202 but above the bottom boundary of the p-type doped region 226, as shown). Figure 4C (As shown).

[0058] like Figure 4D As shown, a film 224 can be formed in the groove 404. For example, a deposition tool can form the film 224 over the dummy material 406. In some embodiments, the deposition tool uses spin coating, CVD, PVD, ALD, and / or another deposition technique to form the film 224. The film 224 can overflow the groove 404, allowing a planarization tool to remove excess material (e.g., using CMP), and the top surface of the film 224 is approximately flush with the top surface of the substrate 202 (e.g., within a 1%, 10%, or similar tolerance range). The dummy material 406 and the film 224 can serve as a dummy isolation structure.

[0059] like Figure 4D As further shown, HM 402 can be removed. For example, photoresist removal tools can use chemical strippers, plasma ashing devices, and / or other techniques to remove the remainder of HM 402. Although exemplary embodiment 400 includes removing HM 402 after forming film 224, other embodiments may include removing HM 402 before forming film 224 (e.g., after depositing dummy material 406 or after implanting p-type doped regions 226).

[0060] like Figure 4EAs shown, the photodiode 104 can be formed in the substrate 202. For example, an ion implantation tool can use ion implantation techniques to dope one or more portions of the substrate 202 to form n-type regions and / or p-type regions of the photodiode 104 to form a pn junction for the photodiode 104. For example, the ion implantation tool can dope the substrate 202 with n-type dopants to form n-type regions and can dope the substrate 202 with p-type dopants to form p-type portions of the pn junction. In some embodiments, another technique is used to form the photodiode 104, such as diffusion.

[0061] As shown, the p-type well 204 can be formed adjacent to the photodiode 104 and the transfer gate 210 (and adjacent to the dummy isolation structure). For example, an ion implantation tool can dope a portion of the substrate 202 to form the p-type well 204. The ion implantation tool can implant p-type ions into the substrate 202 to form the p-type well 204. In some embodiments, the p-type well 204 is formed via diffusion and / or epitaxial growth. Figure 4F As shown, a recess 408 can be formed in the substrate 202. The recess 408 can expose (or at least be above) a top boundary of the photodiode 104. A deposition tool can form a photoresist layer over and / or above the front side surface of the substrate 202, an exposure tool can expose the photoresist layer to a source of radiation to form a pattern on the photoresist layer, and a development tool can develop and remove portions of the photoresist layer to reveal the pattern. Accordingly, an etching tool can etch a portion of the substrate 202 according to the pattern to form the recess 408. For example, the etching tool can use a wet etching technique, a dry etching technique, a plasma enhanced etching technique, and / or another type of etching technique to etch the substrate 202. After forming the recess 408, a photoresist removal tool can remove remaining portions of the photoresist layer (e.g., using a chemical stripper, a plasma asher, and / or other techniques).

[0062] Figure 4G As shown, a gate dielectric 218 can be formed over and / or above a top surface of the substrate 202. In addition to the top surface of the substrate 202, the gate dielectric 218 can also be formed over the sidewalls and bottom surface of the recess 408. A deposition tool can use a CVD technique, a PVD technique, an ALD technique, and / or another type of deposition technique to deposit the gate dielectric 218. In some embodiments, a planarization tool can planarize the gate dielectric 218 (e.g., using a CMP technique) after depositing the gate dielectric 218.

[0063] As shown, a gate electrode 220 can be formed over and / or above the gate dielectric 218. For example, a deposition tool can use a CVD technique, a PVD technique, an ALD technique, and / or another type of deposition technique to deposit the gate electrode 220. In some embodiments, a planarization tool can planarize the gate electrode 220 (e.g., using a CMP technique) after depositing the gate electrode 220. Figure 4G As shown, a gate electrode 220 can be formed over and / or above the gate dielectric 218. For example, a deposition tool can use a CVD technique, a PVD technique, an ALD technique, and / or another type of deposition technique to deposit the gate electrode 220. In some embodiments, a planarization tool can planarize the gate electrode 220 (e.g., using a CMP technique) after depositing the gate electrode 220.

[0064] Figure 4H ​​As shown, the transport gate 210 may be formed on and / or over the gate dielectric 218 and within the recess 408. In some embodiments, a deposition tool uses CVD, PVD, ALD, and / or another type of deposition technique to deposit the transport gate 210, and / or an electroplating tool uses an electroplating operation to deposit the transport gate 210. In some embodiments, an ion implantation tool may use one or more ion implantation operations to form the transport gate 210.

[0065] like Figure 4I As shown, the drain extension region 208 may be formed adjacent to (and thus associated with) the transfer gate 210. For example, an ion implantation tool may dope a portion of the top surface of the substrate 202 to form the drain extension region 208. The ion implantation tool may implant n-type ions into the substrate 202 to form the drain extension region 208. In some embodiments, the drain extension region 208 is formed via diffusion or epitaxial growth. The drain extension region 208 may be formed using photolithography between the transfer gate 210 and the sidewalls of the transfer gate 210 to define the location of the drain extension region 208.

[0066] like Figure 4I As further shown, an n-type doped region 206 may be formed adjacent to the photodiode 104 and the transmission gate 210 (and adjacent to the dummy isolation structure). For example, an ion implantation tool may dope a portion of the substrate 202 to form the n-type doped region 206. The ion implantation tool may implant n-type ions into the substrate 202 to form the n-type doped region 206. In some embodiments, the n-type doped region 206 is formed via diffusion and / or epitaxial growth.

[0067] like Figure 4J As shown, a dielectric layer 212 can be formed over a substrate 202. Deposition tools can be used to deposit the dielectric layer 212 using CVD, PVD, ALD, and / or another type of deposition technique. In some embodiments, a planarization tool can planarize the dielectric layer 212 after deposition (e.g., using CMP). Additionally, as... Figure 4I As shown, a conductive structure 214 can be formed to contact the n-type doped region 206. The conductive structure 214 can be formed by etching grooves in the dielectric layer 212 (e.g., similar to those described above) and depositing a conductive material (e.g., copper (Cu)) in the grooves. Similarly, a conductive structure 216 can be formed to contact the transport gate 210. Conductive structures 214 and 216 can be connected to the BEOL. For example, Figure 4I The structure shown can be bonded to additional chips including BEOL (e.g., ASIC 118, as combined). Figure 1AThe pixel transistors (e.g., the reset gate 110, the SF transistor 112, and the RS transistor 114) are on a chip separate from the photodiode 104 in implementations, the chips can be bonded together such that the combined structure is bonded to an additional chip that includes the BEOL.

[0068] As Figure 4K shown, the dummy material 406 can be removed and replaced with dielectric materials 222a and 222b. For example, an etching tool can use a wet etching technique, a dry etching technique, a plasma enhanced etching technique, and / or another type of etching technique to remove the dummy material 406. Additionally, a deposition tool can use a CVD technique, a PVD technique, an ALD technique, and / or another type of deposition technique to deposit the dielectric materials 222a and 222b. The dielectric materials 222a and 222b can function as an isolation structure from the film 224.

[0069] As described above, a process is provided Figures 4A-4K as an example. Other examples can differ from what is described with respect to at least the following Figures 4A-4K described. For example, the recess 404 can be formed using multiple layers instead of a single HM layer. The multiple layers can include a bottom layer, a middle layer, and a photoresist layer. Additionally or alternatively, a sidewall can be formed on the transfer gate 210 (e.g., after forming the drain extension 208).

[0070] Figures 5A-5I is a diagram of example implementations 500 described herein. The example implementations 500 can be example processes for forming a pixel sensor 230 of a CMOS image sensor, a BSICMOS image sensor, or another type of image sensor having a p-type doped region adjacent to an isolation structure. Figure 2C The pixel sensor formed using the example implementations 500 can include in a CMOS image sensor, a BSICMOS image sensor, or another type of image sensor.

[0071] As Figure 5A shown, the example implementations 500 can include processes incorporated Figures 4A-4C described. As Figure 5A further shown, a film 234 can be formed in the recess 404. For example, a deposition tool can form the film 234 over the dummy material 406. In some implementations, the deposition tool uses a spin-on technique, a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique to form the film 234. In some implementations, the recess 404 is only partially filled (e.g., such that a top surface of the film 234 is lower than a top surface of the substrate 202 but higher than a bottom boundary of the p-type doped region 226, as Figure 5A(As shown). Alternatively, film 234 can overflow from groove 404, and the excess film can be removed with a planarization tool (e.g., using CMP technology), and film 234 can be etched back with an etching tool (e.g., such that the top surface of film 234 is below the top surface of substrate 202 but above the bottom boundary of p-type doped region 226, as shown). Figure 5A (As shown).

[0072] like Figure 5B As shown, film 232 can be formed in groove 404. For example, a deposition tool can form film 232 over film 234. In some embodiments, the deposition tool uses spin coating, CVD, PVD, ALD, and / or another deposition technique to form film 232. Film 232 can overflow groove 404, allowing a planarization tool to remove excess material (e.g., using CMP), and the top surface of film 232 is approximately flush with the top surface of substrate 202 (e.g., within a 1%, 10%, or similar tolerance range). Dummy material 406, film 234, and film 232 can be used as dummy isolation structures.

[0073] like Figure 5B As further shown, HM 402 can be removed. For example, HM 402 can be combined as follows: Figure 4D It was removed as described.

[0074] like Figure 5C As shown, the photodiode 104 can be formed in the substrate 202. For example, the photodiode 104 can be combined as follows: Figure 4E It was injected as described.

[0075] like Figure 5D As shown, a p-type well 204 can be formed adjacent to the photodiode 104 and the transmission gate 210 (and adjacent to the dummy isolation structure). For example, the p-type well 204 can be combined as follows: Figure 4F It forms as described.

[0076] like Figure 5E As shown, a groove 408 can be formed in the substrate 202. The groove 408 can be joined as follows: Figure 4G The formation described. For example... Figure 5E As further shown, the gate dielectric 218 can be formed on and / or above the top surface of the substrate 202. The gate dielectric 218 can be bonded as follows: Figure 4G The formation described.

[0077] like Figure 5F As shown, the transfer gate 210 can be formed on and / or over the gate dielectric 218 and within the recess 408. For example, the transfer gate 210 can be combined as follows: Figure 4H It forms as described.

[0078] As shown in Figure 5G The drain extension region 208 can be formed adjacent to (and thus associated with) the transfer gate 210. For example, the drain extension region 208 can be implanted as described in connection with Figure 4I As further shown, an n-type doped region 206 can be formed adjacent to the photodiode 104 and the transfer gate 210 (and adjacent to the dummy isolation structure). For example, the n-type doped region 206 can be implanted as described in connection with Figure 5G As further shown, an n-type doped region 206 can be formed adjacent to the photodiode 104 and the transfer gate 210 (and adjacent to the dummy isolation structure). For example, the n-type doped region 206 can be implanted as described in connection with Figure 4I As further shown, an n-type doped region 206 can be formed adjacent to the photodiode 104 and the transfer gate 210 (and adjacent to the dummy isolation structure). For example, the n-type doped region 206 can be implanted as described in connection with

[0079] As shown in Figure 5H A dielectric layer 212 can be formed over the substrate 202. The dielectric layer 212 can be deposited as described in connection with Figure 4J Additionally, as shown, a conductive structure 214 can be formed to contact the n-type doped region 206, and a conductive structure 216 can be formed to contact the transfer gate 210. The conductive structures 214 and 216 can be connected to the BEOL. For example, Figure 5G The structures shown can be bonded to an additional chip (e.g., the ASIC 118, as described in connection with Figure 5H The structures shown can be bonded to an additional chip (e.g., the ASIC 118, as described in connection with Figure 1A In implementations where the pixel transistors (e.g., the reset gate 110, the SF transistor 112, and the RS transistor 114) are located on a chip separate from the photodiode 104, the chips can be bonded together such that the combined structure is bonded to an additional chip that includes the BEOL.

[0080] As shown in Figure 5I The dummy material 406 can be removed and replaced with dielectric material 222a and 222b. Thus, the dielectric material 222a and 222b can function as an isolation structure from the films 232 and 234.

[0081] As described above, the provision Figures 5A-5I is by way of example. Other examples can differ from what is described in connection with what is described in connection with Figures 5A-5I For example, the recess 404 can be formed using multiple layers instead of a single HM layer. The multiple layers can include a bottom layer, an intermediate layer, and a photoresist layer. Additionally or alternatively, a sidewall can be formed on the transfer gate 210 (e.g., after the drain extension region 208 is formed).

[0082] Figures 6A-6I is a diagram of an example implementation 600 described herein. The example implementation 600 can be an example process for forming a pixel sensor 260 of a Figure 2D that has a p-type doped region adjacent to an isolation structure. The pixel sensor formed using the example implementation 600 can be included in a CMOS image sensor, a BSICMOS image sensor, or another type of image sensor.

[0083] As Figure 6A further shown, an example implementation 600 can include processes described in connection with Figures 4A-4C As Figure 6A further shown, a film 234 can be formed in the recess 404. For example, a deposition tool can form the film 234 over the dummy material 406. In some implementations, the deposition tool uses a spin-on technique, a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique to form the film 234. In some embodiments, the recess 404 is only partially filled (e.g., such that a top surface of the film 234 is below a top surface of the substrate 202 but above a bottom boundary of the p-type doped region 226, as shown in Figure 6A Alternatively, the film 234 can overflow the recess 404, a planarization tool is used to remove excess film (e.g., using a CMP technique), and an etch tool is used to etch back the film 234 (e.g., such that a top surface of the film 234 is below a top surface of the substrate 202 but above a bottom boundary of the p-type doped region 226, as shown in Figure 6A

[0084] As Figure 6A further shown, a portion of the substrate 202 above the film 234 is laterally removed. For example, an etch tool can use a wet etch technique, a dry etch technique, a plasma enhanced etch technique, and / or another type of etch technique to remove the portion of the substrate 202. The etch removes some of the p-type doped region 226, but allows the film 232 to be formed with a larger width (e.g., as described in connection with Figure 2D Alternatively, the film 232 can overflow the recess 404, a planarization tool is used to remove excess film (e.g., using a CMP technique), and an etch tool is used to etch back the film 232 (e.g., such that a top surface of the film 232 is below a top surface of the substrate 202 but above a bottom boundary of the p-type doped region 226, as described in connection with Figure 6B

[0085] As Figure 6B further shown, the HM 402 can be removed. For example, the HM 402 can be removed as described in connection with Figure 4D

[0086] As Figure 6B further shown, a film 232 can be formed in the recess 404. For example, a deposition tool can form the film 232 over the film 234. In some implementations, the deposition tool uses a spin-on technique, a CVD technique, a PVD technique, an ALD technique, and / or another deposition technique to form the film 232. The film 232 can overflow the recess 404, such that a planarization tool is used to remove excess material (e.g., using a CMP technique), and a top surface of the film 232 is about flush with a top surface of the substrate 202 (e.g., within 1%, 10%, or a similar error range). The dummy material 406, the film 234, and the film 232 can be used as dummy isolation structures.

[0087] As Figure 6C shown, the photodiode 104 can be formed in the substrate 202. For example, the photodiode 104 can be formed as described in connection with​​​Figure 4E is injected as described.

[0088] As Figure 6D shown, a p-type well 204 can be formed adjacent to the photodiode 104 and the transfer gate 210 (and adjacent to the dummy isolation structure). For example, the p-type well 204 can be formed as described in connection with Figure 4F .

[0089] As Figure 6E shown, a recess 408 can be formed in the substrate 202. The recess 408 can be formed as described in connection with Figure 4G . As Figure 6E further shown, a gate dielectric 218 can be formed on and / or over a top surface of the substrate 202. The gate dielectric 218 can be formed as described in connection with Figure 4G .

[0090] As Figure 6F shown, the transfer gate 210 can be formed on and / or over the gate dielectric 218 and the recess 408. For example, the transfer gate 210 can be formed as described in connection with Figure 4H .

[0091] As Figure 6G shown, a drain extension 208 can be formed adjacent to (and thus associated with) the transfer gate 210. For example, the drain extension 208 can be implanted as described in connection with Figure 4I . As Figure 6G further shown, an n-type doped region 206 can be formed adjacent to the photodiode 104 and the transfer gate 210 (and adjacent to the dummy isolation structure). For example, the n-type doped region 206 can be implanted as described in connection with Figure 4I . In example implementations, the n-type doped region 206 includes a film 232.

[0092] As Figure 6H shown, a dielectric layer 212 can be formed over the substrate 202. The dielectric layer 212 can be deposited as described in connection with Figure 4J . Additionally, as Figure 6H shown, a conductive structure 214 can be formed to contact the n-type doped region 206, and a conductive structure 216 can be formed to contact the transfer gate 210. The conductive structures 214 and 216 can be connected to the BEOL. For example, Figure 6H the structures shown can be bonded to an additional chip (e.g., the ASIC 118, as described in connection with Figure 1AThe pixel transistors (e.g., reset gate 110, SF transistor 112, and RS transistor 114) are on a chip separate from the photodiode 104 in implementations, the chips can be bonded together such that the combined structure is bonded to an additional chip that includes the BEOL.

[0093] As Figure 6I illustrated, dummy material 406 can be removed and replaced with dielectric material 222a and 222b. Thus, dielectric material 222a and 222b can function as an isolation structure from films 232 and 234.

[0094] As described above, a process 700 is provided Figures 6A-6I as an example. Other examples can differ from what is described with respect to process 700, for example, as described with respect to Figures 6A-6I implementations described herein. For example, the recess 404 can be formed using multiple layers instead of a single HM layer. The multiple layers can include a bottom layer, a middle layer, and a photoresist layer. Additionally or alternatively, a sidewall can be formed on the transfer gate 210 (e.g., after forming the drain extension 208).

[0095] Figure 7 is a flow diagram of an exemplary process 700 associated with forming a pixel sensor described herein. In some implementations, one or more processing blocks of process 700 are performed using one or more semiconductor processing tools. Additionally or alternatively, one or more processing blocks of process 700 can be performed using one or more components of a device, such as a processor, a memory, an input component, an output component, and / or a communication component. Figure 7 Figure 7 As further illustrated, process 700 can include forming a p-type doped region adjacent to the recess (block 720). For example, the p-type doped region 226 adjacent to the recess 404 can be formed using one or more semiconductor processing tools, as described herein.

[0096] Figure 7 As further illustrated, process 700 can include filling the recess with a dummy material (block 730). For example, the recess 404 can be filled with dummy material 406 using one or more semiconductor processing tools, as described herein.

[0097] Figure 7 As further illustrated, process 700 can include filling the recess with a dummy material (block 730). For example, the recess 404 can be filled with dummy material 406 using one or more semiconductor processing tools, as described herein.

[0098] Figure 7 As

[0099] As Figure 7 ​Further, process 700 can include forming a photodiode in the substrate (block 740). For example, the photodiode 104 can be formed in the substrate 202 using one or more semiconductor processing tools, as described herein.

[0100] As Figure 7 Further, process 700 can include forming a floating node through implantation of the n-type doped region (block 750). For example, the floating node 108 can be formed through implantation of the n-type doped region 206 using one or more semiconductor processing tools, as described herein.

[0101] As Figure 7 Further, process 700 can include forming at least one conductive structure associated with the floating node (block 760). For example, the at least one conductive structure 214 / 216 associated with the floating node 108 can be formed using one or more semiconductor processing tools, as described herein.

[0102] As Figure 7 Further, process 700 can include replacing the dummy material with at least one dielectric material to form an isolation structure (block 770). For example, the dummy material 406 can be replaced with at least one dielectric material to form the isolation structure 220 using one or more semiconductor processing tools, as described herein.

[0103] Process 700 can include additional implementations, such as any single implementation or any combination of implementations described below and / or in combination with one or more other processes described elsewhere herein.

[0104] In a first implementation, process 700 includes bonding the first chip 102 including the photodiode 104, the floating node 108, and the at least one conductive structure 214 / 216 to the second chip 116 including the integrated circuit 118.

[0105] In a second implementation, process 700 includes bonding the first chip 102 including the photodiode 104 and the floating node 108 to a third chip 152 including the at least one transistor 110 / 112 / 114, and bonding the third chip 152 to the second chip 116 including the integrated circuit 118.

[0106] In a third implementation, alone or in combination with one or more of the first and second implementations, forming the p-type doped region 226 includes at least one of performing implantation of the p-type doped region 226, performing plasma doping to form the p-type doped region 226, or performing laser doping to form the p-type doped region 226.

[0107] In a fourth implementation, alone or in combination with one or more of the first through third implementations, the process 700 includes forming a gate material over the substrate 202, wherein the at least one film 224 / 232 / 234 separates the gate material from the at least one dielectric material of the isolation structure 220.

[0108] In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, the process 700 includes etching portions of the dummy material 406 and forming the at least one film 224 / 232 / 234 on the dummy material 406.

[0109] In a sixth implementation, alone or in combination with one or more of the first through fifth implementations, forming the photodiode 104 includes implanting the photodiode 104 at a backside of the substrate 202, wherein the isolation structure 220 is associated with a frontside of the substrate 202.

[0110] Although Figure 7 Example blocks of the process 700 are shown, but in some implementations, the process 700 includes additional blocks, fewer blocks, different blocks, or blocks in a different order than those depicted in FIG. 7. Additionally or alternatively, two or more blocks of the process 700 can be performed in parallel. Figure 7 Figure 7

[0111] In this way, the p-type doped region around the isolation structure provides additional electrical isolation between the pixel sensors of the pixel array. As a result, current leakage from a floating node of one pixel sensor to another pixel sensor is reduced. Thus, dark current can be reduced and the performance of the pixel array can be improved. Additionally, pixel noise caused by trapped electrons in the isolation structure can be reduced.

[0112] As described in more detail above, some implementations described herein provide a semiconductor structure. The semiconductor structure includes a photodiode in a substrate and a floating node including an n-type doped region. The semiconductor structure includes an isolation structure around the photodiode. The semiconductor structure includes a p-type doped region between the n-type doped region of the floating node and the isolation structure and is configured to absorb excess charge from the isolation structure.

[0113] As described in more detail above, some implementations described herein provide a method. The method includes forming a recess in a substrate. The method includes forming a p-type doped region adjacent to the recess. The method includes filling the recess with a dummy material. The method includes forming a photodiode in the substrate. The method includes forming a floating node by implanting an n-type doped region. The method includes forming at least one conductive structure associated with the floating node. The method includes replacing the dummy material with at least one dielectric material to form an isolation structure. ​

[0114] As described in more detail above, some embodiments described herein provide a semiconductor structure. The semiconductor structure includes a photodiode in a substrate and a transfer gate associated with a drain region. The semiconductor structure includes an isolation structure around the photodiode. The semiconductor structure includes a p-type doped region between the drain region and the isolation structure and is configured to absorb excess charge from the isolation structure.

[0115] As used herein, "satisfies a threshold" can refer to a value that is greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, depending on the context. Threshold, not equal to the threshold, etc.

[0116] The foregoing outlines features of several embodiments so that a person having ordinary skill in the art can more readily understand the detailed description of the disclosure. Those of ordinary skill in the art, having the benefit of the present disclosure, will appreciate that they can readily apply the disclosure as taught herein to other processes and structures without departing from the spirit and scope of the present disclosure. Those of ordinary skill in the art, having the benefit of the present disclosure, will also understand that they can make various changes, substitutions and alterations to the disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized by, comprising: a photodiode in a substrate; a floating node comprising an n-type doped region; an isolation structure surrounding the photodiode; and a p-type doped region between the n-type doped region of the floating node and the isolation structure to sink excess charge from the isolation structure. further comprising:

2. The semiconductor structure of claim 1, wherein, a transfer gate connected to the floating node. The floating node further comprises a drain extension region.

3. The semiconductor structure of claim 1, wherein, further comprising:

4. The semiconductor structure of claim 1, wherein, at least one film adjacent to the p-type doped region and on a dielectric material of the isolation structure. The at least one film comprises a first film and a second film, and the p-type doped region contacts the first film and the second film.

5. The semiconductor structure of claim 4, wherein, The at least one film comprises a first film and a second film, the first film is wider than the second film, and the p-type doped region contacts the second film.

6. The semiconductor structure of claim 4, wherein, further comprising:

7. The semiconductor structure of claim 1, wherein, a conductive structure contacting a portion of the film above the dielectric material of the isolation structure. comprising:

8. A semiconductor structure, characterized by a photodiode in a substrate; a transfer gate associated with a drain region; an isolation structure surrounding the photodiode; and a p-type doped region between the drain region and the isolation structure to sink excess charge from the isolation structure. A ratio of a depth of the p-type doped region to a width of the p-type doped region is in a range of 0.6 to 200.

0. A ratio of a depth of the isolation structure to a depth of the p-type doped region is in a range of 2.50 to 266.67, and a ratio of a width of the isolation structure to a width of the p-type doped region is in a range of 1.0 to 60.

0.

9. The semiconductor structure of claim 8, wherein, ​ 10. The semiconductor structure of claim 8, wherein, ​

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