Chip aging test device

Abstract

The utility model provides a chip aging test device. The chip aging test device comprises a mainboard, an aging test system and a BMC (Baseboard Management Controller), the aging test system and the BMC are arranged on the mainboard and are electrically connected through the mainboard, and the BMC controls the chip aging test system to set the chip body as an aging test environment. The chip aging test device can save the space occupied by the chip aging test device.

Description

TECHNICAL FIELD

[0001] The utility model relates to chip testing technical field especially relates to a chip aging test device. BACKGROUND

[0002] After the chip is encapsulated, potential defects may exist, which will cause the chip performance to be unstable or the function of the chip to be not fully realized. If these chips with potential defects are used in the customer's equipment, equipment failure may occur, thereby affecting the customer's business.

[0003] The purpose of the aging test is to place the chip at a certain temperature for a certain period of time, and then apply a specific voltage to accelerate the aging of the chip, so as to discover the chip problem in advance, thereby avoiding potential risks in the design stage and ensuring the stability and reliability of the chip performance handed over to the customer. Therefore, the chip aging test is an important means to ensure the reliability of the chip quality and is also a necessary link in the chip test project.

[0004] However, the existing chip aging test process not only needs special test equipment, which is expensive, but also needs to design a separate matching use machine room, which increases the test cost and occupies a large space. UTILITY MODEL CONTENTS

[0005] To solve the above problems, the chip aging test device provided by the utility model can save the space occupied by the chip aging test device by setting the aging test system and the management control system on the mainboard.

[0006] The utility model provides a kind of chip aging test device, and chip aging test device includes: mainboard, aging test system and BMC (Baseboard Management Controller, baseboard management controller);

[0007] Aging test system and BMC are set on mainboard and are electrically connected by mainboard, and BMC controls chip aging test system to set chip body as aging test environment.

[0008] Optionally, the chip aging test device further includes an operating system loading device and a chip auxiliary system.

[0009] BMC is electrically connected with the aging test system, and the aging test system and the BMC are both electrically connected with the chip body through the mainboard, and the chip auxiliary system and the operating system loading device are both in communication connection with the chip body.

[0010] The operating system loading device is used to transmit test data to the chip body via the loaded operating system when the chip auxiliary system is in working state, and start the aging test when the chip body is set as the aging test environment.

[0011] The BMC is used to transmit test data to the chip body when the chip auxiliary system is in a non-working state, and to start the aging test when the chip body is set in an aging test environment.

[0012] Optionally, the BMC comprises a control subsystem, a first network interface, a control interface and a storage device.

[0013] The first network interface and the control interface are electrically connected with the control subsystem, the control subsystem is electrically connected with the aging test system and the chip body through the control interface, and the storage device is electrically connected with the control subsystem.

[0014] Optionally, the BMC further comprises a monitoring interface.

[0015] The monitoring interface is electrically connected with the control subsystem, and the control subsystem is electrically connected with a monitoring device through the monitoring interface.

[0016] Optionally, the BMC further comprises a display interface.

[0017] The display interface is electrically connected with the control subsystem, and the BMC is electrically connected with an operating system loading device through the display interface.

[0018] Optionally, the control interface comprises a JTAG communication interface.

[0019] The control subsystem is electrically connected with the chip body through the JTAG communication interface.

[0020] Optionally, the aging test system comprises a chip power supply subsystem and a chip temperature control subsystem.

[0021] The chip power supply subsystem is electrically connected with the BMC and the chip body respectively, and the chip temperature control subsystem is electrically connected with the BMC and the chip body respectively.

[0022] The BMC controls the voltage of the chip body through the chip power supply subsystem and controls the temperature of the chip body through the chip temperature control subsystem.

[0023] Optionally, the chip power supply subsystem comprises a power supply chip and a regulation resistance.

[0024] The power supply chip is electrically connected with the BMC and the regulation resistance respectively, and the regulation resistance is electrically connected with the chip body and the BMC.

[0025] The power supply chip provides power supply to the chip body through the regulation resistance, the BMC acquires current data of the regulation resistance, and regulates the voltage output by the power supply chip.

[0026] Optionally, the chip temperature control subsystem comprises a heating subsystem and a heat dissipation subsystem.

[0027] The BMC is electrically connected with the heating subsystem and the heat dissipation subsystem respectively;

[0028] The BMC increases the temperature of the chip body through the heating subsystem and decreases the temperature of the chip body through the heat dissipation subsystem.

[0029] Optionally, the chip aging test device further comprises a host computer.

[0030] The host computer is electrically connected with the BMC and the operating system loading device.

[0031] The host computer is configured to transmit test data to the chip body via the operating system loaded by the operating system loading device when the chip auxiliary system is in the working state, transmit test data to the chip body through the BMC when the chip auxiliary system is in the non-working state, and start the aging test through the BMC when the chip body is set to the aging test environment.

[0032] Optionally, the chip auxiliary system comprises a memory subsystem and a peripheral subsystem.

[0033] The memory subsystem is electrically connected with the chip body, and the peripheral subsystem is communicatively connected with the chip body.

[0034] Optionally, the peripheral subsystem comprises an information interaction interface.

[0035] The peripheral subsystem is electrically connected with the operating system loading device through the information interaction interface.

[0036] The chip aging test device provided by the embodiment of the utility model has simple structure and is convenient to manufacture, can not only reduce the manufacturing cost of the chip aging test device, but also improve the space utilization of the chip aging test device and save the space occupied by the chip aging test device. In addition, when the chip auxiliary system is in the working state, test data can be transmitted to the chip body through the operating system loading device, so that the chip body can be tested in the HTOL SLT (High Temperature Operation Life System Level Test) test mode, and when the chip auxiliary system is in the non-working state, test data can be transmitted to the chip body through the management control system, so that the chip body can be tested in the HTOL DFT (High Temperature Operation Life Design For Test) test mode, thereby improving the compatibility of the chip aging test device. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only represent some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative effort based on these drawings.

[0038] Figure 1 A schematic structural block diagram of a chip aging test device according to an embodiment of the present application;

[0039] Figure 2 A schematic partial structural block diagram of a chip aging test device according to an embodiment of the present application;

[0040] Figure 3 A schematic partial structural block diagram of a chip aging test device according to an embodiment of the present application;

[0041] Figure 4 A schematic partial structural block diagram of a chip aging test device according to an embodiment of the present application.

[0042] Reference signs:

[0043] 1, BMC; 11, control subsystem; 12, first network interface; 13, control interface; 14, storage device; 15, monitoring interface; 2, operating system loading device; 31, chip body; 32, chip auxiliary system; 321, memory subsystem; 322, peripheral subsystem; 4, aging test system; 41, chip power supply subsystem; 411, power chip; 412, regulation resistance; 42, chip temperature control subsystem; 421, heating subsystem; 422, heat dissipation subsystem; 5, mainboard; 6, host computer. DETAILED DESCRIPTION

[0044] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The embodiments of the present application are shown in the accompanying drawings. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0046] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0047] It is noted that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Like numbers refer to like elements throughout.

[0048] In the field of electricity, the communication connection is also referred to as an electrical connection, which includes a wired communication connection and a wireless communication connection. For the wired communication connection, it can be understood as a form of connection between different elements in the line structure through the entity line such as PCB copper foil or wire that can transmit electrical signals. For the wireless communication connection, it can be understood as a form of communication connection between two devices through wireless means, such as the wireless communication connection between a wireless mouse and a notebook, but it needs to be attached to the wireless mouse and the notebook respectively to realize the wireless data transceiver components that are adapted to each other, which will not be described in detail.

[0049] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", or "includes" and / or "including" when used herein, specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0050] The embodiment provides a chip aging test device, referring to Figure 1 The chip aging test device comprises a mainboard 5, an aging test system 4 and a BMC 1.

[0051] The aging test system 4 and the BMC 1 are arranged on the mainboard 5 and are electrically connected through the mainboard 5, and the BMC 1 controls the chip aging test system 4 to set the chip body 31 as an aging test environment.

[0052] It can be understood that the mainboard 5 also has a mounting station for mounting the chip body 31, and the mounting station is a space area on the mainboard 5, and after the chip body 31 is mounted on the mounting station of the mainboard 5, the chip body 31 can communicate with other devices on the mainboard 5 through the mainboard 5.

[0053] Further, the chip aging test device further comprises an operating system loading device 2 and a chip auxiliary system 32.

[0054] The BMC 1 is electrically connected with the aging test system 4, and the aging test system 4 and the BMC 1 are both electrically connected with the chip body 31 through the mainboard 5, and the chip auxiliary system 32 and the operating system loading device 2 are both in communication connection with the chip body 31. The operating system loading device 2 can be arranged on the mainboard 5 or outside the mainboard 5, and the embodiment does not make a specific limitation in this regard.

[0055] The operating system loading device 2 is used for transmitting test data to the chip body 31 via the loaded operating system when the chip auxiliary system 32 is in a working state, and starting the aging test when the chip body 31 is set as an aging test environment. The BMC 1 is used for transmitting test data to the chip body 31 when the chip auxiliary system 32 is in a non-working state, and starting the aging test when the chip body 31 is set as an aging test environment.

[0056] The chip aging test device provided by the embodiment of the utility model has simple structure and is convenient to manufacture, can not only reduce the manufacturing cost of the chip aging test device, but also improve the space utilization of the chip aging test device and save the space occupied by the chip aging test device.

[0057] Referring to Figure 1 In some embodiments, the chip aging test device comprises a BMC 1, an operating system loading device 2, a chip auxiliary system 32 and an aging test system 4.

[0058] The BMC system 1 is electrically connected with the aging test system 4. The aging test system 4 and the BMC 1 are both electrically connected with the chip body 31. The chip auxiliary system 32 and the operating system loading device 2 are both in communication connection with the chip body 31.

[0059] The operating system loading device 2 is used for transmitting test data to the chip body 31 when the chip auxiliary system 32 is in a working state. The BMC 1 performs aging test on the chip body 31 according to the test data on the chip body 31 and through the aging test system 4, and transmits test data to the chip body 31 when the chip auxiliary system 32 is in a non-working state.

[0060] It should be noted that the chip auxiliary system 32 in the working state can be understood as the chip auxiliary system 32 being in a power-on state, that is, the power supply subsystem normally supplies power to the chip auxiliary system 32, and the chip auxiliary system 32 in the non-working state can be understood as the chip auxiliary system 32 being in a power-off state, that is, the power supply subsystem stops supplying power to the chip auxiliary system 32, or being in an abnormal working state.

[0061] In the embodiment, the test data includes a test running script. In the aging test process, the BMC 1 can make the chip body 31 perform different operation contents by selecting different test running scripts in the chip body 31. The operation system loading device 2 includes a storage medium such as a hard disk or an optical disk, so as to provide the chip body 31 with an operation system matched with the chip body 31, and the utility model does not involve improvement of the operation system.

[0062] The chip aging test device provided by the embodiment of the utility model transmits the test data to the chip body 31 through the operation system loading device 2 when the chip auxiliary system 32 is in the working state, so as to realize the HTOL SLT test mode of the chip body 31, and when the chip auxiliary system 32 is in the non-working state, the test data can be transmitted to the chip body 31 through the BMC system 1, so as to realize the HTOL DFT test mode of the chip body 31, thereby improving the compatibility of the chip aging test device.

[0063] Further, the chip aging test device further includes: a host computer 6. The host computer 6 is electrically connected with the BMC 1 and the operation system loading device 2.

[0064] It can be understood that the host computer 6 can be directly electrically connected with the BMC 1 and the operation system loading device 2, or can be electrically connected with the BMC 1 and the operation system loading device 2 through the mainboard 5.

[0065] The host computer 6 is used for transmitting test data to the chip body 31 through the operation system loaded by the operation system loading device 2 when the chip auxiliary system 32 is in the working state, transmitting test data to the chip body 31 through the BMC 1 when the chip auxiliary system 32 is in the non-working state, and starting the aging test through the BMC 1 when the chip body 31 is set to the aging test environment.

[0066] In combination with Figure 2 The BMC 1 includes: a control subsystem 11, a first network interface 12, a control interface 13 and a storage device 14.

[0067] The first network interface 12 and the control interface 13 are electrically connected with the control subsystem 11, the control subsystem 11 is electrically connected with the aging test system 4 and the chip body 31 through the control interface 13, and the memory device 14 is electrically connected with the control subsystem 11.

[0068] The control subsystem 11 is electrically connected with the host computer 6 through the first network interface 12. The operating system loading device 2 is electrically connected with a second network interface, and the operating system loading device 2 is electrically connected with the host computer 6 through the second network interface.

[0069] The first network interface 12 can realize a data exchange interface between the control subsystem 11 and the host computer 6. Thus, the host computer 6 can be remotely connected to the chip aging test device through a network, and the starting and stopping of the chip body 31 aging test, the flexible adjustment of the power supply voltage of the chip body 31, the flexible setting of the aging temperature of the chip body 31, the collection of test data and the monitoring of the test environment state can be realized through the control subsystem 11. The memory device 14 is used for storing test data, test logs and firmware of the control subsystem 11 of the chip body 31.

[0070] The BMC 1 further comprises a monitoring interface 15. The monitoring interface 15 is electrically connected with the control subsystem 11, and the control subsystem 11 is electrically connected with a monitoring device through the monitoring interface 15.

[0071] In a further optional embodiment of the embodiment, the chip aging test device further comprises a monitoring device, which can be an ADC (Analog-to-Digital Converter), a Monitor or other chip, to realize real-time monitoring of the environmental temperature of the chip body 31, the voltage and current of the chip body 31, the power consumption and temperature of the chip body 31 and other key parameters.

[0072] In the embodiment, the control subsystem 11 comprises a graphics card subsystem. The graphics card subsystem has the function of a graphics card. The BMC system 1 further comprises a display interface. The display interface is electrically connected with the control subsystem 11. The peripheral system 322 comprises a display screen, the display screen is electrically connected with the chip body 31 and the control subsystem 11, and the control subsystem 11 is electrically connected with the operating system loading device 2 through the display interface. By setting the display interface, a user can view key parameters through the display screen and flexibly control the key parameters.

[0073] It should be noted that, in the embodiment, the graphics card subsystem in the control subsystem 11 is realized through an existing circuit design, and the utility model does not involve improvement of the graphics card subsystem in the control subsystem 11.

[0074] The control interface 13 comprises a JTAG communication interface. The control subsystem 11 is electrically connected to the chip body 31 through the JTAG communication interface. The control subsystem 11 transmits test data to the chip body 31 through the JTAG communication interface, starts the chip body 31 to perform the aging test, and collects the results of the aging test on the chip body 31.

[0075] The control interface 13 further comprises a low-speed bus such as PMBUS / I2C (Power Management Bus / Inter-Integrated Circuit), SVI2 / SVI3 (Serial Voltage Identification Interface 2.0 / Serial Voltage Identification Interface 3.0), or SPI (Serial Peripheral Interface), etc. The control subsystem 11 sends control data such as the working frequency of the chip body 31 to the chip body 31 through the low-speed bus.

[0076] In combination Figure 3 The aging test system 4 comprises a chip power subsystem 41 and a chip temperature control subsystem 42. The chip power subsystem 41 is electrically connected to the BMC system 1 and the chip body 31 respectively, and the chip temperature control subsystem 42 is electrically connected to the BMC system 1 and the chip body 31 respectively. The control subsystem 11 controls the voltage of the chip body 31 through the chip power subsystem 41. The control subsystem 11 controls the temperature of the chip body 31 through the chip temperature control subsystem 42.

[0077] By setting the chip power subsystem 41 and the chip temperature control subsystem 42, the chip aging test device flexibly regulates and controls the power voltage and the temperature of the chip body 31, and further improves the compatibility of the chip aging test device.

[0078] It should be noted that, in the embodiment, the control of the voltage and the temperature of the chip body 31 by the control subsystem 11 can be realized by the existing control method, and the utility model does not involve the improvement of the control method of the voltage and the temperature of the chip body 31 by the control subsystem 11. Therefore, the embodiment will not be described here.

[0079] In combination Figure 2 and Figure 3The chip power supply subsystem 41 comprises a power supply chip 411 and a regulating resistor 412. The power supply chip 411 is electrically connected with the control subsystem 11 through the control interface 13 and is electrically connected with the regulating resistor 412. The regulating resistor 412 is electrically connected with the control subsystem 11 through the control interface 13 and is electrically connected with the chip body 31.

[0080] The power supply chip 411 provides power supply to the chip body 31 through the regulating resistor 412, the BMC system 1 is used to acquire current data of the regulating resistor 412, so as to acquire actual power consumption of the chip body 31 in real time and is used to regulate voltage output by the power supply chip 411.

[0081] In the embodiment, the regulating resistor 412 is a precision resistor, the control subsystem 11 acquires current data of each item of the chip body 31 through the regulating resistor 412 and uploads the current data to the upper computer. The control subsystem 11 controls the power supply chip 411 when receiving the voltage regulation instruction sent by the upper computer 6, so as to regulate voltage output by the power supply chip 411.

[0082] In combination with Figure 2 and Figure 4 The chip temperature control subsystem 42 comprises a heating subsystem 421 and a heat dissipation subsystem 422. The control subsystem 11 is electrically connected with the heating subsystem 421 and the heat dissipation subsystem 422 through the control interface 13. The heating subsystem 421 and the heat dissipation subsystem 422 are both in contact with the surface of the chip body 31.

[0083] The control subsystem 11 raises the temperature of the surface of the chip body 31 through the heating subsystem 421 and lowers the temperature of the surface of the chip body 31 through the heat dissipation subsystem 422 by means of a fan or water cooling. The heating subsystem 421 can be set to realize rapid heating of the chip body 31 and reach a specified aging temperature in a low-power-consumption test scenario.

[0084] When controlling the temperature of the chip body 31, the control subsystem 11 can also control the heating subsystem 421 and the heat dissipation subsystem 422 at the same time, so as to keep the temperature of the surface of the chip body 31 within a range of ±1℃, thereby providing a stable and reliable temperature environment for the aging test of the chip body 31.

[0085] In combination with Figure 1 The chip auxiliary system 32 comprises a memory system 321 and a peripheral system 322. The memory system 321 is electrically connected with the chip body 31 and the peripheral system 322 is communicatively connected with the chip body 31. The memory system 321 is a memory in the art and the peripheral system 322 can be an input device such as a mouse or a keyboard, but is not limited thereto. In the embodiment, the peripheral system 322 and the operating system loading device 2 are both electrically connected with the chip body 31.

[0086] Further, the peripheral system 322 comprises an information interaction interface. The peripheral system 322 is electrically connected to the operating system loading device 2 through the information interaction interface. By setting the information interaction interface, the peripheral system 322, such as a keyboard, can read and write test data on the chip body 31 through the operating system loading device 2.

[0087] The chip aging test device further comprises a mainboard 5. The BMC 1, the operating system loading device 2, the chip body 31, the chip auxiliary system 32 and the aging test system 4 are electrically connected to the mainboard 5. Among them, the BMC 1 and the aging test system 4 are fixedly arranged on the mainboard 5 to form a mainboard system structure; the chip body 31 is detachably connected to the mainboard 5 to facilitate replacement of the chip body 31.

[0088] In the HTOL DFT test mode, the memory system 321 and the peripheral system 322 are in a non-working state, and the mainboard system cannot enter the operating system loading device 2. The host computer 6 is connected to the control subsystem 11 through the first network interface 12 to control the chip power supply subsystem 41 and the chip temperature control subsystem 42 to set and monitor the environment of the chip body 31 aging test, and at the same time, through the control interface 13, the test data is transmitted to the chip body 31, the test results are collected, and the chip aging test is started through the operating system loading device 2.

[0089] In the HTOL SLT test mode, the memory system 321 and the peripheral system 322 are in a normal working state, and the mainboard system is normally started. The host computer 6 is connected to the operating system loading device 2 and the control subsystem 11 through the network interface, respectively, and controls the chip power supply subsystem 41 and the chip temperature control subsystem 42 through the control subsystem 11 to set and monitor the environment of the chip body 31 aging test, and at the same time, through the control interface 13, the test data is transmitted to the chip body 31, the test results are collected, and the chip aging test is started through the operating system loading device 2.

[0090] The chip aging test device provided in the embodiment has simple structure, low manufacturing cost, high test efficiency, and can quickly complete production and construction of chip aging test environment. Based on the general mainboard form and configuration, the BMC in the mainboard system is used to realize chip aging power management, temperature control, test script transmission and test result uploading processing. At the same time, the chip aging test device can be placed in a laboratory environment or a common oven environment to complete the aging test, saving the space occupied by the chip aging test device.

[0091] In addition, the chip aging test device provided by the embodiment not only realizes the conventional chip aging test DFT mode, that is, only the chip auxiliary system 32 in the mainboard system is in an inactive state, but also realizes the SLT aging test of the chip body 31 in the normal working state, greatly increases the range of the aging chip test, and improves the compatibility of the chip aging test device. Meanwhile, the embodiment also improves the DFT aging test efficiency. Specifically, after the DFT aging test is completed, the system can be normally started to enter the subsystem, and the test result representation is quickly completed.

[0092] In the description of the present specification, the description referring to the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are contained in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0093] The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combinations of the technical features do not contradict, they should be considered as the scope of the present application.

[0094] The above embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A chip burn-in test apparatus, characterized by comprising: The chip aging test device comprises a mainboard, an aging test system and a BMC; The aging test system and the BMC are arranged on the mainboard and electrically connected through the mainboard, and the BMC controls the chip aging test system to set a chip body as an aging test environment.

2. The chip burn-in test apparatus according to claim 1, wherein The chip aging test device further comprises an operating system loading device and a chip auxiliary system; The BMC is electrically connected with the aging test system, and the aging test system and the BMC are electrically connected with the chip body through the mainboard, and the chip auxiliary system and the operating system loading device are communicatively connected with the chip body; The operating system loading device is configured to transmit test data to the chip body via a loaded operating system when the chip auxiliary system is in a working state, and start aging test when the chip body is set as an aging test environment; The BMC is configured to transmit the test data to the chip body when the chip auxiliary system is in a non-working state, and start aging test when the chip body is set as an aging test environment.

3. The chip burn-in test apparatus according to claim 2, wherein The BMC comprises a control subsystem, a first network interface, a control interface and a storage device; The first network interface and the control interface are electrically connected with the control subsystem, the control subsystem is electrically connected with the aging test system and the chip body through the control interface, and the storage device is electrically connected with the control subsystem.

4. The chip burn-in test apparatus according to claim 3, wherein The BMC further comprises a monitoring interface; The monitoring interface is electrically connected with the control subsystem, and the control subsystem is electrically connected with a monitoring device through the monitoring interface.

5. The chip burn-in test apparatus according to claim 3, wherein The BMC further comprises a display interface; The display interface is electrically connected with the control subsystem, and the BMC is electrically connected with an operating system loading device through the display interface.

6. The chip burn-in test apparatus according to claim 3, wherein The control interface comprises a JTAG communication interface; The control subsystem is electrically connected with the chip body through the JTAG communication interface.

7. The chip burn-in test apparatus according to claim 2, wherein The aging test system comprises a chip power supply subsystem and a chip temperature control subsystem; The chip power supply subsystem is electrically connected with the BMC and the chip body respectively, and the chip temperature control subsystem is electrically connected with the BMC and the chip body respectively; The BMC controls the voltage of the chip body through the chip power supply subsystem and controls the temperature of the chip body through the chip temperature control subsystem.

8. The chip burn-in test apparatus according to claim 7, wherein The chip power supply subsystem comprises a power supply chip and a regulation resistor; The power supply chip is electrically connected with the BMC and the regulation resistor respectively, and the regulation resistor is electrically connected with the chip body and the BMC; The power supply chip provides power supply to the chip body through the regulation resistor, the BMC acquires current data of the regulation resistor, and regulates the voltage output by the power supply chip.

9. The chip burn-in test apparatus of claim 7, wherein The chip temperature control subsystem comprises a heating subsystem and a heat dissipation subsystem; The BMC is electrically connected with the heating subsystem and the heat dissipation subsystem respectively; The BMC increases the temperature of the chip body through the heating subsystem and reduces the temperature of the chip body through the heat dissipation subsystem.

10. The chip burn-in test apparatus of claim 2, wherein The chip aging test device further comprises an upper computer; The host computer is electrically connected with the BMC and the operating system loading device; The host computer is configured to transmit test data to the chip body via an operating system loaded by the operating system loading device when the chip auxiliary system is in a working state, transmit the test data to the chip body by the BMC when the chip auxiliary system is in a non-working state, and start an aging test by the BMC when the chip body is set as an aging test environment.

11. The chip burn-in test apparatus according to any one of claims 2 to 10, wherein The chip auxiliary system comprises a memory subsystem and a peripheral subsystem. The memory subsystem is electrically connected with the chip body, and the peripheral subsystem is communicatively connected with the chip body.

12. The chip burn-in test apparatus of claim 11, wherein The peripheral subsystem comprises an information interaction interface. The peripheral subsystem is electrically connected with the operating system loading device through the information interaction interface.

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