Clock control circuit and storage device and system

Abstract

The utility model discloses a clock control circuit and storage device and system, this clock control circuit includes oscillation circuit, including first output and two first control end, oscillation circuit's first output is connected with the memory, and the two first control end of oscillation circuit is used for receiving the adjustment signal, temperature response module, including acquisition end and feedback end, and temperature response module gathers the temperature information of memory through acquisition end, the feedback end of temperature response module is electrically connected with the two first control end of oscillation circuit respectively, and the main control unit is used for generating adjustment signal and outputing to two first control end according to the temperature information that temperature response module gathered, to control the frequency of oscillation circuit output clock signal, in this way, through temperature response module, can gather the temperature information of memory in real time, and combine the main control unit and dynamically adjust the frequency of oscillation circuit output clock signal according to temperature change, to improve the reliability of memory operation.

Description

TECHNICAL FIELD

[0001] The utility model relates to data storage technical field, especially a clock control circuit and storage device and system. BACKGROUND

[0002] In modern semiconductor memories, such as NAND Flash and other non-volatile memories, the clock signal (CLK) is the core signal that controls internal operations. The read, write, and erase operations of the memory all need to be coordinated by the clock signal to ensure accurate storage and reading of data. The frequency of the clock signal has an important impact on the overall performance, power consumption, and data reliability of the memory.

[0003] Currently, the generation of internal clock signals in semiconductor memories is usually achieved through an oscillator circuit. The oscillator circuit in the prior art usually adopts a fixed frequency or a design with a certain stability to power fluctuations.

[0004] However, in a high-temperature environment, a clock signal with a fixed frequency cannot extend the write time, which may cause the write failure of the memory cell or the decline of data integrity; and in a low-temperature environment, it cannot shorten the operation time, which affects the efficiency and power consumption. Therefore, the related technology lacks flexibility when facing temperature changes, and it is difficult to adapt to the reliability and performance requirements of memory operations. SUMMARY

[0005] The main purpose of the utility model is to provide a clock control circuit, which aims to solve the problem of lack of flexible read-write operation when the memory faces temperature changes.

[0006] To achieve the above purpose, the utility model provides a clock control circuit applied to a memory, which comprises:

[0007] An oscillator circuit comprising a first output end and two first control ends, wherein the first output end of the oscillator circuit is electrically connected to the memory, and the two first control ends of the oscillator circuit are used to receive an adjustment signal;

[0008] A temperature sensing module comprising a collection end and a feedback end, wherein the temperature sensing module collects temperature information of the memory through the collection end;

[0009] A master control unit electrically connected to the two first control ends of the oscillator circuit and the feedback end of the temperature sensing module, respectively, wherein the master control unit is used to generate an adjustment signal and output it to the two first control ends according to the temperature information collected by the temperature sensing module, so as to control the frequency of the clock signal output by the oscillator circuit.

[0010] In some embodiments, the master control unit comprises:

[0011] a signal generation module comprising a second output end, the signal generation module being electrically connected to the feedback end, for receiving temperature information collected by the temperature sensing module and generating at least three adjustment signals;

[0012] a switch module comprising a second control end and two first connection ends, the second control end being electrically connected to the second output end, and the two first connection ends being electrically connected to the two first control ends.

[0013] In some embodiments, the signal generation module comprises:

[0014] a multiplexer electrically connected to the feedback end and the second output end respectively, the multiplexer being configured to receive temperature information fed back by the temperature sensing module;

[0015] a voltage generation module electrically connected to the multiplexer, the voltage generation module being configured to generate at least a first threshold voltage, a second threshold voltage and a third threshold voltage;

[0016] wherein the multiplexer is configured to select one of the first threshold voltage, the second threshold voltage and the third threshold voltage to output to the second output end according to the temperature information collected by the temperature sensing module.

[0017] In some embodiments, the voltage generation module comprises a bandgap voltage module and a voltage dividing module, the voltage dividing module being electrically connected to the bandgap voltage module, for dividing the voltage generated by the bandgap voltage module into at least the first threshold voltage, the second threshold voltage and the third threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage, and the second threshold voltage is greater than the third threshold voltage.

[0018] In some embodiments, the voltage generation module further comprises an operational amplifier electrically connected between the bandgap voltage module and the voltage dividing module, the operational amplifier being configured to amplify the voltage generated by the bandgap voltage module and output to the voltage dividing module.

[0019] In some embodiments, the switch module comprises two first switch tubes and two second switch tubes, a source of one of the first switch tubes being electrically connected to a power supply, a drain of one of the first switch tubes being electrically connected to one of the first connection ends, a drain and a gate of one of the first switch tubes being grounded through the other of the first switch tubes, and a gate of the other of the first switch tubes being electrically connected to the second control end.

[0020] One source electrode of the second switch tube is electrically connected to a power supply, one drain electrode of the second switch tube is electrically connected to another first connection end, another drain electrode and another gate electrode of the second switch tube are electrically connected to the first connection end, and another source electrode of the second switch tube is grounded.

[0021] In some embodiments, the oscillation circuit comprises at least one oscillation module, the oscillation module comprising a third output end, a third switch tube, a fourth switch tube and a capacitor, a source electrode of the third switch tube being electrically connected to a power supply, a drain electrode of the third switch tube being grounded through the fourth switch tube, the third output end being electrically connected to the drain electrode of the third switch tube, and one end of the capacitor being electrically connected to the third output end and the other end being grounded.

[0022] In some embodiments, the multiplexer comprises a first receiving end, a second receiving end and a third receiving end, and the voltage dividing module comprises a first resistor, a second resistor and a third resistor.

[0023] One end of the first resistor is electrically connected to the operational amplifier and the first receiving end, one end of the second resistor is electrically connected to the operational amplifier through the first resistor, the second receiving end is electrically connected to one end of the second resistor, the other end of the second resistor is grounded through the third resistor, and the third receiving end is electrically connected to the other end of the second resistor.

[0024] The utility model further proposes a storage device, including memory and aforementioned embodiment's clock control circuit.

[0025] The utility model further still proposes a storage system including aforementioned embodiment's storage device.

[0026] The utility model technical scheme has the advantages that through the temperature sensing module, the temperature information of the memory can be collected in real time, and the frequency of the clock signal output by the oscillation circuit is dynamically adjusted according to the temperature change in combination with the master control unit, so that the reliability of the memory operation is improved. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 It is a module electric connection schematic drawing of the clock control circuit in an embodiment of the utility model;

[0028] Figure 2 It is a module electric connection schematic drawing of the clock control circuit in an embodiment of the utility model;

[0029] Figure 3Part of circuit diagram of clock control circuit in one embodiment of the utility model;

[0030] Figure 4 Part of circuit diagram of clock control circuit in one embodiment of the utility model;

[0031] Figure 5 Part of circuit diagram of clock control circuit in one embodiment of the utility model.

[0032] Explanation of drawing reference numeral:

[0033] 100, oscillation circuit;A1, first output end;B1, first control end;

[0034] 110, oscillation module;A3, third output end;Q3, third switch tube;Q4, fourth switch tube;C1, capacitor;

[0035] 200, temperature sensing module;B2, acquisition end;B3, feedback end;

[0036] 300, main control unit;

[0037] 310, signal generation module;A2, second output end;

[0038] 320, multiplexer;A4, first receiving end;A5, second receiving end;A6, third receiving end;

[0039] 330, voltage generation module;

[0040] 331, band gap voltage module;

[0041] 332, voltage division module;R1, first resistor;R2, second resistor;R3, third resistor;

[0042] U1, operational amplifier;

[0043] 340, switch module;B4, second control end;B5, first connection end;

[0044] Q1, first switch tube;

[0045] Q2, second switch tube.

[0046] The utility model aims at realizing, function characteristics and advantage will combine embodiment, reference to the further explanation of attached drawing. Specific implementation

[0047] The schemes in the embodiments of the present application will be described in detail below with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of the present application.

[0048] It should be noted that all directional indications, such as upper, lower, left, right, front, back, etc., in the embodiments of the present application are only used to explain the relative positional relationship, movement condition, etc. between components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications will also change accordingly.

[0049] It should also be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or can have a middle element. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or can have a middle element.

[0050] In addition, the description of "first", "second" and the like in the present application is only for the purpose of description and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the protection scope required by the present application.

[0051] Referring to Figure 1 and Figure 2 The embodiment of the present application provides a clock control circuit applied to a memory, which comprises:

[0052] An oscillation circuit 100 comprises a first output end A1 and two first control ends B1, the first output end A1 of the oscillation circuit 100 is electrically connected to the memory, and the two first control ends B1 of the oscillation circuit 100 are used for receiving an adjustment signal;

[0053] A temperature sensing module 200 comprises a collection end B2 and a feedback end B3, and the temperature sensing module 200 collects temperature information of the memory through the collection end B2;

[0054] The main control unit 300 is electrically connected with the two first control ends B1 of the oscillation circuit 100 and the feedback end B3 of the temperature sensing module 200 respectively, and is used for generating an adjusting signal according to the temperature information collected by the temperature sensing module 200 and outputting the adjusting signal to the two first control ends B1, so as to control the frequency of the clock signal output by the oscillation circuit 100.

[0055] In the embodiment, the oscillation circuit 100 in the clock control circuit is mainly used for generating a clock signal required for internal operation of the memory. The oscillation circuit 100 includes a first output end A1 and two first control ends B1, and the generated clock signal is transmitted to the memory through the first output end A1, so as to control the time sequence and rhythm of read, write and erase operations of the memory.

[0056] The oscillation circuit 100 can be implemented by a crystal oscillator, an RC oscillator or a ring oscillator. The crystal oscillator is suitable for a scene with high requirement for the clock signal due to its high precision and stability, and the RC oscillator has the advantages of low cost and simple design.

[0057] In the memory, for example, a NAND Flash, the clock signal is a core signal for coordinating internal operations of the memory. The read operation needs the clock signal to accurately control the transmission time of data from a storage unit to an output end; the write operation (Program) relies on the clock signal to control the time of writing data into the storage unit; and the erase operation (Erase) needs the clock signal to ensure that the data in the storage unit is reliably cleared. Without the coordination of the clock signal, the operation of the memory will become chaotic, affecting the accuracy and reliability of data.

[0058] In the embodiment, the temperature sensing module 200 is used for collecting temperature information of the memory and transmitting the temperature information to the main control unit 300 through the feedback end B3. The temperature sensing module 200 can be implemented by a thermistor, a semiconductor temperature sensing module or an integrated temperature detection chip (such as LM75 or DS18B20). The function thereof is to detect real-time temperature changes when the memory is running.

[0059] The operation characteristics of the memory are extremely sensitive to temperature. For example, in a high-temperature environment, the threshold voltage (Vt) of the storage unit is low, which may cause insufficient write (Program) time and information storage failure; and in a low-temperature environment, the Vt is high, which may cause excessively long write time and increased power consumption. The erase (Erase) and read (Read) operations are also affected by temperature. Therefore, in order to improve the operation reliability and efficiency of the memory, the temperature sensing module 200 is arranged in the embodiment, an adjusting signal is generated by the main control unit 300, and the frequency of the clock signal output by the oscillation circuit 100 is dynamically adjusted, so as to adapt to operation requirements under different temperature conditions.

[0060] In the embodiment, the clock control circuit dynamically adjusts the output frequency of the oscillation circuit 100 according to the temperature information of the memory, so as to optimize the operation performance of the memory.

[0061] When the temperature is high, the temperature sensing module 200 detects that the memory is in a high-temperature state through the acquisition end B2, and transmits the temperature information to the main control unit 300. The main control unit 300 generates an adjustment signal according to the high-temperature information and outputs the adjustment signal to the two first control ends B1 of the oscillation circuit 100. The oscillation circuit 100 reduces the frequency of the clock signal according to the adjustment signal, thereby prolonging the write (Program) time and reducing the erase (Erase) time, so as to improve the threshold voltage distribution of the memory unit and improve the operation reliability.

[0062] When the temperature is moderate, the temperature sensing module 200 detects that the memory is in a normal-temperature state, and the main control unit 300 generates a default adjustment signal to maintain the frequency of the clock signal output by the oscillation circuit 100 within a standard value range. At this time, the read and write operations of the memory are performed with normal timing, ensuring the balance between performance and efficiency.

[0063] When the temperature sensing module 200 detects that the memory is in a low-temperature state, the main control unit 300 generates an adjustment signal according to the temperature information and outputs the adjustment signal to the two first control ends B1 of the oscillation circuit 100. The oscillation circuit 100 increases the frequency of the clock signal according to the adjustment signal, thereby shortening the write (Program) time and increasing the erase (Erase) time, so as to reduce power consumption and improve the operation efficiency of the memory unit.

[0064] The beneficial effects of the technical scheme of the utility model lie in that: through the temperature sensing module 200, the temperature information of the memory can be collected in real time, and the frequency of the clock signal output by the oscillation circuit is dynamically adjusted according to the temperature change by the main control unit 300, thereby improving the reliability of the memory operation. At the same time, the read and write times and the erase time are dynamically adjusted according to the temperature, thereby effectively reducing power consumption and improving performance. In addition, the design can ensure the stable operation of the memory within a wide temperature range, prolong the service life of the memory, significantly improve the adaptability of the traditional fixed clock frequency circuit to temperature change, and improve the overall performance and reliability of the memory.

[0065] Continuing to refer to Figure 2 In the embodiment, the main control unit 300 comprises:

[0066] The signal generation module 310 comprises a second output end A2, and the signal generation module 310 is electrically connected with the feedback end B3 and is used for receiving the temperature information collected by the temperature sensing module 200 and generating at least three adjustment signals;

[0067] The switch module 340 includes a second control end B4 and two first connection ends B5. The second control end B4 is electrically connected to the second output end A2. The two first connection ends B5 are electrically connected to the two first control ends B1.

[0068] In this embodiment, the signal generation module 310 has a second output end A2, which is electrically connected to the feedback end B3 of the temperature sensing module 200, for receiving temperature information collected by the temperature sensing module 200. The signal generation module 310 generates at least three adjustment signals according to the temperature information. The adjustment signals can be driving voltages. Specifically, different temperature parameters correspond to different driving voltages.

[0069] The switch module 340 has a second control end B4 and two first connection ends B5. The second control end B4 is electrically connected to the second output end A2 of the signal generation module 310, for receiving the generated adjustment signals. The two first connection ends B5 are respectively electrically connected to the two first control ends B1 of the oscillation circuit 100. Specifically, the switch module 340 controls its conduction degree by receiving the adjustment signals, thereby changing the voltages on the two first control ends B1.

[0070] In the working process, the temperature sensing module 200 collects real-time temperature information of the memory through the collection end B2, and transmits the temperature information to the signal generation module 310 through the feedback end B3. The signal generation module 310 generates corresponding adjustment signals (for example, driving voltages V1, V2, V3) according to the received temperature information, and outputs the adjustment signals to the second control end B4 of the switch module 340 through the second output end A2.

[0071] After receiving the driving voltages, the switch module 340 changes its conduction degree. The conduction degree of the switch module 340 directly affects the output voltages of the two first connection ends B5. These voltages are transmitted to the two first control ends B1 of the oscillation circuit 100, for further controlling the running state of the oscillation circuit 100.

[0072] The oscillation circuit 100 adjusts the frequency of the output clock signal according to the voltages received by the two first control ends B1. For example, under high temperature conditions, the oscillation circuit 100 reduces the frequency of the clock signal to prolong the memory write (Program) time and reduce the erase (Erase) time.

[0073] Under medium temperature conditions, the oscillation circuit 100 maintains the frequency of the clock signal within a normal range, to ensure the balance of the operation performance.

[0074] Under low temperature conditions, the oscillation circuit 100 increases the frequency of the clock signal to shorten the write time and increase the erase time.

[0075] The technical scheme of the embodiment realizes dynamic adjustment of the working state of the oscillation circuit 100 according to the temperature information collected by the temperature sensing module 200, and further adjusts the frequency of the clock signal, so as to ensure the operation reliability of the storage device under different temperature conditions.

[0076] Referring to Figure 3 In the embodiment, the signal generation module 310 includes:

[0077] The multiplexer 320 is electrically connected to the feedback end B3 and the second output end A2 respectively, and is configured to receive the temperature information fed back by the temperature sensing module 200.

[0078] The voltage generation module 330 is electrically connected to the multiplexer 320, and is configured to generate at least a first threshold voltage, a second threshold voltage and a third threshold voltage.

[0079] The multiplexer 320 is configured to select one of the first threshold voltage, the second threshold voltage and the third threshold voltage according to the temperature information collected by the temperature sensing module 200 and output the selected one to the second output end A2.

[0080] In the embodiment, the signal generation module 310 includes the multiplexer 320 and the voltage generation module 330, which work together to realize the function of dynamically adjusting the output voltage according to the temperature information collected by the temperature sensing module 200.

[0081] Specifically, the multiplexer 320 is electrically connected to the feedback end B3 and the second output end A2 of the temperature sensing module 200 respectively, and is configured to receive the temperature information collected and fed back by the temperature sensing module 200, and select one of the first threshold voltage, the second threshold voltage and the third threshold voltage generated by the voltage generation module 330 according to the temperature information and output the selected one to the second output end A2. The voltage generation module 330 is electrically connected to the multiplexer 320 and can generate a plurality of different threshold voltages, which correspond to different temperature conditions respectively and are used to adjust the working state of the subsequent module.

[0082] In the specific working process, the temperature sensing module 200 transmits the real-time collected temperature information to the multiplexer 320 through the feedback end B3. According to the different temperature ranges, the multiplexer 320 can automatically select the appropriate threshold voltage generated by the voltage generation module 330, for example, selecting the first threshold voltage to reduce the operation frequency of the subsequent module under high temperature conditions, selecting the second threshold voltage to maintain the normal operation frequency under normal temperature conditions, and selecting the third threshold voltage to increase the operation frequency under low temperature conditions. The selected threshold voltage is transmitted to the second control end B4 of the switch module 340 through the second output end A2, and then controls the conduction degree of the switch module 340.

[0083] The switch module 340 adjusts its conduction degree according to the received threshold voltage, thereby changing the voltage on the two first control terminals B1 of the oscillation circuit 100, adjusting the working state of the oscillation circuit 100, and finally achieving dynamic adjustment of the clock signal frequency. For example, in a high-temperature environment, the write (Program) time is extended and the erase time is reduced by lowering the clock signal frequency, thereby improving the reliability of memory operation; in a low-temperature environment, the write time is shortened and the erase time is increased by increasing the clock signal frequency, thereby improving the operation efficiency; in a normal-temperature environment, the normal clock signal frequency is maintained to ensure the balance between performance and efficiency.

[0084] Through the design of the embodiment, the combination of the multiplexer 320 and the voltage generation module 330 enables the master control unit 300 to dynamically adapt to the requirements under different temperature conditions, that is, the club can adjust the working state of the oscillation circuit 100 according to the real-time temperature, adapt to a wide temperature range, and thus optimize the read / write and erase operation time to ensure operation efficiency and reliability. At the same time, by dynamically adjusting the frequency, power consumption can also be effectively reduced, prolonging the service life of the memory.

[0085] Continuing to refer to Figure 3 In the embodiment, the voltage generation module 330 includes a bandgap voltage module 331 and a voltage dividing module 332, and the voltage dividing module 332 is electrically connected to the bandgap voltage module 331 and is used to divide the voltage generated by the bandgap voltage module 331 into at least a first threshold voltage, a second threshold voltage, and a third threshold voltage. Among them, the first threshold voltage is greater than the second threshold voltage, and the second threshold voltage is greater than the third threshold voltage.

[0086] In the embodiment, the voltage generation module 330 includes a bandgap voltage module 331 and a voltage dividing module 332, and the voltage dividing module 332 is electrically connected to the bandgap voltage module 331 and is used to divide the voltage generated by the bandgap voltage module 331 into at least a first threshold voltage, a second threshold voltage, and a third threshold voltage. Among them, the first threshold voltage is greater than the second threshold voltage, and the second threshold voltage is greater than the third threshold voltage.

[0087] The bandgap voltage module 331 is a kind of precise reference voltage generation circuit, which generates a temperature-stable reference voltage by using the positive temperature coefficient and negative temperature coefficient characteristics of semiconductor materials. Specifically, the bandgap voltage module 331 combines the positive temperature characteristics of diodes and the negative temperature characteristics of transistors to form a reference voltage (usually about 1.2V) that is almost unaffected by temperature. Such a voltage has high precision and high stability, and is suitable for circuit modules that require reliable reference voltage.

[0088] In this embodiment, the voltage generation module 330 further includes an operational amplifier U1 electrically connected between the bandgap voltage module 331 and the voltage dividing module 332. The operational amplifier U1 is configured to amplify the voltage generated by the bandgap voltage module 331 and output to the voltage dividing module 332.

[0089] It should be noted that in this embodiment, the voltage dividing module 332 is only used to generate the first threshold voltage, the second threshold voltage and the third threshold voltage. In other embodiments, more threshold voltages can be generated according to specific requirements. In addition, in addition to using the voltage dividing module 332, an adjustable voltage regulator can also be used to generate multiple different threshold voltages directly according to the input bandgap reference voltage. The adjustable voltage regulator precisely controls the output voltage by changing the proportion of the internal feedback network.

[0090] The voltage dividing module 332 of this embodiment can be expanded to generate more threshold voltages according to actual requirements. In addition, the voltage dividing module 332 and the bandgap voltage module 331 used in this embodiment have good compatibility and can be flexibly adapted to the requirements of other modules or systems, thereby further improving the applicability and stability of the circuit.

[0091] Referring to Figure 3 In this embodiment, the voltage generation module 330 further includes an operational amplifier U1 electrically connected between the bandgap voltage module 331 and the voltage dividing module 332. The operational amplifier U1 is configured to amplify the voltage generated by the bandgap voltage module 331 and output to the voltage dividing module 332.

[0092] In this embodiment, the voltage generation module 330 adds the operational amplifier U1, which is connected between the bandgap voltage module 331 and the voltage dividing module 332. The main function of the operational amplifier U1 is to amplify the voltage generated by the bandgap voltage module 331 and then transmit it to the voltage dividing module 332. In this way, not only the accuracy of the voltage generated by the voltage dividing module 332 is improved, but also the overall driving capability and stability of the voltage generation module 330 are enhanced.

[0093] Specifically, the reference voltage generated by the bandgap voltage module 331 is usually small (e.g. about 1.2V). The operational amplifier U1 amplifies the reference voltage to a voltage range suitable for the input of the voltage dividing module 332 by its high input impedance and low output impedance characteristics, so as to generate multiple threshold voltages subsequently.

[0094] The voltage division module 332 is usually composed of a plurality of resistance networks, and the reference voltage may fluctuate due to the load current. Therefore, the low output impedance of the operational amplifier U1 can provide stronger driving capability, ensuring that the voltage division module 332 can work stably without affecting the performance of the bandgap voltage module 331. At the same time, the operational amplifier U1 can effectively isolate the bandgap voltage module 331 from the voltage division module 332, avoiding the interference of load changes on the bandgap voltage module 331, thereby improving the stability and precision of the entire voltage generation module 330.

[0095] In the working process, the bandgap voltage module 331 generates a stable reference voltage and inputs it to the positive input terminal of the operational amplifier U1 through the signal line. The operational amplifier U1 amplifies the input reference voltage, and the amplified voltage is transmitted from the output terminal of the operational amplifier U1 to the voltage division module 332. The voltage division module 332 uses the internal resistance network to divide the amplified voltage to generate the first threshold voltage, the second threshold voltage and the third threshold voltage for driving the switch module 340 to work.

[0096] In this embodiment, by adding the operational amplifier U1 between the bandgap voltage module 331 and the voltage division module 332, the reference voltage is amplified and stably output, improving the input voltage quality of the voltage division module 332 and the reliability of the overall system.

[0097] Referring to Figure 4 In this embodiment, the switch module 340 includes two first switch tubes Q1 and two second switch tubes Q2. The source electrode of one first switch tube Q1 is electrically connected to the power supply, the drain electrode of one first switch tube Q1 is electrically connected to one first connection end B5, the drain electrode and the gate electrode of one first switch tube Q1 are grounded through the other first switch tube Q1, and the gate electrode of the other first switch tube Q1 is electrically connected to the second control end B4.

[0098] The source electrode of one second switch tube Q2 is electrically connected to the power supply, the drain electrode of one second switch tube Q2 is electrically connected to the other first connection end B5, the drain electrode and the gate electrode of the other second switch tube Q2 are electrically connected to the first connection end B5, and the source electrode of the other second switch tube Q2 is grounded.

[0099] In this embodiment, the switch module 340 can be built by two first switch tubes Q1 and two second switch tubes Q2, which is used to adjust the control signal voltage of the oscillation circuit 100, so as to realize the dynamic adjustment of the clock signal frequency.

[0100] Specifically, one first switch tube Q1 can be a P-type MOS tube, the source electrode of which is electrically connected to the power supply, and the drain electrode of which is electrically connected to one first connection end B5.

[0101] Another first switch tube Q1 can be an N-type MOS tube, whose drain and gate are grounded through another first switch tube Q1, and whose gate is electrically connected to the second control end B4.

[0102] A second switch tube Q2 can be a P-type MOS tube, whose source is electrically connected to a power supply, and whose drain is electrically connected to another first connection end B5.

[0103] Another second switch tube Q2 can be an N-type MOS tube, whose drain and gate are electrically connected to the first connection end B5, and whose source is grounded.

[0104] In the working process, the signal generation module 310 generates at least a first threshold voltage, a second threshold voltage and a third threshold voltage according to the preset condition, and receives temperature information (such as memory temperature or environmental temperature) through the feedback end B3, selects the corresponding threshold voltage according to the temperature information and outputs to the second control end B4.

[0105] When the second control end B4 receives the threshold voltage, the N-type MOS tube (another first switch tube Q1) electrically connected thereto is turned on; after being turned on, the voltage of the first connection end B5 is adjusted by the switch module 340, which is specifically that when the first switch tube Q1 is turned on, the voltage of the first connection end B5 is pulled down;

[0106] The change of this voltage directly acts on the electrically connected oscillation circuit 100, changes the control end voltage of the oscillation circuit 100, and thus adjusts the frequency of the clock signal output by the oscillation circuit 100.

[0107] The degree of conduction of the switch module 340 changes with the input voltage of the second control end B4. Specifically, when the second control end B4 inputs a higher threshold voltage, the P-type MOS tube gradually closes, and the N-type MOS tube gradually turns on, and the voltage of the first connection end B5 decreases;

[0108] On the contrary, when a lower threshold voltage is input, the P-type MOS tube is turned on, and the N-type MOS tube is closed, and the voltage of the first connection end B5 rises, so that the continuous voltage change can realize the dynamic adjustment of the clock signal frequency by controlling the oscillation circuit 100.

[0109] At high temperature, the signal generation module 310 selects and outputs a higher threshold voltage (such as the first threshold voltage) to the second control end B4. According to the low threshold voltage, the switch module 340 gradually closes the P-type MOS tube and turns on the N-type MOS tube, and the voltage of the first connection end B5 is greatly pulled down. The control end voltage of the oscillation circuit 100 decreases, and the clock signal frequency decreases, so as to prolong the write time, reduce the erase time, and improve the reliability of the memory.

[0110] At room temperature, the signal generation module 310 outputs a medium threshold voltage (such as the second threshold voltage), the switch module 340 maintains a moderate conduction state, the voltage of the first connection end B5 is kept at a medium level, the control end voltage of the oscillation circuit 100 is kept in a normal range, the clock signal frequency is maintained at a standard value, and the balance between operation efficiency and performance is ensured.

[0111] At low temperature, the signal generation module 310 selects and outputs a lower threshold voltage (such as the first threshold voltage) to the second control end B4. The switch module 340 gradually turns on the P-type MOS tube and turns off the N-type MOS tube, and the voltage of the first connection end B5 rises. The control end voltage of the oscillation circuit 100 rises, and the clock signal frequency accelerates to shorten the write time, increase the erase time, improve the operation efficiency, and reduce the power consumption.

[0112] Through the threshold voltage generated by the signal generation module 310 and the conduction control of the switch module 340, the real-time adjustment of the clock signal frequency is realized to adapt to the memory operation requirements under different temperature conditions.

[0113] Referring to Figure 5 In this embodiment, the oscillation circuit 100 includes at least one oscillation module 110, and the oscillation module 110 includes a third output end A3, a third switch tube Q3, a fourth switch tube Q4, and a capacitor C1. The source electrode of the third switch tube Q3 is electrically connected to the power supply, the drain electrode of the third switch tube Q3 is grounded through the fourth switch tube Q4, the third output end A3 is electrically connected to the drain electrode of the third switch tube Q3, and one end of the capacitor C1 is electrically connected to the third output end A3 and the other end is grounded.

[0114] In this embodiment, the oscillation circuit 100 includes at least one oscillation module 110, and the oscillation module 110 is used to generate a clock signal and output through the third output end A3. The main components of the oscillation module 110 include a third switch tube Q3, a fourth switch tube Q4, a capacitor C1, and a third output end A3.

[0115] The oscillation module 110 repeatedly receives high-level and low-level signals through the first control end B1 (CTL_P) and the second control end B4 (CTL_N). The high-level signal makes the third switch tube Q3 and the fourth switch tube Q4 alternately conduct and cut off, thereby controlling the flow of current and the charging and discharging of the capacitor C1.

[0116] Specifically, when the third switch tube Q3 is turned on and the fourth switch tube Q4 is cut off, the capacitor C1 starts to charge, and the voltage of the third output end A3 rises;

[0117] When the fourth switch Q4 is turned on and the third switch Q3 is turned off, the capacitor C1 begins to discharge, and the voltage of the third output terminal A3 decreases. In this way, by alternately inputting the high and low levels of the control signal, the capacitor C1 continuously charges and discharges, thereby generating a periodic clock signal at the third output terminal A3. Thus, the voltage signal output by the third output terminal A3 has a certain periodicity, i.e., the clock signal generated by the oscillation module 110.

[0118] In the working process, when the first control terminal B1 (CTL_P), the second control terminal B4 (CTL_N), and the IN pin are all low-level signals, the third switch Q3 (P-type MOS tube) is turned on, and the fourth switch Q4 (N-type MOS tube) is turned off. At this time, the current flows from the power supply (B1) to the capacitor C1, charging the capacitor C1, and the voltage of the third output terminal A3 rises.

[0119] When the first control terminal B1 (CTL_P), the second control terminal B4 (CTL_N), and the IN pin are all high-level signals, the third switch Q3 (P-type MOS tube) is turned off, and the fourth switch Q4 (N-type MOS tube) is turned on. The capacitor C1 begins to discharge, and the voltage of the third output terminal A3 decreases.

[0120] By alternately inputting the high and low levels of the signals of the first control terminal B1 (CTL_P), the second control terminal B4 (CTL_N), and the IN pin, the third switch Q3 and the fourth switch Q4 repeatedly and alternately turn on and turn off, and the capacitor C1 continuously charges and discharges, thereby generating a periodic clock signal at the third output terminal A3.

[0121] The signal generation module 310 controls the conduction degree of the switch module 340 according to the temperature parameter. For example, under high-temperature conditions, the signal generation module 310 is configured to, when the first control terminal B1 (CTL_P), the second control terminal B4 (CTL_N), and the IN pin are all high-level signals, pull down the levels of the first control terminal B1 (CTL_P) and the second control terminal B4 (CTL_N) to reduce the conduction ability of the third switch Q3 (slow down the current passing through), thereby prolonging the charging time of the capacitor C1 and reducing the output frequency of the clock signal. In this way, by dynamically adjusting the output of the signal generation module 310, the oscillation module 110 can adapt to the working requirements under different temperature conditions, optimize the system performance, and improve the running stability.

[0122] Referring to Figure 3 In this embodiment, the multiplexer 320 includes a first receiving terminal A4, a second receiving terminal A5, and a third receiving terminal A6, and the voltage division module 332 includes a first resistor R1, a second resistor R2, and a third resistor R3.

[0123] One end of the first resistor R1 is electrically connected to the operational amplifier U1 and the first receiving end A4, one end of the second resistor R2 is electrically connected to the operational amplifier U1 through the first resistor R1, one end of the second receiving end A5 is electrically connected to one end of the second resistor R2, and the other end of the second resistor R2 is electrically connected to the third receiving end A6 through the third resistor R3.

[0124] In the embodiment, the multiplexer 320 includes the first receiving end A4, the second receiving end A5 and the third receiving end A6, and the voltage dividing module 332 is composed of three series resistors including the first resistor R1, the second resistor R2 and the third resistor R3.

[0125] One end of the first resistor R1 is electrically connected to the output end of the operational amplifier U1 and the first receiving end A4 of the multiplexer 320. One end of the second resistor R2 is electrically connected to the operational amplifier U1 through the first resistor R1, and the other end of the second resistor R2 is electrically connected to the second receiving end A5 of the multiplexer 320. One end of the third resistor R3 is electrically connected to the second receiving end A5 through the second resistor R2, and the other end of the third resistor R3 is grounded. The third receiving end A6 of the multiplexer 320 is electrically connected to the connection point of the second resistor R2 and the third resistor R3.

[0126] Specifically, the multiplexer 320 switches among the first receiving end A4, the second receiving end A5 and the third receiving end A6 according to the control signal, so as to select different voltage values for output. The voltage dividing module 332 sequentially divides the input voltage into different voltage values through the series structure of the three resistors, and supplies the voltage values to the receiving ends of the multiplexer 320.

[0127] The embodiment adopts the simple and efficient resistor voltage dividing and multiplexing structure, and can flexibly select different voltage outputs according to requirements, and is suitable for dynamic voltage adjustment scenarios.

[0128] The utility model further proposes a kind of storage device, including memory and clock control circuit, the specific structure of this storage device refers to above-mentioned embodiment, since the present storage device has adopted all the technical solutions of above-mentioned all embodiments, at least has all the technical effects brought by the technical solutions of above-mentioned embodiments, here will not be elaborated one by one.

[0129] In the embodiment, the storage device introduces the clock control circuit, effectively improves the read-write operation performance of the memory. In the read operation, the clock control circuit can dynamically adjust the frequency of the clock signal according to the temperature condition, to ensure the accuracy and efficiency of data transmission. In the write operation, the clock control circuit optimizes the clock frequency, so that the threshold voltage distribution of the storage unit is more uniform, thereby improving the success rate of writing and the long-term reliability of data.

[0130] In addition, since the clock control circuit can adapt to different temperature conditions, the operation stability of the storage device in high-temperature and low-temperature environments is significantly enhanced, and the problem of read / write failure of the traditional memory under extreme conditions is avoided.

[0131] The utility model further still proposes a kind of storage system, including the storage device of preceding embodiment.Can adapt to the work demand under different temperature conditions, optimize system performance and improve operating stability.

[0132] The above-mentioned is only part or preferred embodiment of the utility model, and both words and drawings cannot limit the range of protection of the utility model, and equivalent structural transformation is made using the utility model specification and drawing contents under the concept of the whole of the utility model, or direct / indirect application in other related technical fields are included in the range of protection of the utility model.

Claims

1. A clock control circuit applied to a memory, characterized by, The clock control circuit comprises: an oscillation circuit comprising a first output end and two first control ends, the first output end of the oscillation circuit being electrically connected to the memory, and the two first control ends of the oscillation circuit being used for receiving an adjustment signal; a temperature sensing module comprising a collection end and a feedback end, the temperature sensing module collecting temperature information of the memory through the collection end; a master control unit, the master control unit being electrically connected to the two first control ends of the oscillation circuit and the feedback end of the temperature sensing module respectively, and the master control unit being used for generating an adjustment signal according to the temperature information collected by the temperature sensing module and outputting the adjustment signal to the two first control ends to control the frequency of the clock signal output by the oscillation circuit.

2. The clock control circuit of claim 1, wherein, The master control unit comprises: a signal generation module comprising a second output end, the signal generation module being electrically connected to the feedback end, used for receiving the temperature information collected by the temperature sensing module, and generating at least three adjustment signals; a switch module comprising a second control end and two first connection ends, the second control end being electrically connected to the second output end, and the two first connection ends being electrically connected to the two first control ends.

3. The clock control circuit of claim 2, wherein, The signal generation module comprises: a multiplexer being electrically connected to the feedback end and the second output end respectively, the multiplexer being used for receiving the temperature information fed back by the temperature sensing module; a voltage generation module being electrically connected to the multiplexer, the voltage generation module being configured to generate at least a first threshold voltage, a second threshold voltage and a third threshold voltage; wherein the multiplexer is configured to select one of the first threshold voltage, the second threshold voltage and the third threshold voltage to output to the second output end according to the temperature information collected by the temperature sensing module.

4. The clock control circuit of claim 3, wherein, The voltage generation module comprises a bandgap voltage module and a voltage dividing module, the voltage dividing module being electrically connected to the bandgap voltage module, used for dividing the voltage generated by the bandgap voltage module into at least the first threshold voltage, the second threshold voltage and the third threshold voltage, wherein the first threshold voltage is greater than the second threshold voltage, and the second threshold voltage is greater than the third threshold voltage.

5. The clock control circuit of claim 4, wherein, The voltage generation module further comprises an operational amplifier, the operational amplifier being electrically connected between the bandgap voltage module and the voltage dividing module, and the operational amplifier being used for amplifying the voltage generated by the bandgap voltage module and outputting the voltage to the voltage dividing module.

6. The clock control circuit according to claim 2 or 4, characterized by The switch module comprises two first switch tubes and two second switch tubes, a source electrode of one of the first switch tubes being electrically connected to a power supply, a drain electrode of one of the first switch tubes being electrically connected to one of the first connection ends, a drain electrode and a gate electrode of one of the first switch tubes being grounded through the other of the first switch tubes, and a gate electrode of the other of the first switch tubes being electrically connected to the second control end; a source electrode of one of the second switch tubes being electrically connected to the power supply, a drain electrode of one of the second switch tubes being electrically connected to the other of the first connection ends, a drain electrode and a gate electrode of the other of the second switch tubes being electrically connected to the first connection ends, and a source electrode of the other of the second switch tubes being grounded.

7. The clock control circuit of claim 1, wherein, The oscillation circuit comprises at least one oscillation module, the oscillation module comprising a third output end, a third switch tube, a fourth switch tube and a capacitor, a source of the third switch tube being electrically connected to a power supply, a drain of the third switch tube being grounded through the fourth switch tube, the third output end being electrically connected to the drain of the third switch tube, one end of the capacitor being electrically connected to the third output end, and the other end being grounded.

8. The clock control circuit of claim 5, wherein, The multiplexer comprises a first receiving end, a second receiving end and a third receiving end, and the voltage dividing module comprises a first resistor, a second resistor and a third resistor. The first resistor has one end electrically connected to the operational amplifier and the first receiving end, the second resistor has one end electrically connected to the operational amplifier through the first resistor, the second receiving end is electrically connected to one end of the second resistor, the other end of the second resistor is grounded through the third resistor, and the third receiving end is electrically connected to the other end of the second resistor.

9. A memory device, comprising: The memory device comprises a memory and a clock control circuit as claimed in any one of claims 1 to 8.

10. A storage system, characterized by The memory device comprises the memory device as claimed in claim 9.

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