Power semiconductor device

Abstract

The utility model discloses a power semiconductor device, the power semiconductor device comprises a copper-clad ceramic substrate and at least three semiconductor chip sets, the semiconductor chip sets are electrically connected with the copper-clad ceramic substrate through bonding wires, and the at least three semiconductor chip sets are sequentially arranged along a first direction; the semiconductor chip set comprises an upper bridge arm circuit, a lower bridge arm circuit and a first connecting terminal, and the upper bridge arm circuit and the lower bridge arm circuit are sequentially arranged in the second direction; the upper bridge arm circuit and the lower bridge arm circuit comprise two semiconductor chips which are connected in parallel, and the semiconductor chips of the upper bridge arm circuit and the lower bridge arm circuit are connected with the first connecting terminals respectively. Each of the at least three semiconductor chip sets of the power semiconductor device comprises the upper bridge arm circuit and the lower bridge arm circuit, and each of the upper bridge arm circuit and the lower bridge arm circuit comprises the two semiconductor chips which are connected in parallel, so that the consistency of the at least three semiconductor chip sets is good, the parasitic parameters of the power semiconductor device can be reduced, and the reliability of the power semiconductor device is improved. The present invention improves current equalization of a power semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a power semiconductor device. BACKGROUND

[0002] With the development of technology and social needs, power semiconductor devices are rapidly developing, and the market size is continuously growing. Higher requirements are put forward for power semiconductor devices applied in various fields. For example, the power density, efficiency and performance of power semiconductor devices need to be further improved.

[0003] The existing power semiconductor device is more sensitive to the parasitic parameters introduced by the package at a high switching speed, resulting in poor current sharing of the semiconductor chip. CONTENT OF THE UTILITY MODEL

[0004] In order to solve the technical problem of poor current sharing in the prior art, the present application provides a power semiconductor device.

[0005] In order to solve the technical problem in the prior art, the present application provides a power semiconductor device, which comprises a copper-clad ceramic substrate and at least three semiconductor chip groups. The at least three semiconductor chip groups are electrically connected to the copper-clad ceramic substrate by bonding wires, and the at least three semiconductor chip groups are arranged in sequence along a first direction. The semiconductor chip group comprises an upper bridge arm circuit, a lower bridge arm circuit and a first connection terminal. The upper bridge arm circuit and the lower bridge arm circuit are arranged in sequence along a second direction, and the second direction is perpendicular to the first direction. The upper bridge arm circuit comprises two semiconductor chips in parallel, and the lower bridge arm circuit comprises two semiconductor chips in parallel. The semiconductor chips of the upper bridge arm circuit and the lower bridge arm circuit are connected to the first connection terminal.

[0006] Optionally, the semiconductor chip group further comprises a second connection terminal and a third connection terminal. The first connection terminal, the second connection terminal and the third connection terminal surround the semiconductor chips of the upper bridge arm circuit and the lower bridge arm circuit. The first end of the semiconductor chip of the upper bridge arm circuit is connected to the second connection terminal, the second end of the semiconductor chip of the upper bridge arm circuit is connected to the first connection terminal, the first end of the semiconductor chip of the lower bridge arm circuit is connected to the first connection terminal, and the second end of the semiconductor chip of the lower bridge arm circuit is connected to the third connection terminal.

[0007] Optionally, the first connection terminal is an AC connection terminal, the second connection terminal is a DC+ connection terminal, and the third connection terminal is a DC- connection terminal.

[0008] Optionally, the upper bridge arm circuit comprises two parallel first transistors, a first driving terminal and a second driving terminal, a drain of the first transistor is connected with the second connection terminal, a gate of the first transistor is connected with the first driving terminal, an auxiliary source of the first transistor is connected with the second driving terminal, and a power source of the first transistor is connected with the first connection terminal.

[0009] Optionally, the lower bridge arm circuit comprises two parallel second transistors, a third driving terminal and a fourth driving terminal, the second transistors are in parallel, a drain of the second transistor is connected with the first connection terminal, a gate of the second transistor is connected with the third driving terminal, an auxiliary source of the second transistor is connected with the fourth driving terminal, and a power source of the second transistor is connected with the third connection terminal.

[0010] Optionally, the auxiliary source of the first transistor is connected with the second driving terminal through the bonding wire, and the auxiliary source of the second transistor is connected with the fourth driving terminal through the bonding wire, so as to realize Kelvin connection.

[0011] Optionally, a first driving gate copper foil is welded on the copper clad ceramic substrate, the upper bridge arm circuit further comprises a first driving resistor, the first driving resistor is arranged on one side of the first driving gate copper foil, the gate of the first transistor is connected with the first driving gate copper foil through the bonding wire and the first driving resistor, so as to be connected with the first driving terminal through the first driving gate copper foil.

[0012] Optionally, the copper clad ceramic substrate further comprises a first gate resistor copper foil and a first auxiliary source copper foil, the first gate resistor copper foil is located between the first auxiliary source copper foil and the first driving gate copper foil, and the first driving gate copper foil, the first gate resistor copper foil and the first auxiliary source copper foil are arranged in sequence along the first direction, the first driving resistor is arranged on the first gate resistor copper foil, and the auxiliary source of the first transistor is connected with the first auxiliary source copper foil through the bonding wire, so as to be connected with the second driving terminal through the first auxiliary source copper foil.

[0013] Optionally, the copper clad ceramic substrate comprises a first driving gate copper foil and a first auxiliary source copper foil, the first driving gate copper foil and the first auxiliary source copper foil are arranged in sequence along the second direction, the gate of the first transistor is connected with the first driving gate copper foil through the bonding wire, so as to be connected with the first driving terminal through the first driving gate copper foil; and the auxiliary source of the first transistor is connected with the first auxiliary source copper foil through the bonding wire, so as to be connected with the second driving terminal through the first auxiliary source copper foil.

[0014] Optionally, the semiconductor chip is at least one of a field effect transistor, a bipolar transistor, a diode, and a gallium nitride chip.

[0015] Compared with the prior art, the power semiconductor device provided by the application comprises a copper-clad ceramic substrate and at least three semiconductor chip groups, the at least three semiconductor chip groups are electrically connected to the copper-clad ceramic substrate through bonding wires respectively, and the at least three semiconductor chip groups are arranged in sequence along a first direction; wherein the semiconductor chip group comprises an upper bridge arm circuit, a lower bridge arm circuit, and a first connection terminal, the upper bridge arm circuit and the lower bridge arm circuit are arranged in sequence along a second direction, and the second direction is perpendicular to the first direction; the upper bridge arm circuit comprises two semiconductor chips in parallel, the lower bridge arm circuit comprises two semiconductor chips in parallel, and the semiconductor chips of the upper bridge arm circuit and the lower bridge arm circuit are connected to the first connection terminal respectively. In the foregoing manner, the at least three semiconductor chip groups of the power semiconductor device each comprise an upper bridge arm circuit and a lower bridge arm circuit, and the upper bridge arm circuit and the lower bridge arm circuit each comprise two semiconductor chips in parallel, so that the consistency of the at least three semiconductor chip groups is good, which is conducive to reducing the parasitic parameters of the power semiconductor device and improving the current sharing property of the power semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0017] Figure 1 is a structural schematic diagram of a first embodiment of the power semiconductor device provided by the present application;

[0018] Figure 2 is Figure 1 is a structural schematic diagram of the power semiconductor device from a top view;

[0019] Figure 3 is a circuit topology diagram of an embodiment of the power semiconductor device provided by the present application;

[0020] Figure 4 is a structural schematic diagram of a second embodiment of the power semiconductor device provided by the present application;

[0021] Figure 5 is Figure 4 is a structural schematic diagram of the power semiconductor device from a top view;

[0022] Figure 6 is a structural schematic diagram of a third embodiment of the power semiconductor device provided by the present application;

[0023] Figure 7 is a structural schematic diagram of a fourth embodiment of the power semiconductor device provided in the present application.

[0024] In the figure, 10 is a copper clad ceramic substrate; 11 is a first drive gate copper foil; 12 is a first gate resistance copper foil; 13 is a first auxiliary source copper foil; 20 is a semiconductor chip set; 21 is an upper bridge arm circuit; 211 is a first transistor; 211a is a first first transistor; 211b is a second first transistor; 212 is a first drive terminal; 213 is a second drive terminal; 214 is a first drive resistance; 214a is a first first drive resistance; 214b is a second first drive resistance; 22 is a lower bridge arm circuit; 221 is a second transistor; 221a is a first second transistor; 221b is a second second transistor; 222 is a third drive terminal; 223 is a fourth drive terminal; 224 is a second drive resistance; 224a is a first second drive resistance; 224b is a second second drive resistance; 23 is a first connection terminal; 25 is a second connection terminal; 24 is a third connection terminal; 26 is a negative temperature coefficient thermistor; 30 is an outer shell; 31 is a protective layer; 32 is a protrusion. DETAILED DESCRIPTION

[0025] The present application will be further described by way of illustration with reference to the following figures and examples. It is specifically intended that the following examples are only to be illustrative of the application, and not to limit the scope of the application. Similarly, it is to be specifically understood that the following examples are only a portion of the embodiments of the application, and all other embodiments obtained by those of ordinary skill in the art without any creative work, fall within the scope of the present application.

[0026] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase that the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of other embodiments. It is explicitly understood that the embodiments described herein are combinable.

[0027] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "setting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be connected through an intermediate medium. For those skilled in the art, if the present application has any directional indication (such as up, down, left, right, front, back, etc.), the directional indication is only used to explain the relative position relationship, movement condition, etc. between the components in a certain posture (as shown in the drawings), if the certain posture changes, the directional indication will also change accordingly.

[0028] Please refer to Figures 1-3 , Figure 1 is a structural schematic diagram of a first embodiment of a power semiconductor device provided by the present application, Figure 2 is Figure 1 a structural schematic diagram of a power semiconductor device in a top view, Figure 3 is a circuit topology diagram of an embodiment of a power semiconductor device provided by the present application. As Figures 1-3 shown, in the present embodiment, the power semiconductor device includes a copper-clad ceramic substrate 10 (Direct Bond Copper, DBC) and at least three semiconductor chip sets 20.

[0029] The copper-clad ceramic substrate 10 is a substrate formed by directly bonding a copper metal layer to a ceramic substrate, and is used to carry the at least three semiconductor chip sets 20 and to help the semiconductor chip sets 20 dissipate heat and withstand various mechanical stresses during operation of the semiconductor chip sets 20, so as to provide a stable working environment for the semiconductor chip sets 20 and ensure the performance and reliability of the semiconductor chip sets 20.

[0030] The at least three semiconductor chip sets 20 are electrically connected to the copper-clad ceramic substrate 10 by bonding wires, and the at least three semiconductor chip sets 20 are arranged in sequence along a first direction; the semiconductor chip set 20 includes an upper bridge arm circuit 21, a lower bridge arm circuit 22 and a first connection terminal 23, the upper bridge arm circuit 21 and the lower bridge arm circuit 22 are arranged in sequence along a second direction, and the second direction is perpendicular to the first direction; the upper bridge arm circuit 21 includes two semiconductor chips in parallel, and the lower bridge arm circuit 22 includes two semiconductor chips in parallel, and the semiconductor chips of the upper bridge arm circuit 21 and the lower bridge arm circuit 22 are connected to the first connection terminal 23.

[0031] Specifically, the semiconductor chip set 20 controls the on-off of current through the switching of multiple semiconductor chips to realize the functions of power conversion, motor control, zero-voltage switching, or zero-voltage zero-current switching. The first direction is the length direction of the copper-clad ceramic substrate 10, and the second direction is the width direction of the copper-clad ceramic substrate 10. At least three semiconductor chip sets 20 are arranged in sequence along the first direction, and the upper bridge arm circuit 21 and the lower bridge arm circuit 22 of each semiconductor chip set 20 are arranged in sequence along the second direction, so that the structural consistency of the at least three semiconductor chip sets 20 is good, and each semiconductor chip set 20 includes two semiconductor chips in parallel, which can effectively improve the current-carrying capacity of each semiconductor chip set 20.

[0032] In a possible implementation, the copper-clad ceramic substrate 10 includes a first metal layer, a ceramic substrate layer, and a second metal layer, the ceramic substrate layer is located between the first metal layer and the second metal layer, the first metal layer on the upper layer is etched to form multiple independent conductor layers, and the first metal layer is used to form a circuit topology with semiconductor chips, bonding wires, connection terminals, and the like. The ceramic substrate layer in the middle layer is used to play the roles of insulation and heat conduction. The second metal layer on the lower layer is generally connected with a heat sink through a thermal interface material to play the role of heat conduction.

[0033] Further, the copper foils on the first metal layer are soldered with multiple terminals to realize the connection of multiple semiconductor chips with the copper-clad ceramic substrate 10. The gaps of the multiple copper foils on the first metal layer are close to the minimum electrical clearance, so as to reduce the parasitic inductance of the semiconductor chip set 20 and improve the current consistency of the semiconductor chip set 20. The copper foils on the first metal layer can be designed in a concave-convex shape to facilitate soldering, and the transition regions of the concave-convex shape are all rounded to reduce stress concentration in the soldering process. The copper foils on the first metal layer can be provided with a solder resist layer to prevent solder overflow when soldering semiconductor chips and other components on the copper foils, and to reduce or prevent the problem of electrical short circuit during use. The distance between the outermost copper foil of the first metal layer and the edge of the ceramic substrate layer can be but is not limited to 2.2 mm, the distance between the outermost copper foil of the second metal layer and the edge of the ceramic substrate layer can be but is not limited to 0.55 mm, and the minimum distance between the copper foils on the first metal layer and the second metal layer can be but is not limited to 0.6 mm, so as to improve the insulation performance and voltage withstand performance of the copper-clad ceramic substrate 10. The ceramic substrate layer includes but is not limited to a silicon nitride ceramic layer, which has a lighter density and a longer service life compared with other ceramic layers; and when the silicon nitride ceramic layer is used as the substrate layer, the chips can be soldered through an advanced silver sintering process to increase the heat dissipation of the overall module through excellent thermal conductivity, further reduce the thermal resistance, and improve the performance of the power semiconductor device.

[0034] In the embodiment of the present application, the power semiconductor device comprises a copper-clad ceramic substrate 10 and at least three semiconductor chip groups 20, the at least three semiconductor chip groups 20 are electrically connected to the copper-clad ceramic substrate 10 through bonding wires respectively, and the at least three semiconductor chip groups 20 are arranged in sequence along a first direction; wherein the semiconductor chip group 20 comprises an upper bridge arm circuit 21, a lower bridge arm circuit 22 and a first connection terminal 23, the upper bridge arm circuit 21 and the lower bridge arm circuit 22 are arranged in sequence along a second direction, and the second direction is perpendicular to the first direction; the upper bridge arm circuit 21 comprises two semiconductor chips in parallel, the lower bridge arm circuit 22 comprises two semiconductor chips in parallel, and the semiconductor chips of the upper bridge arm circuit 21 and the lower bridge arm circuit 22 are connected to the first connection terminal 23 respectively. In the foregoing manner, the at least three semiconductor chip groups 20 of the power semiconductor device each comprise the upper bridge arm circuit 21 and the lower bridge arm circuit 22, and the upper bridge arm circuit 21 and the lower bridge arm circuit 22 each comprise two semiconductor chips in parallel, so that the consistency of the at least three semiconductor chip groups 20 is good, which is conducive to reducing the parasitic parameters of the power semiconductor device and improving the current sharing property of the power semiconductor device.

[0035] In an embodiment, the semiconductor chip group 20 further comprises a second connection terminal 25 and a third connection terminal 24, the first connection terminal 23, the second connection terminal 25 and the third connection terminal 24 surround the semiconductor chips of the upper bridge arm circuit 21 and the lower bridge arm circuit 22, the first end of the semiconductor chips of the upper bridge arm circuit 21 is connected to the second connection terminal 25, the second end of the semiconductor chips of the upper bridge arm circuit 21 is connected to the first connection terminal 23, the first end of the semiconductor chips of the lower bridge arm circuit 22 is connected to the first connection terminal 23, and the second end of the semiconductor chips of the lower bridge arm circuit 22 is connected to the third connection terminal 24.

[0036] Specifically, the two semiconductor chips of the upper bridge arm circuit 21 are arranged along the first direction, and the two semiconductor chips of the lower bridge arm circuit 22 are arranged along the first direction, so that the four semiconductor chips of each semiconductor chip group 20 are arranged in a square matrix. The first connection terminal 23, the second connection terminal 25 and the third connection terminal 24 are arranged around the four semiconductor chips; the first connection terminal 23, the second connection terminal 25 and the third connection terminal 24 can be arranged on different sides of the four semiconductor chips respectively. For example, the first connection terminal 23 can be located below the four semiconductor chips, the second connection terminal 25 can be located above the four semiconductor chips, and the third connection terminal 24 can be located on the left side or the right side of the four semiconductor chips. In the foregoing manner, the layout of the connection terminals and the semiconductor chips of the semiconductor chip group 20 in the embodiment is compact, which is conducive to the circuit design and wiring arrangement of the semiconductor chip group 20, can improve the space utilization of the semiconductor chip group 20 under the condition of ensuring the safe creepage distance, and is conducive to the miniaturization design of the semiconductor chip group 20.

[0037] The first end of the semiconductor chip of the upper bridge arm circuit 21 is connected with the second connection terminal 25, the second end of the semiconductor chip of the upper bridge arm circuit 21 is connected with the first connection terminal 23, the first end of the semiconductor chip of the lower bridge arm circuit 22 is connected with the first connection terminal 23, and the second end of the semiconductor chip of the lower bridge arm circuit 22 is connected with the third connection terminal 24. In this way, the semiconductor chip of the upper bridge arm circuit 21 and the semiconductor chip of the lower bridge arm circuit 22 can be connected with external circuits through the connection terminals, so that the semiconductor chip set 20 can realize the functions of power conversion, motor control, zero-voltage switching or zero-voltage zero-current switching, etc.

[0038] Optionally, the first connection terminal 23 is an AC connection terminal, the third connection terminal 24 is a DC- connection terminal, and the second connection terminal 25 is a DC+ connection terminal.

[0039] Specifically, the first connection terminal 23 is an AC connection terminal, and the semiconductor chips of the upper bridge arm circuit 21 and the lower bridge arm circuit 22 are respectively connected with external AC power sources through the AC connection terminal to input AC power to the semiconductor chip set 20. The third connection terminal 24 is a DC- connection terminal, which is a negative connection terminal of a DC terminal, and the semiconductor chip of the lower bridge arm circuit 22 is connected with external circuits through the DC- connection terminal. The second connection terminal 25 is a DC+ connection terminal, which is a positive connection terminal of a DC terminal, and the semiconductor chip of the upper bridge arm circuit 21 is connected with external circuits through the DC+ connection terminal. The DC+ connection terminal and the DC- connection terminal can form two ends of a DC bus, so that the semiconductor chip set 20 can be connected with external motors or other loads through the connection of the upper bridge arm circuit 21 and the DC+ connection terminal and the connection of the lower bridge arm circuit 22 and the DC- connection terminal, thereby ensuring the normal operation of the semiconductor chip set 20.

[0040] Further, at least three semiconductor chip sets 20 can be commonly connected to the first connection terminal 23, the third connection terminal 24 and the second connection terminal 25. The first connection terminal 23, the third connection terminal 24 and the second connection terminal 25 can be further divided into a plurality of wiring terminals corresponding to the semiconductor chip sets 20, and the plurality of wiring terminals of the first connection terminal 23, the third connection terminal 24 and the second connection terminal 25 can be arranged close to each other at the same position or arranged at different positions. The terminal surface can be provided with a nickel plating layer and a gold plating layer to resist moisture, mold and salt spray and enhance the service life. The number and diameter of the terminals are determined according to the current carrying capacity of each circuit design, which is not specifically limited here.

[0041] Further, the upper bridge arm circuit 21 includes two first transistors 211 connected in parallel, a first driving terminal 212, and a second driving terminal 213. The drain of the first transistor 211 is connected to the second connection terminal 25, the gate of the first transistor 211 is connected to the first driving terminal 212, the auxiliary source of the first transistor 211 is connected to the second driving terminal 213, and the power source of the first transistor 211 is connected to the first connection terminal 23.

[0042] Specifically, the semiconductor chip of the upper bridge arm circuit 21 is the first transistor 211, which can be but is not limited to a metal-oxide-semiconductor field effect transistor. The two first transistors 211 of the upper bridge arm circuit 21 are connected in parallel, and the first transistor 211 includes an auxiliary source, a power source, a drain, and a gate. The gate of the first transistor 211 is used to control the input signal, the power source is used to control the output signal, and the first transistor 211 controls the flow of current by applying a voltage between the gate and the power source. The drain of the first transistor 211 is opposite to the power source, the drain is the end point of the current outflow, and the power source is the starting point of the current. The change of the gate voltage can control the formation and disconnection of the conduction channel between the drain and the power source, thereby realizing the control of the current.

[0043] In this embodiment, the drain of the first transistor 211 is connected to the second connection terminal 25, the gate of the first transistor 211 is connected to the first driving terminal 212, the auxiliary source of the first transistor 211 is connected to the second driving terminal 213, and the power source of the first transistor 211 is connected to the first connection terminal 23. Therefore, the first transistor 211 can be connected to the second driving terminal 213 through the auxiliary source to reduce the switching loss of the semiconductor chip set 20 and reduce the parasitic inductance from the auxiliary source to the internal chip. By connecting the gate to the first driving terminal 212, when a positive voltage is applied to the gate through the first driving terminal 212, the first transistor 211 is in an open state, a conduction channel is formed, and the current is allowed to flow from the drain to the power source. When a reverse voltage is applied to the gate through the first driving terminal 212, the first transistor 211 is in an off state, the channel is cut off, and the current flows through the body diode, i.e., from the power source to the drain, thereby realizing the function of current control of the first transistor 211.

[0044] In this embodiment, the drain of the first transistor 211 is connected to the second connection terminal 25, the gate of the first transistor 211 is connected to the first driving terminal 212, the auxiliary source of the first transistor 211 is connected to the second driving terminal 213, and the power source of the first transistor 211 is connected to the first connection terminal 23. Therefore, the first transistor 211 can be connected to the second driving terminal 213 through the auxiliary source to reduce the switching loss of the semiconductor chip set 20 and reduce the parasitic inductance from the auxiliary source to the internal chip. By connecting the gate to the first driving terminal 212, when a positive voltage is applied to the gate through the first driving terminal 212, the first transistor 211 is in an open state, a conduction channel is formed, and the current is allowed to flow from the drain to the power source. When a reverse voltage is applied to the gate through the first driving terminal 212, the first transistor 211 is in an off state, the channel is cut off, and the current flows through the body diode, i.e., from the power source to the drain, thereby realizing the function of current control of the first transistor 211.

[0045] Similarly, similar to the upper bridge arm circuit 21, the semiconductor chip of the lower bridge arm circuit 22 is a second transistor 221, which can be but is not limited to a metal-oxide-semiconductor field effect transistor. The second transistor 221 is similar to the first transistor 211, the drain of the second transistor 221 is connected with the first connection terminal 23, the gate of the second transistor 221 is connected with the third driving terminal 222, the auxiliary source of the second transistor 221 is connected with the fourth driving terminal 223, and the power source of the second transistor 221 is connected with the third connection terminal 24, and the specific content will not be repeated.

[0046] The first driving terminal 212 of the upper bridge arm circuit 21 and the third driving terminal 222 of the lower bridge arm circuit 22 are gate driving terminals, and the second driving terminal 213 of the upper bridge arm circuit 21 and the fourth driving terminal 223 of the lower bridge arm circuit 22 are auxiliary source driving terminals. Therefore, the first transistor 211 of the upper bridge arm circuit 21 can control the turn-on and turn-off of the gate through the first driving terminal 212, and the first transistor 211 of the lower bridge arm circuit 22 can control the turn-on and turn-off of the gate through the third driving terminal 222; the second transistor 221 of the upper bridge arm circuit 21 can drive and control the auxiliary source through the second driving terminal 213, and the second transistor 221 of the lower bridge arm circuit 22 can drive and control the auxiliary source through the fourth driving terminal 223, so as to optimize the design of the gate driving.

[0047] In the embodiment of the present application, the structure of the lower bridge arm circuit 22 is similar to that of the upper bridge arm circuit 21, so that the circuits on the upper half and the lower half of each semiconductor chip group 20 are almost the same, further improving the consistency of the at least three semiconductor chip groups 20, which is beneficial to reduce the parasitic parameters of the power semiconductor device and improve the current sharing of the power semiconductor device.

[0048] Among them, the auxiliary source of the first transistor 211 is connected with the second driving terminal 213 through the bonding wire, and the auxiliary source of the second transistor 221 is connected with the fourth driving terminal 223 through the bonding wire, so as to realize Kelvin connection.

[0049] Specifically, the bonding wire for connecting the electrode and the copper clad ceramic substrate 10, the number of the bonding wire is determined according to the bondable area size of the transistor electrode, the thickness of the bonding wire is determined according to the characteristics and use occasions of the transistor electrode, and the material of the bonding wire includes but is not limited to aluminum bonding wire, copper bonding wire and the like, for example, when the conductivity and thermal conductivity of the bonding wire are considered, the copper bonding wire can be selected for connection. Among them, the first transistor 211 and the second transistor 221 of the embodiment realize Kelvin connection through the design of the auxiliary source, so as to separate the current in the power supply line and the current in the gate driving line, reduce the loss of the gate switch, and improve the switching performance of the first transistor 211 and the second transistor 221.

[0050] In an embodiment, as shown in Figure 1 and Figure 2 The first drive gate copper foil 11 is welded on the copper clad ceramic substrate 10, and the upper arm circuit 21 further comprises a first drive resistor 214, which is arranged on one side of the first drive gate copper foil 11, and the gate of the first transistor 211 is connected to the first drive gate copper foil 11 through a bonding wire and the first drive resistor 214, so as to be connected to the first drive terminal 212 through the first drive gate copper foil 11.

[0051] Specifically, the connection mode of the gate of the second transistor 221 and the third drive terminal 222 is similar to that of the first transistor 211, and the copper clad ceramic substrate 10 further comprises a second drive gate copper foil, which is welded on the side of the copper clad ceramic substrate 10 away from the first drive gate copper foil 11, and the lower arm circuit 22 further comprises a second drive resistor 224, which is arranged on one side of the second drive gate copper foil, and the gate of the second transistor 221 is connected to the second drive gate copper foil through a bonding wire and the second drive resistor 224, so as to be connected to the third drive terminal 222 through the second drive gate copper foil.

[0052] In the above manner, the gate of the first transistor 211 is connected to the first drive resistor 214, and the gate of the second transistor 221 is connected to the second drive resistor 224, so that the gate current can be limited by the first drive resistor 214 and the second drive resistor 224, the instantaneous change of the gate voltage is reduced, and the oscillation of the gate voltage is eliminated, thereby improving the stability and reliability of the upper arm circuit 21 and the lower arm circuit 22.

[0053] In the above manner, the gate of the first transistor 211 is connected to the first drive resistor 214, and the gate of the second transistor 221 is connected to the second drive resistor 224, so that the gate current can be limited by the first drive resistor 214 and the second drive resistor 224, the instantaneous change of the gate voltage is reduced, and the oscillation of the gate voltage is eliminated, thereby improving the stability and reliability of the upper arm circuit 21 and the lower arm circuit 22.

[0054] Specifically, the auxiliary source electrode of the first transistor 211 is connected with the first auxiliary source electrode copper foil 13 through a bonding wire, so as to be connected with the second driving terminal 213 through the first auxiliary source electrode copper foil 13, thereby realizing the connection between the auxiliary source electrode of the first transistor 211 and the external circuit. The gate electrode of the first transistor 211 is connected with the first driving gate electrode copper foil 11 through a bonding wire and the first driving resistance 214, so as to be connected with the first driving terminal 212 through the first driving gate electrode copper foil 11, thereby realizing the connection between the gate electrode of the first transistor 211 and the external circuit. Further, the auxiliary source electrode of the second transistor 221 is connected with the fourth driving terminal 223 in a similar manner to the first transistor 211. For example, the copper clad ceramic substrate 10 further comprises a second gate resistance copper foil and a second auxiliary source electrode copper foil to realize the connection of the second transistor 221, which will not be described herein.

[0055] In the above manner, in the power semiconductor device, the first gate resistance copper foil 12 is located between the first auxiliary source electrode copper foil 13 and the first driving gate electrode copper foil 11, and the first driving gate electrode copper foil 11, the first gate resistance copper foil 12 and the first auxiliary source electrode copper foil 13 are arranged in sequence along the first direction. The layout is compact, which is convenient for the loop design and wiring arrangement of the first transistor 211, can improve the space utilization of the upper bridge arm circuit 21 under the condition of ensuring the safe creepage distance, and is conducive to the miniaturization design of the upper bridge arm circuit 21.

[0056] In another embodiment, please refer to Figure 4 and Figure 5 , Figure 4 is a structural schematic diagram of a second embodiment of the power semiconductor device provided by the present application, Figure 5 is Figure 4 is a structural schematic diagram of the power semiconductor device in the top view. As shown in Figure 4 and Figure 5 , in the power semiconductor device of the present embodiment, the gate electrode of the first transistor 211 is directly connected with the first driving gate electrode copper foil 11 through a bonding wire, and the gate electrode of the second transistor 221 is directly connected with the second driving gate electrode copper foil through a bonding wire, which reduces the welding of the driving resistance, can further reduce the packaging cost of the power semiconductor device, and simplifies the welding jig.

[0057] Optionally, the copper clad ceramic substrate 10 comprises a first driving gate electrode copper foil 11 and a first auxiliary source electrode copper foil 13, the first driving gate electrode copper foil 11 and the first auxiliary source electrode copper foil 13 are arranged in sequence along the second direction, the gate electrode of the first transistor 211 is connected with the first driving gate electrode copper foil 11 through a bonding wire, so as to be connected with the first driving terminal 212 through the first driving gate electrode copper foil 11; the auxiliary source electrode of the first transistor 211 is connected with the first auxiliary source electrode copper foil 13 through a bonding wire, so as to be connected with the second driving terminal 213 through the first auxiliary source electrode copper foil 13.

[0058] Specifically, the copper clad ceramic substrate 10 further comprises a second driving gate copper foil and a second auxiliary source copper foil, the gate of the second transistor 221 is directly connected with the second driving gate copper foil through a bonding wire, and the auxiliary source of the second transistor 221 is connected with the second auxiliary source copper foil in a similar manner as the first transistor 211, which will not be described here.

[0059] In the above manner, the gate of the first transistor 211 is directly connected with the first driving gate copper foil 11 through a bonding wire, without the need of welding the first driving resistor 214, which can further reduce the packaging cost of the power semiconductor device, simplify the welding tool, and make the power semiconductor device applicable to scenarios that only require gate voltage driving.

[0060] Further, referring to Figure 6 , Figure 6 is a structural schematic diagram of a third embodiment of the power semiconductor device provided by the present application. The first semiconductor chip set 20, the second semiconductor chip set 20 and the third semiconductor chip set 20 of the at least three semiconductor chip sets 20 are arranged in sequence along the first direction, and the first semiconductor chip set 20 is located on the left side of the copper clad ceramic substrate 10, and the third semiconductor chip set 20 is located on the right side of the copper clad ceramic substrate 10.

[0061] In an embodiment, as shown in Figure 4 , the three semiconductor chip sets 20 correspond to three first connection terminals 23 respectively, the positions of the three first connection terminals 23 are located between the first semiconductor chip set 20 and the second semiconductor chip set 20, and the three first connection terminals 23 are arranged in a triangular array. In another embodiment, as shown in Figure 6 , the three first connection terminals 23 are arranged in sequence along the second direction. The above manner adjusts the arrangement of the first connection terminals 23, which can make the power semiconductor device of the present embodiment convenient to design the layout of the corresponding PCB according to the application, and improve the rationality of the layout design when applied to various electronic device scenarios.

[0062] Among them, the power semiconductor device can also be provided with a negative temperature coefficient thermistor 26 (Negative Temperature Coefficient Thermistor, NTC) for monitoring the health status of the semiconductor chip set 20 during operation. Specifically, in an embodiment, as shown in Figure 1 and Figure 4 , the negative temperature coefficient thermistor 26 can be arranged at the lower right corner of the copper clad ceramic substrate 10, and the negative temperature coefficient thermistor 26 is located below the third semiconductor chip set 20; as Figure 6As shown, the negative temperature coefficient thermistor 26 of the embodiment can be arranged between the first semiconductor chip set 20 and the second semiconductor chip set 20, and specifically between the second driving terminal 213 and the third driving terminal 222 of the two semiconductor chip sets 20.

[0063] In the above manner, the power semiconductor device of the embodiment adjusts the positions of the terminals of the main current loop and the driving loop to ensure a safe creepage distance and improve the integration of the semiconductor chip set 20 on the copper clad ceramic substrate 10.

[0064] In an embodiment, the semiconductor chip is at least one of a field effect transistor, a bipolar transistor, a diode, and a gallium nitride chip.

[0065] Specifically, the semiconductor chip of the semiconductor chip set 20 of the embodiment can be, but is not limited to, a field effect transistor (MOSFET), a bipolar transistor (IGBT), a diode, and a gallium nitride chip (GAN), and the semiconductor chip of the semiconductor chip set 20 can also be a combination of at least one of the above chips. Therefore, the circuit module of the power semiconductor device of the embodiment is compatible with MOSFET, IGBT, diode, GAN, and other semiconductor chips, has strong compatibility, and can be applied to various application scenarios.

[0066] Further, the upper bridge arm circuit 21 in the above embodiment includes two parallel first transistors 211, and corresponding to this, the first driving resistors 214 connected to the first transistors 211 each have two corresponding ones. The lower bridge arm circuit 22 includes two parallel second transistors 221, and corresponding to this, the second driving resistors 224 connected to the second transistors 221 each have two corresponding ones. Exemplarily, as shown in Figure 2 As shown, the two first transistors 211 of the upper bridge arm circuit 21 can include a first first transistor 211a and a second first transistor 211b, the gate of the first first transistor 211a is connected to the first first driving resistor 214a, and the gate of the second first transistor 211b is connected to the second first driving resistor 214b. The two second transistors 221 of the lower bridge arm circuit 22 can include a first second transistor 221a and a second second transistor 221b, the gate of the first second transistor 221a is connected to the first second driving resistor 224a, and the gate of the second second transistor 221b is connected to the second second driving resistor 224b.

[0067] In an embodiment, please refer to Figure 7 , Figure 7 is a structural schematic diagram of a fourth embodiment of the power semiconductor device provided by the present application. As shown in Figure 7As shown, the power semiconductor device further comprises a housing 30, which is bonded at the bottom to the ceramic substrate layer of the copper clad ceramic substrate 10. Inside the housing 30, there is a protective layer 31 for protecting the components of the chip set from external pollution. The protective layer 31 includes but is not limited to an epoxy layer. On the top of the housing 30, there is a protective protrusion 32, which is used for facilitating the connection and positioning of the external PCB. The housing 30 and the copper clad ceramic substrate 10 are fastened by dispensing.

[0068] The housing 30 includes but is not limited to a semi-crystalline thermoplastic housing 30, which is composed of polybutylene terephthalate (PBT) to ensure the plastic deformation resistance, thermal deformation resistance and electrical insulation of the housing 30. The height of the housing 30 can be designed to include an epoxy potting adhesive, which is used to protect the internal chips, DBC substrate and bonding wires from external environmental pollution, and further increase the internal insulation strength.

[0069] The above is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A power semiconductor device, characterized by, include: Copper-clad ceramic substrate; At least three semiconductor chip groups are electrically connected to the copper-clad ceramic substrate via bonding wires, and the at least three semiconductor chip groups are arranged sequentially along a first direction; The semiconductor chipset includes an upper bridge arm circuit, a lower bridge arm circuit, and a first connection terminal. The upper bridge arm circuit and the lower bridge arm circuit are arranged sequentially along a second direction, which is perpendicular to the first direction. The upper bridge arm circuit includes two semiconductor chips connected in parallel, and the lower bridge arm circuit includes two semiconductor chips connected in parallel. The semiconductor chips of the upper bridge arm circuit and the lower bridge arm circuit are respectively connected to the first connection terminal.

2. The power semiconductor device according to claim 1, characterized in that, The semiconductor chipset further includes a second connection terminal and a third connection terminal. The first connection terminal, the second connection terminal, and the third connection terminal surround the semiconductor chips of the upper bridge arm circuit and the lower bridge arm circuit. A first end of the semiconductor chip of the upper bridge arm circuit is connected to the second connection terminal, a second end of the semiconductor chip of the upper bridge arm circuit is connected to the first connection terminal, a first end of the semiconductor chip of the lower bridge arm circuit is connected to the first connection terminal, and a second end of the semiconductor chip of the lower bridge arm circuit is connected to the third connection terminal.

3. The power semiconductor device according to claim 2, characterized in that The first connection terminal is an AC connection terminal, the second connection terminal is a DC- connection terminal, and the third connection terminal is a DC+ connection terminal.

4. The power semiconductor device according to claim 3, characterized in that The upper bridge arm circuit includes two parallel first transistors, a first driving terminal, and a second driving terminal. The drain of the first transistor is connected to the second connection terminal, the gate of the first transistor is connected to the first driving terminal, the auxiliary source of the first transistor is connected to the second driving terminal, and the power source of the first transistor is connected to the first connection terminal.

5. The power semiconductor device according to claim 4, characterized in that, The lower bridge arm circuit includes two parallel second transistors, a third driving terminal, and a fourth driving terminal. The second transistors are connected in parallel, with the drain of the second transistor connected to the first connection terminal, the gate of the second transistor connected to the third driving terminal, the auxiliary source of the second transistor connected to the fourth driving terminal, and the power source of the second transistor connected to the third connection terminal.

6. The power semiconductor device according to claim 5, characterized in that The auxiliary source of the first transistor is connected to the second driving terminal via the bonding wire, and the auxiliary source of the second transistor is connected to the fourth driving terminal via the bonding wire to achieve a Kelvin connection.

7. The power semiconductor device according to claim 4, characterized in that, A first driving gate copper foil is soldered onto the copper-clad ceramic substrate. The upper bridge arm circuit also includes a first driving resistor, which is disposed on one side of the first driving gate copper foil. The gate of the first transistor is connected to the first driving gate copper foil through the bonding wire and the first driving resistor, so as to be connected to the first driving terminal through the first driving gate copper foil.

8. The power semiconductor device according to claim 7, characterized in that The copper-clad ceramic substrate further comprises a first gate resistance copper foil and a first auxiliary source copper foil, the first gate resistance copper foil is located between the first auxiliary source copper foil and the first driving gate copper foil, and the first driving gate copper foil, the first gate resistance copper foil and the first auxiliary source copper foil are arranged in sequence along the first direction, the first driving resistance is arranged on the first gate resistance copper foil, and the auxiliary source of the first transistor is connected with the first auxiliary source copper foil through the bonding wire to be connected with the second driving terminal through the first auxiliary source copper foil.

9. The power semiconductor device according to claim 4, characterized in that, The copper-clad ceramic substrate comprises a first driving gate copper foil and a first auxiliary source copper foil, the first driving gate copper foil and the first auxiliary source copper foil are arranged in sequence along the second direction, the gate of the first transistor is connected with the first driving gate copper foil through the bonding wire to be connected with the first driving terminal through the first driving gate copper foil, and the auxiliary source of the first transistor is connected with the first auxiliary source copper foil through the bonding wire to be connected with the second driving terminal through the first auxiliary source copper foil.

10. The power semiconductor device according to claim 1, characterized in that, The semiconductor chip is at least one of a field effect transistor, a bipolar transistor, a diode and a gallium nitride chip.

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