Staggered parallel Boost-FPC (Flexible Printed Circuit) circuit of vehicle-mounted charger

Abstract

The utility model provides an interleaved Boost-FPC circuit of a vehicle-mounted charger. The interleaved Boost-FPC circuit comprises a rectifier bridge, a first Boost converter, a second Boost converter, an output capacitor Co and a control circuit, the first Boost converter comprises an inductor L1, a diode D1 and an NMOS (N-channel Metal Oxide Semiconductor) power tube S1; the second Boost converter comprises an inductor L2, a diode D2 and an NMOS (N-channel Metal Oxide Semiconductor) power tube S2; the control circuit comprises a first subtracter, a voltage gain amplifier, a first multiplier, a second subtracter, a current gain amplifier and a peak current controller; according to the utility model, the plurality of interleaved control Boost converters are connected in parallel, so that high-power output is effectively realized, and the current ripple amplitude of an input power supply is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of circuits in vehicle charger, especially a kind of vehicle charger staggered parallel Boost-FPC circuit. BACKGROUND

[0002] With the rapid development of power electronics, power electronic load in power grid system increases sharply, harmonic pollution is increasingly serious, power factor correction (PFC) circuit is an effective method to improve power supply quality, Boost circuit is widely used due to its simple topology structure, high efficiency, easy to control and other characteristics. SUMMARY

[0003] In view of the deficiencies in the prior art, the utility model embodiment provides a kind of vehicle charger staggered parallel Boost-FPC circuit, by the parallel connection of multiple staggered control Boost converter, effectively realize high-power output, and reduce the current ripple amplitude of input power supply.To achieve the above technical purpose, the technical scheme adopted by the utility model embodiment is:

[0004] The utility model embodiment provides a kind of vehicle charger staggered parallel Boost-FPC circuit, including rectifier bridge, first Boost converter, second Boost converter, output capacitor Co, control circuit;

[0005] The first Boost converter includes inductance L1, diode D1 and NMOS power tube S1;

[0006] The second Boost converter includes inductance L2, diode D2 and NMOS power tube S2;

[0007] The control circuit includes first subtracter, voltage gain amplifier, first multiplier, second subtracter, current gain amplifier, peak current controller;

[0008] Two input ends of the rectifier bridge are used to be connected to input power Vin respectively;The positive output end of rectifier bridge is connected to one end of inductance L1 and one end of inductance L2, the other end of inductance L1 is connected to the drain of NMOS power tube S1 and the anode of diode D1, the other end of inductance L2 is connected to the drain of NMOS power tube S2 and the anode of diode D2, the cathode of diode D1 and the cathode of diode D2 are connected to one end of output capacitor Co, and are used to connect one end of load RL;The negative output end of the rectifier bridge is connected to the source of NMOS power tube S1, the source of NMOS power tube S2 and the other end of output capacitor Co, and is used to connect the other end of load RL;

[0009] One end of the first multiplier is connected with an input voltage sampling signal Vs(t) obtained from a positive output end of a rectifier bridge; a negative input end of the first subtractor is connected with an output voltage signal Vo obtained from one end of an output capacitor Co, a positive input end of the first subtractor is connected with a reference voltage Vref, an output end of the first subtractor is connected with an input of a voltage gain amplifier, an output end of the voltage gain amplifier is connected with the other end of the first multiplier; an output end of the first multiplier is connected with a positive input end of a second subtractor, a negative input end of the second subtractor is connected with an input current sampling signal Is(t) obtained from a negative output end of the rectifier bridge, an output end of the second subtractor is connected with a current gain amplifier, an output end of the current gain amplifier is connected with a peak current controller and sends a peak current control signal Ic(t) to the peak current controller, current signal sampling signals obtained from drains of NMOS power tubes S1 and S2 are connected with the peak current controller; two output ends of the peak current controller output a first PWM control signal d1(t) and a second PWM control signal d2(t) respectively, the first PWM control signal d1(t) and the second PWM control signal d2(t) are connected with gates of the NMOS power tubes S1 and S2 respectively.

[0010] Further, the first PWM control signal d1(t) and the second PWM control signal d2(t) have a phase difference of 180 degrees.

[0011] Further, the inductor L1 is 200-400 mu H.

[0012] Further, the inductor L2 is 200-400 mu H.

[0013] Further, the output capacitor Co is 200-1000 mu F.

[0014] The technical scheme provided by the embodiment of the utility model has the advantages that the interleaved parallel Boost-FPC circuit has strong advantages in high-power power supply, multiple interleaved control Boost converters are connected in parallel, high-power output is effectively realized, current unevenness caused by direct parallel connection of switching tubes (NMOS power tubes in the application) is avoided, power device stress can be reduced, input power current ripple amplitude can be reduced, inductance volume can be reduced and power grade can be improved, switching loss can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 The interleaved parallel Boost-FPC circuit schematic diagram in the embodiment of the utility model. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical scheme and advantages of the utility model clearer and more apparent, the utility model will be further described in detail below in combination with the drawings and examples. It should be understood that the specific examples described herein are only used to explain the utility model and are not used to limit the utility model.

[0017] As shown in Figure 1 The utility model discloses vehicle charger staggered parallel Boost-FPC circuit, including rectifier bridge, first Boost converter, second Boost converter, output capacitor Co, control circuit;

[0018] The first Boost converter includes inductance L1, diode D1 and NMOS power tube S1;

[0019] The second Boost converter includes inductance L2, diode D2 and NMOS power tube S2;

[0020] The control circuit includes first subtracter 10, voltage gain amplifier 20, first multiplier 30, second subtracter 40, current gain amplifier 50, peak current controller 60;

[0021] The two input ends of rectifier bridge are used to respectively connect input power Vin;Input power Vin can be the power supply of power grid;The positive output end of rectifier bridge connects one end of inductance L1 and one end of inductance L2, the other end of inductance L1 connects the drain of NMOS power tube S1 and the anode of diode D1, the other end of inductance L2 connects the drain of NMOS power tube S2 and the anode of diode D2, the cathode of diode D1 and the cathode of diode D2 connect one end of output capacitor Co, and are used to connect one end of load RL;The negative output end of rectifier bridge connects the source of NMOS power tube S1, the source of NMOS power tube S2 and the other end of output capacitor Co, and is used to connect the other end of load RL;

[0022] One end of the first multiplier 30 is connected to the input voltage sampling signal Vs(t) obtained from the positive output terminal of the rectifier bridge; the negative input terminal of the first subtractor 10 is connected to the output voltage signal Vo obtained from one end of the output capacitor Co, the positive input terminal of the first subtractor 10 is connected to the reference voltage Vref, the output terminal of the first subtractor 10 is connected to the input terminal of the voltage gain amplifier 20, the output terminal of the voltage gain amplifier 20 is connected to the other end of the first multiplier 30; the output terminal of the first multiplier 30 is connected to the positive input terminal of the second subtractor 40, the negative input terminal of the second subtractor 40 is connected to the input current sampling signal Is(t) obtained from the negative output terminal of the rectifier bridge, the output terminal of the second subtractor 40 is connected to the current gain amplifier 50, the output terminal of the current gain amplifier 50 is connected to the peak current controller 60 and sends the peak current control signal Ic(t) to the peak current controller 60, the current signal sampling signal obtained from the drain of the NMOS power tube S1 and the drain of the NMOS power tube S2 is connected to the peak current controller 60; the two output terminals of the peak current controller 60 output the first PWM control signal d1(t) and the second PWM control signal d2(t) respectively, the first PWM control signal d1(t) and the second PWM control signal d2(t) are connected to the gate of the NMOS power tube S1 and the gate of the NMOS power tube S2 respectively.

[0023] In the embodiment, the control circuit adopts double-loop control, the voltage outer loop focuses on the feedback regulation of the output voltage; the current inner loop controls the tracking of the input current and the change of the input voltage, and realizes the waveform correction of the input current; the input current sampling signal Is(t) is also a voltage signal in form, that is, a voltage signal converted from the input current.

[0024] The vehicle charger interleaved parallel Boost-FPC circuit includes the following four working states:

[0025] (1) State I, the NMOS power tubes S1 and S2 are turned on at the same time, the inductors L1 and L2 are both rising, and the output capacitor Co releases energy;

[0026] (2) State II, the NMOS power tube S1 is turned off and the NMOS power tube S2 is turned on, the inductor L1 current decreases and the inductor L2 current increases;

[0027] (3) State III, the NMOS power tube S1 is turned on and the NMOS power tube S2 is turned off, the inductor L1 current increases and the inductor L2 current decreases;

[0028] (4) State IV, the NMOS power tubes S1 and S2 are both turned off, at this time the inductors L1 and L2 currents are both reduced, and the output capacitor Co stores energy.

[0029] Due to the two staggered control Boost converters in parallel, the peak current of single Boost converter can be reduced by about half, thereby reducing the current ripple amplitude of input power Vin.

[0030] Further, the first PWM control signal d1(t) and the second PWM control signal d2(t) are 180 degrees out of phase.

[0031] Further, the inductance L1 is 200-400μH.

[0032] Further, the inductance L2 is 200-400μH.

[0033] In a specific embodiment, the inductance L1 and the inductance L2 are both 330μH.

[0034] Further, the output capacitance Co is 200-1000μF.

[0035] In a specific embodiment, the output capacitance Co is 680μF.

[0036] The rectifier bridge adopts the conventional connection method in the prior art, including four diodes D3, D4, D5 and D6; the four diodes D3, D4, D5 and D6 are connected in a bridge rectifier form.

[0037] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present application and are not limiting. Although the present application has been described in detail with reference to the embodiments, it should be understood by those skilled in the art that the technical solutions of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application, and all should be covered in the scope of the claims of the present application.

Claims

1. An interleaved parallel Boost-FPC circuit for an on-board charger, comprising: The rectifier bridge, the first Boost converter, the second Boost converter, the output capacitor Co, and the control circuit are included. The first Boost converter includes an inductor L1, a diode D1, and an NMOS power tube S1. The second Boost converter includes an inductor L2, a diode D2, and an NMOS power tube S2. The control circuit includes a first subtractor (10), a voltage gain amplifier (20), a first multiplier (30), a second subtractor (40), a current gain amplifier (50), and a peak current controller (60). Two input terminals of the rectifier bridge are used to connect input power Vin respectively; the positive output terminal of the rectifier bridge is connected to one end of the inductor L1 and one end of the inductor L2, the other end of the inductor L1 is connected to the drain of the NMOS power tube S1 and the anode of the diode D1, the other end of the inductor L2 is connected to the drain of the NMOS power tube S2 and the anode of the diode D2, the cathode of the diode D1 and the cathode of the diode D2 are connected to one end of the output capacitor Co and are used to connect one end of the load RL; the negative output terminal of the rectifier bridge is connected to the source of the NMOS power tube S1, the source of the NMOS power tube S2, and the other end of the output capacitor Co, and is used to connect the other end of the load RL. One end of the first multiplier (30) is connected to the input voltage sampling signal Vs(t) obtained from the positive output terminal of the rectifier bridge; the negative input terminal of the first subtractor (10) is connected to the output voltage signal Vo obtained from one end of the output capacitor Co, the positive input terminal of the first subtractor (10) is connected to the reference voltage Vref, the output terminal of the first subtractor (10) is connected to the input terminal of the voltage gain amplifier (20), the output terminal of the voltage gain amplifier (20) is connected to the other end of the first multiplier (30); the output terminal of the first multiplier (30) is connected to the positive input terminal of the second subtractor (40), the negative input terminal of the second subtractor (40) is connected to the input current sampling signal Is(t) obtained from the negative output terminal of the rectifier bridge, the output terminal of the second subtractor (40) is connected to the current gain amplifier (50), the output terminal of the current gain amplifier (50) is connected to the peak current controller (60) and sends the peak current control signal Ic(t) to the peak current controller (60), the current signal sampling signal obtained from the drain of the NMOS power tube S1 and the drain of the NMOS power tube S2 is connected to the peak current controller (60); the two output terminals of the peak current controller (60) output the first PWM control signal d1(t) and the second PWM control signal d2(t) respectively, and the first PWM control signal d1(t) and the second PWM control signal d2(t) are connected to the gate of the NMOS power tube S1 and the gate of the NMOS power tube S2 respectively.

2. The vehicle charger interleaved parallel Boost-FPC circuit according to claim 1, wherein The first PWM control signal d1(t) and the second PWM control signal d2(t) have a phase difference of 180 degrees.

3. The vehicle charger interleaved parallel Boost-FPC circuit according to claim 1, wherein The inductance L1 is 200 μH-400 μH.

4. The interleaved parallel Boost-FPC circuit of an on-board charger according to claim 1, wherein, The inductance L2 is 200 μH-400 μH.

5. The interleaved parallel Boost-FPC circuit of an on-board charger according to claim 1, wherein, The output capacitance Co is 200 μF-1000 μF.

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