High-speed push-pull drive output pure hardware circuit

Abstract

The utility model discloses a pure hardware circuit with high-speed push-pull drive output, which realizes level conversion of high-speed PWM (pulse width modulation) signals and amplification of driving current capability through triodes, and constructs an amplification circuit of the level and the driving current of the PWM signals by utilizing different conduction characteristics of NPN (negative-positive-negative) type triodes and PNP (positive-negative-positive) type triodes.

Description

TECHNICAL FIELD

[0001] The utility model relates to a car switch control circuit technical field especially relates to a kind of pure hardware circuit of high-speed push-pull drive output. BACKGROUND

[0002] Car switch has high-speed PWM drive output function, circuit has higher requirement to drive edge and on-off time, traditional method is to use high-speed push-pull drive chip, which is relatively high in cost, especially in the current market needs to compress cost situation. SUMMARY

[0003] The utility model aims at overcoming the shortcomings and deficiencies of prior art, and provides a kind of pure hardware circuit of high-speed push-pull drive output.

[0004] To achieve the above object, the utility model provides the following technical scheme: a kind of pure hardware circuit of high-speed push-pull drive output, including resistance R1, resistance R2, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, triode Q1, triode Q2, triode Q3, triode Q4, capacitor C1 and capacitor C2;

[0005] The collector of the triode Q3 is connected with power supply VCC, the base of the triode Q3 is connected with one end of resistance R6 and capacitor C1, the other end of resistance R6 is connected between the collector of triode Q2 and resistance R5, the other end of resistance R5 is grounded, the emitter of triode Q3 and resistance R7 and the emitter of triode Q4 are connected, the base of triode Q4 is connected between the base of triode Q3 and capacitor C1, the other end of capacitor C1 is grounded, resistance R8 and capacitor C2 are connected in parallel between resistance R7 and output terminal OUT;The emitter of triode Q2 is connected with power supply VCC and one end of resistance R3, the other end of resistance R3 is connected with resistance R4, the other end of resistance R4 is connected with the collector of triode Q1, the base of the triode Q2 is connected between resistance R3 and resistance R4, the emitter of triode Q1 is grounded, the base of triode Q1 is connected with one end of resistance R1 and one end of resistance R2, the other end of the resistance R1 is connected with input terminal IN, and the other end of the resistance R2 is grounded.

[0006] As a preferred technical scheme of the utility model, the triode Q2 and triode Q4 are PNP type triodes.

[0007] As a preferred technical scheme of the utility model, the triode Q1 and triode Q3 are NPN type triodes.

[0008] Summarized above, the beneficial effects of the utility model are:

[0009] 1. The level conversion and driving current amplification of high-speed PWM signal is realized by using the different conduction characteristics of NPN and PNP transistors to construct the amplification circuit of PWM signal level and driving current, which is very low in cost and good in performance;

[0010] 2. The input IN is usually controlled by the MCU to output, the level of the driving output OUT is determined by the voltage of the power supply VCC, the driving current is determined by the maximum current of the emitter of the transistor Q3 and the transistor Q4 and the size of the current limiting resistors R7 and R8, and the level of the input IN is consistent with that of the output OUT;

[0011] 3. The base resistors of the transistors are matched to make the transistors in the saturated conduction state, when the input IN is high, the transistor Q1 is turned on to make the base of the transistor Q2 low and turned on, the base voltage of the transistor Q3 and the transistor Q4 is-0.7V, when the voltage of the output OUT is lower than-1.4V, the transistor Q3 is turned on, the transistor Q4 is turned off, and the output OUT outputs high level; when the input IN is low, the transistor Q1 is turned off to make the base of the transistor Q2 high and pulled up to be turned off, the base voltage of the transistor Q3 and the transistor Q4 is 0V, when the voltage of the output OUT is higher than 0.7V, the transistor Q4 is turned on, the transistor Q3 is turned off, and the output OUT outputs low level;

[0012] 4. The base and the emitter of the transistor Q3 and the transistor Q4 are in the same potential by using the conduction characteristics of the transistors, which physically prevents the short circuit risk caused by the simultaneous conduction of the transistors; the current limiting resistors R7 and R8 avoid the harm of large current caused by the short circuit of the output OUT, and the capacitor C2 can filter the high-frequency interference in the level conversion. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is the circuit diagram of the utility model. DETAILED DESCRIPTION

[0014] Various embodiments of the present application will be described in greater detail below with reference to the accompanying drawings. In each of the drawings, the same elements are denoted by the same or similar reference numerals. Each part in the drawings is not drawn to scale for the sake of clarity.

[0015] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0016] like Figure 1 The circuit shown is a pure hardware circuit for high-speed push-pull drive output, including resistors R1, R2, R3, R4, R5, R6, R7, R8, transistors Q1, Q2, Q3, and Q4, capacitors C1 and C2.

[0017] The collector of transistor Q3 is connected to power supply VCC. The base of transistor Q3 is connected to one end of resistor R6 and capacitor C1. The other end of resistor R6 is connected between the collector of transistor Q2 and resistor R5. The other end of resistor R5 is grounded. The emitter of transistor Q3 is connected to resistor R7 and the emitter of transistor Q4. The base of transistor Q4 is connected between the base of transistor Q3 and capacitor C1. The other end of capacitor C1 is grounded. Resistor R8 and capacitor C2 are connected in parallel with resistor R7. The transistor Q2 is connected to the power supply VCC and one end of resistor R3. The other end of resistor R3 is connected to resistor R4. The other end of resistor R4 is connected to the collector of transistor Q1. The base of transistor Q2 is connected between resistors R3 and R4. The emitter of transistor Q1 is grounded. The base of transistor Q1 is connected to one end of resistor R1 and one end of resistor R2. The other end of resistor R1 is connected to the input terminal IN. The other end of resistor R2 is grounded.

[0018] In this embodiment, transistors Q2 and Q4 are PNP transistors, and transistors Q1 and Q3 are NPN transistors.

[0019] High-speed PWM signal level conversion and drive current amplification are achieved by using transistors. By utilizing the different conduction characteristics of NPN and PNP transistors, an amplifier circuit for PWM signal level and drive current can be constructed, which is very low in cost and has good performance.

[0020] Working principle: the input end IN is usually controlled by the MCU output, the level of the driving output end OUT is determined by the voltage of the power supply VCC, the driving current depends on the maximum current of the emitter of the transistor Q3 and the transistor Q4 and the size of the current limiting resistor R7, R8, the level of the input end IN and the output end OUT keeps consistent; the base resistors of the transistors are matched, so that the transistors are in the saturated conduction state, when the input end IN is high level, the transistor Q1 is turned on, so that the base of the transistor Q2 is low level and turned on, the base voltage of the transistor Q3 and the transistor Q4 is-0.7V, when the voltage of the output end OUT is lower than-1.4V, the transistor Q3 is turned on, the transistor Q4 is turned off, and the output end OUT outputs high level; when the input end IN is low level, the transistor Q1 is turned off, so that the base of the transistor Q2 is high level and pulled up to be turned off, the base voltage of the transistor Q3 and the transistor Q4 is 0V, when the voltage of the output end OUT is higher than 0.7V, the transistor Q4 is turned on, the transistor Q3 is turned off, and the output end OUT outputs low level; by using the conduction characteristics of the transistors, the base and the emitter of the transistor Q3 and the transistor Q4 are in the same potential, so that the risk of short circuit caused by the simultaneous conduction of the transistors is physically eliminated; the current limiting resistor R7 and the current limiting resistor R8 limit the current to avoid the harm of large current caused by the short circuit of the output end OUT, and the capacitor C2 can filter the high frequency interference in the level conversion, and can provide a certain degree of compensation current for the load such as the driving MOS tube (not shown in the figure) which has a momentary large current impact.

[0021] The basic principle, main characteristics and advantages of the utility model are shown and described above. It should be understood by those skilled in the art that the utility model is not limited by the above examples, the above examples and the description in the specification are only preferred examples of the utility model, and are not used to limit the utility model, various changes and improvements of the utility model can be made without departing from the spirit and scope of the utility model, these changes and improvements all fall within the scope of the utility model claimed, and the protection scope of the utility model is defined by the appended claims and their equivalents.

Claims

1. A purely hardware circuit for high speed push-pull drive output, characterized by: The circuit comprises resistors R1, R2, R3, R4, R5, R6, R7, R8, transistors Q1, Q2, Q3, Q4, capacitor C1 and capacitor C2. The collector of the transistor Q3 is connected to a power supply VCC, the base of the transistor Q3 is connected to one end of the resistor R6 and the capacitor C1, the other end of the resistor R6 is connected between the collector of the transistor Q2 and the resistor R5, the other end of the resistor R5 is grounded, the emitter of the transistor Q3 is connected to the resistor R7 and the emitter of the transistor Q4, the base of the transistor Q4 is connected between the base of the transistor Q3 and the capacitor C1, the other end of the capacitor C1 is grounded, the resistor R8 and the capacitor C2 are connected in parallel between the resistor R7 and an output terminal OUT; the emitter of the transistor Q2 is connected to the power supply VCC and one end of the resistor R3, the other end of the resistor R3 is connected to the resistor R4, the other end of the resistor R4 is connected to the collector of the transistor Q1, the base of the transistor Q2 is connected between the resistor R3 and the resistor R4, the emitter of the transistor Q1 is grounded, the base of the transistor Q1 is connected to one end of the resistor R1 and one end of the resistor R2, the other end of the resistor R1 is connected to an input terminal IN, and the other end of the resistor R2 is grounded.

2. A pure hardware circuit for high speed push-pull drive output as claimed in claim 1 characterized by: The transistors Q2 and Q4 are PNP type transistors.

3. The pure hardware circuit for high speed push-pull drive output of claim 1, wherein: The transistors Q1 and Q3 are NPN type transistors. The transistors Q1 and Q3 are NPN type transistors.

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