High-resolution analog-to-digital conversion equivalent circuit device

Abstract

The utility model relates to the technical field of low-frequency application occasions for voltage and current measurement and acquisition, in particular to a high-resolution analog-to-digital conversion equivalent circuit device, which comprises a sawtooth wave generating circuit, a voltage / current acquisition and conversion circuit, a signal shaping circuit and an MCU (Microprogrammed Control Unit) analog-to-digital conversion circuit, the voltage / current acquisition and conversion circuit obtains a sampling voltage Vsample, the sawtooth wave voltage V-carrier and the sampling voltage Vsample are compared and shaped through the signal shaping circuit to output a rectangular wave Vduty x, and the rectangular wave Vduty x is processed and transmitted to the MCU analog-to-digital conversion circuit for duty ratio sampling to complete analog-to-digital conversion. The utility model provides a novel voltage and current acquisition circuit which is built by utilizing the comparator and replaces an ADC (Analog to Digital Converter), and has the advantages of low cost, low power consumption, easiness in integration, high stability and the like.

Description

TECHNICAL FIELD

[0001] The utility model relates to low frequency application occasion technical field of voltage, current measurement collection, especially, relate to a kind of high-resolution analog-digital conversion equivalent circuit device. BACKGROUND

[0002] With the rapid development of industrial automation and intelligentization, the demand for accurate collection of industrial analog quantities (such as voltage, current, etc.) is increasing. Although traditional analog-to-digital converters (ADCs) are widely used in voltage and current collection, they have problems such as high cost, high power consumption, and complex design. In particular, in some cost-sensitive or space-limited application scenarios, traditional ADC solutions may not be the best choice. Therefore, it is of great significance to develop a low-cost, low-power, easy-to-integrate circuit that can meet the needs of industrial analog quantity collection.

[0003] Currently, the following problems exist:

[0004] 1) High cost: Traditional high-resolution analog-to-digital converter (ADC) solutions often rely on high-precision, high-performance ADC chips, which are expensive, increasing the overall system manufacturing cost, especially in large-scale deployment or cost-sensitive applications, this problem is particularly prominent;

[0005] 2) High power consumption: High-performance ADCs usually consume more power when running, which is a significant burden for battery-powered or low-power industrial applications, limiting the device's working time and long-term operation feasibility;

[0006] 3) Design complexity: The design and debugging process of ADC circuit is relatively complex, requiring SPI or IIC master-slave communication mechanism, increasing the consumption of MCU hardware resources. INVENTION CONTENT

[0007] The utility model provides a kind of high-resolution analog-digital conversion equivalent circuit device, provide a novel voltage and current collection circuit of alternative ADC built by comparator, with low cost, low power consumption, easy to integrate and high stability etc., can be widely applied in the field of industrial analog quantity collection. No digital communication, without occupying MCU communication interface, save hardware resources, reduce MCU selection requirement.

[0008] The utility model discloses a high resolution's analog-digital conversion equivalent circuit device, sawtooth wave generating circuit, voltage / current collection conversion circuit, signal shaping circuit and MCU analog-digital conversion circuit, sawtooth wave generating circuit produces sawtooth wave voltage V carrier, voltage / current collection conversion circuit gets sampling voltage V sample, and sawtooth wave voltage V carrier and sampling voltage V sample compare shaping output rectangular wave V duty x through signal shaping circuit, and rectangular wave V duty x is handled transmission to MCU analog-digital conversion circuit and carries out duty cycle sampling and completes analog-digital conversion.

[0009] As the optimization scheme of the utility model, the voltage / current collection conversion circuit includes first resistance R1, second resistance R2, third resistance R3, fourth resistance R4, fifth resistance R5, first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4 and first operational amplifier U2, the first capacitor C1 is connected with the first terminal and the second terminal respectively, the first resistance R1, the third resistance R3 and the fourth resistance R4 are connected in series between the first terminal and the 5th pin of the first operational amplifier U2, one end of the second resistance R2 is connected between the first resistance R1 and the third resistance R3, the other end of the second resistance R2 is grounded, one end of the third capacitor C3 is connected between the third resistance R3 and the fourth resistance R4, the other end of the third capacitor C3 is grounded, the second capacitor C2 is connected between the 5th pin of the first operational amplifier U2 and ground, the 4th pin of the 5th pin of the first operational amplifier U2 is connected with the 1st pin of the first operational amplifier U2, and the 1st pin of the first operational amplifier U2 is grounded through the series resistance R5 and capacitor C4.

[0010] As the optimization scheme of the utility model, the sawtooth wave generating circuit includes first voltage reference U1, sixth resistance R6, seventh resistance R7, eighth resistance R8, ninth resistance R9, tenth resistance R10, fifth capacitor C5, sixth capacitor C6, first MOS tube Q1 and second MOS tube Q2, the first voltage reference U1 is grounded through the ninth resistance R9, the sixth resistance R6 is connected between the power supply VCC and the 1st pin of the first voltage reference U1, the seventh resistance R7 is connected between the 1st pin and the 2nd pin of the first voltage reference U1, the gate of the first MOS tube Q1 is connected with the 3rd pin of the first voltage reference U1, the source of the first MOS tube Q1 is connected with the 2nd pin of the first voltage reference U1, the drain of the first MOS tube Q1 is connected with the drain of the second MOS tube Q2, the fifth capacitor C5 is connected between the drain of the second MOS tube Q2 and the source of the second MOS tube Q2, the gate of the second MOS tube Q2 is grounded through the sixth capacitor C6, the drain of the first MOS tube Q1 is connected with the signal shaping circuit through the eighth resistance R8, and the gate of the second MOS tube Q2 is connected with the signal shaping circuit through the tenth resistance R10.

[0011] As an optimization scheme of the utility model, signal shaping circuit includes first voltage comparator U2, second voltage comparator U3, second voltage reference U6, first exclusive or logic gate XOR GATE, eleventh resistance R11, twelfth resistance R12, seventh capacitor C7, eighth capacitor C8 and ninth capacitor C9, the 4th pin of first voltage comparator U2 is connected with the 5th pin of second voltage comparator U3, the 4th pin of second voltage comparator U3 is grounded through seventh capacitor C7, the 4th pin of second voltage comparator U3 is connected with the 2nd pin of second voltage reference U6 through eleventh resistance R11, the 2nd pin of second voltage reference U6 is grounded through ninth capacitor C9, the 1st pin of first voltage comparator U2 is connected with the 1st pin of first exclusive or logic gate XOR GATE, the 1st pin of second voltage comparator U3 is connected with the 2nd pin of first exclusive or logic gate XOR GATE.

[0012] As an optimization scheme of the utility model, MCU analog-to-digital conversion circuit includes first single-chip microcomputer MCU, the 3rd pin (external interrupt trigger pin) of first single-chip microcomputer MCU is connected with the 4th pin of first exclusive or logic gate XOR GATE.

[0013] The utility model has the positive effect: 1) the utility model replaces the expensive ADC chip by utilizing the low-cost comparator, and the hardware cost is greatly reduced.Compared with ADC chip, voltage comparator is more versatile, and the device is strong in replaceability.Compared with ADC chip, voltage comparator greatly reduces power consumption.The design is simple, and SPI or IIC communication peripherals do not need to be provided;

[0014] 2) the utility model solves the limitations of traditional ADC in industrial analog quantity acquisition, and realizes accurate acquisition of voltage and current signals by innovatively using comparator instead of traditional ADC.Comparator is a basic electronic element, and has the advantages of low cost, low power consumption and fast response speed.Through the ingenious design of the connection mode and working mode of comparator, the resolution comparable to high-performance ADC or even better can be realized.In addition, various interference and noise problems that may exist in industrial environment are considered, and the stability and reliability of the acquired signal are improved by optimizing the circuit design and introducing filtering mechanism.It is not only suitable for general industrial analog quantity acquisition scene, but also can work stably in harsh industrial environment;

[0015] 3) the utility model provides a novel ADC voltage and current acquisition circuit built by using comparator, which has the advantages of low cost, low power consumption, easy integration and high stability, and can be widely used in the field of industrial analog quantity acquisition.There is no digital communication, and the MCU communication interface does not need to be occupied, so that hardware resources are saved, and the MCU selection requirement is reduced. Attached Figure Description

[0016] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0017] Figure 1 This is a schematic diagram of the principle of this utility model;

[0018] Figure 2 This is the circuit schematic diagram of the voltage / current acquisition and conversion circuit of this utility model;

[0019] Figure 3 This is the circuit diagram of the sawtooth wave generating circuit of this utility model;

[0020] Figure 4 This is the circuit schematic diagram of the signal shaping circuit and the MCU analog-to-digital conversion circuit of this utility model;

[0021] Figure 5 This is a schematic diagram of the duty cycle output waveform of the first voltage comparator of this utility model when the input is 16mA;

[0022] Figure 6 This is a schematic diagram of the fixed duty cycle output waveform of the second voltage comparator of this utility model;

[0023] Figure 7 This is a schematic diagram showing the output duty cycle relationship of the first XOR logic gate when the input is 4mA.

[0024] Figure 8 This is a schematic diagram showing the output duty cycle relationship of the first XOR logic gate when the input is 12mA.

[0025] Figure 9 This is a schematic diagram showing the output duty cycle relationship of the first XOR logic gate when the input is 20mA. Detailed Implementation

[0026] like Figure 1 As shown, this utility model discloses a high-resolution analog-to-digital conversion equivalent circuit device, including a sawtooth wave generation circuit, a voltage / current acquisition and conversion circuit, a signal shaping circuit, and an MCU analog-to-digital conversion circuit. The sawtooth wave generation circuit generates a sawtooth wave voltage V-carrier, the voltage / current acquisition and conversion circuit obtains a sampled voltage V_sample, the sawtooth wave voltage V-carrier and the sampled voltage V_sample are compared and shaped by the signal shaping circuit to output a rectangular wave V_duty_x, the rectangular wave V_duty_x is processed and transmitted to the MCU analog-to-digital conversion circuit for duty cycle sampling to complete the analog-to-digital conversion.

[0027] like Figure 2As shown, the voltage / current acquisition and conversion circuit includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, and a first operational amplifier U2. The first capacitor C1 is connected to both the first and second terminals. The first resistor R1, the third resistor R3, and the fourth resistor R4 are connected in series between the first terminal and the fifth pin of the first operational amplifier U2. One end of the second resistor R2 is connected between the first resistor R1 and the third resistor R3, and the other end is grounded. One end of the third capacitor C3 is connected between the third resistor R3 and the fourth resistor R4, and the other end is grounded. The second capacitor C2 is connected between the fifth pin of the first operational amplifier U2 and ground. The fourth pin of the fifth pin of the first operational amplifier U2 is connected to the first pin of the first operational amplifier U2. The first pin of the first operational amplifier U2 is grounded through the series resistor R5 and capacitor C4.

[0028] like Figure 3 As shown, the sawtooth wave generating circuit includes a first voltage reference U1, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a fifth capacitor C5, a sixth capacitor C6, a first MOSFET Q1, and a second MOSFET Q2. The first voltage reference U1 is grounded through the ninth resistor R9. The sixth resistor R6 is connected between the power supply VCC and the first voltage reference U1's first pin. The seventh resistor R7 is connected between the first voltage reference U1's first pin and second pin. The gate of the first MOSFET Q1 is connected to the first voltage reference U1's third pin. The source of the first MOSFET Q1 is connected to the first voltage reference U1's second pin. The drain of the first MOSFET Q1 is connected to the drain of the second MOSFET Q2. The fifth capacitor C5 is connected between the second MOSFET Q2's drain and the second MOSFET Q2's source. The gate of the second MOSFET Q2 is grounded through the sixth capacitor C6. The drain of the first MOSFET Q1 is connected to the signal shaping circuit through the eighth resistor R8. The gate of the second MOSFET Q2 is connected to the signal shaping circuit through the tenth resistor R10.

[0029] like Figure 4As shown, the signal shaping circuit includes a first voltage comparator U2, a second voltage comparator U3, a second voltage reference U6, a first XOR logic gate, an eleventh resistor R11, a twelfth resistor R12, a seventh capacitor C7, an eighth capacitor C8 and a ninth capacitor C9, the pin 4 of the first voltage comparator U2 is connected with the pin 5 of the second voltage comparator U3, the pin 4 of the second voltage comparator U3 is grounded through the seventh capacitor C7, the pin 4 of the second voltage comparator U3 is connected with the pin 2 of the second voltage reference U6 through the eleventh resistor R11, the pin 2 of the second voltage reference U6 is grounded through the ninth capacitor C9, the pin 1 of the first voltage comparator U2 is connected with the pin 1 of the first XOR logic gate, and the pin 1 of the second voltage comparator U3 is connected with the pin 2 of the first XOR logic gate. The MCU analog conversion circuit includes a first single-chip microcomputer MCU, and the pin 3 of the first single-chip microcomputer MCU is connected with the pin 4 of the first XOR logic gate. The first single-chip microcomputer MCU can be any single-chip microcomputer, which is connected to an external interrupt trigger pin.

[0030] The current / voltage is input through the first and second wiring terminals, is sampled by the first and second resistors R1 and R2, is connected to the third resistor R3, the third capacitor C3, the fourth resistor R4 and the second capacitor C2 to form a second-order low-pass filter circuit, is connected to the 5-pin input positive terminal of the first operational amplifier U2, is connected to the 4-pin input negative terminal of the first operational amplifier U2 and the 1-pin output positive terminal to form a voltage follower. The output pin of the first operational amplifier U2 is connected to the fifth resistor R5 and the fourth capacitor C4 to form a first-order filter, and the sampled signal V_sample after filtering is transmitted to the 5-pin of the first voltage comparator U2. The 1-pin of the first voltage comparator U2 is connected to the 1-pin of the first XOR logic gate, and the 4-pin of the first voltage comparator U2 is connected to the 5-pin of the second voltage comparator U3. The 1-pin of the second comparator is connected to the 2-pin of the first XOR logic gate. The 4-pin of the first XOR logic gate is connected to the 1-pin of the first single-chip microcomputer MCU. The 4-pin of the second voltage comparator is connected to the 2-pin of the second voltage reference through an RC filter composed of the eleventh resistor R11 and the seventh capacitor C7, the 2-pin of the second voltage reference is connected to the ninth capacitor C9, and the 1-pin of the second voltage reference is connected to the eighth capacitor C8, and the 1-pin is connected to the power supply VCC through the twelfth resistor R12.

[0031] The power supply is connected to the 1 pin of the first voltage reference through the sixth resistor R6, the 1 pin of the first voltage reference is connected to the 2 pin of the first voltage reference through the seventh resistor R7, the 2 pin of the first voltage reference is connected to the 2 pin of the first MOS tube, the 1 pin of the first MOS tube is connected to the 3 pin of the first voltage reference, and the 1 pin of the first MOS tube is connected to the ground through the ninth resistor R9. The 3 pin of the first MOS tube is connected to the ground through the first capacitor. Meanwhile, the 3 pin of the first MOS tube is connected to the 3 pin of the second MOS tube, and the 3 pin of the second MOS tube is connected to the eighth resistor R8 to the 4 pin of the first voltage comparator and the second voltage comparator. The 1 pin of the second MOS tube is connected to the 4 pin of the MCU through the tenth resistor, and the 1 pin of the second MOS tube is connected to the sixth capacitor C6 to the ground.

[0032] The following will be described in combination with Figures 1 to 3 Taking the conversion of the commonly used 4-20mA current sampling in industry as an example, the high-resolution analog-digital conversion principle is introduced.

[0033] The first voltage reference U1 is a high-side feedback reference, and the current flowing through the second resistor from VCC is constant I1=V_ref / R2, forming a constant current source to charge the first capacitor. The PWM generated by the single-chip microcomputer (the first single-chip microcomputer MCU) reaches the 1 pin of the second MOS tube through the fifth resistor R5 and the second capacitor C2, controls the conduction and shutdown of the MOS tube, and when the second MOS tube is off, the first capacitor C1 is charged with a constant current I1, and U=∫idt / C, the voltage of the first capacitor rises at a fixed slope; when the second MOS tube is on, the first capacitor C1 discharges through the second MOS tube, and the voltage drops to 0V. With the periodic conduction and shutdown of the second MOS tube, a fixed-period sawtooth wave V_carrier is generated, which is input to the input negative end of the first voltage comparator and the positive end of the second voltage comparator for input voltage comparison. The current flows through the first resistor R1, the second resistor R2, and then returns to the second terminal, generating a sampling voltage V_r2 on the second resistor R2, which is transmitted to the input positive end of the first operational amplifier through the second-order low-pass filter composed of the third resistor R3, the third capacitor C3, the fourth resistor R4 and the second capacitor C2, followed by the first operational amplifier negative end to the output 1 pin of the first operational amplifier, and then through the first-order RC filter composed of the fifth capacitor C5 and the fourth capacitor C4 to obtain a stable sampling voltage V_sample. V_sample and the sawtooth wave voltage V-carrier generated by the sawtooth wave generating circuit are compared and shaped, and a rectangular wave (V_duty_x) with a fixed period and a variable pulse width is output, Figure 5 The first voltage comparator input-output relationship when the current input is 16mA.

[0034] The second voltage reference generates a constant voltage V_ref under the excitation of the VCC, which is transmitted to the negative input of the second voltage comparator through the ninth resistor and the seventh capacitor. V_ref is compared with the sawtooth wave at the positive input of the second voltage comparator, and a fixed duty cycle voltage V_duty0 is output to the output 1 of the second voltage comparator, as shown in Figure 6 .

[0035] The V_duty_x output by the first voltage comparator and the V_duty0 output by the second voltage comparator are operated under the first XOR logic gate to output V_duty_y, the pulse width of which has a linear relationship with the input signal. V_duty_y is transmitted to the 3-pin timer capture port of the MCU, and the duty cycle sampling is performed by the MCU. As shown in Figure 7 , Figure 8 , Figure 9 The input relationship of the first XOR logic gate when the current is 4mA, 12mA and 20mA.

[0036] The MCU captures the duty cycle at 4mA and 20mA corresponding values through the timer, and performs linear relationship mapping, that is, the analog-digital conversion of the 4-20mA analog quantity in the example can be completed. Only one 16-bit internal timer is needed, which can be equivalent to a 16-bit high-resolution ADC device.

[0037] The second voltage reference is introduced to generate a fixed duty cycle voltage. The result of the XOR operation of the first XOR logic gate and the first voltage comparator can distinguish the duty cycle generated when the input current sampling is 0V and exceeds the maximum amplitude of the sawtooth wave, thereby realizing the functions of input disconnection and over-range detection, enhancing the flexibility and efficiency of product application, and facilitating remote diagnosis and maintenance.

[0038] Element number explanation:

[0039] 1: first terminal.

[0040] 2: second terminal.

[0041] U1: first voltage reference Voltage Reference, 1 pin for output +, 2 pin for FB feedback pin, 3 pin for -, 1, 2 normal working state, this reference is high side feedback reference, the voltage between 1, 2 is a constant value V_fb.

[0042] U2: first voltage comparator Comparator, 1 pin connected to output, 2 pin connected to ground, 3 pin connected to power supply, 4 pin for comparator negative end, 5 pin for comparator positive end.

[0043] U3: second voltage comparator Comparator, 1 pin connected to output, 2 pin connected to ground, 3 pin connected to power supply, 4 pin for comparator negative end, 5 pin for comparator positive end.

[0044] U4: first exclusive OR logic gate xOR GATE, 1 foot is input A, 2 feet are input B, 3 feet are ground pins, 4 feet are exclusive OR logic output pins, and 5 feet are power supplies.

[0045] U5: first single-chip microcomputer MCU, 1 foot is connected to VCC; 2 feet are connected to GND; 3 feet are GPIO pins configured as timer capture, rising edge and falling edge trigger; 4 feet are GPIO pins configured as output pins, output square wave signal V_spuare.

[0046] U6: second voltage reference Voltage Reference, 1 foot is an output cathode, 2 feet are REF feedback pins, and 3 feet are anodes. This reference is a low-side feedback reference, and in the normal working state, 2 feet are always V_ref to 3 feet.

[0047] The above specific embodiments further illustrate the purpose, technical solutions and advantages of the utility model. It should be understood that the above description is only a specific embodiment of the utility model and is not intended to limit the utility model. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the utility model should be included in the protection scope of the utility model.

Claims

1. A high resolution analog-to-digital conversion equivalent circuit apparatus, characterized by: The sawtooth wave generating circuit, the voltage / current acquisition conversion circuit, the signal shaping circuit and the MCU analog conversion circuit are included, the sawtooth wave generating circuit generates the sawtooth wave voltage V-carrier, the voltage / current acquisition conversion circuit obtains the sampling voltage V_sample, the sawtooth wave voltage V-carrier and the sampling voltage V_sample are compared and shaped by the signal shaping circuit to output the rectangular wave V_duty_x, the rectangular wave V_duty_x is transmitted to the MCU analog conversion circuit for duty cycle sampling to complete the analog conversion; The signal shaping circuit includes the first voltage comparator U2, the second voltage comparator U3, the second voltage reference U6, the first XOR logic gate XOR GATE, the eleventh resistor R11, the twelfth resistor R12, the seventh capacitor C7, the eighth capacitor C8 and the ninth capacitor C9, the fourth pin of the first voltage comparator U2 is connected with the fifth pin of the second voltage comparator U3, the fourth pin of the second voltage comparator U3 is grounded through the seventh capacitor C7, the fourth pin of the second voltage comparator U3 is connected with the second pin of the second voltage reference U6 through the eleventh resistor R11, the second pin of the second voltage reference U6 is grounded through the ninth capacitor C9, the first pin of the first voltage comparator U2 is connected with the first pin of the first XOR logic gate XOR GATE, and the first pin of the second voltage comparator U3 is connected with the second pin of the first XOR logic gate XOR GATE.

2. A high resolution analog to digital conversion equivalent circuit means as claimed in claim 1, characterized in that: The voltage / current acquisition conversion circuit includes the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4 and the first operational amplifier U2, the first capacitor C1 is connected with the first terminal and the second terminal respectively, the first resistor R1, the third resistor R3 and the fourth resistor R4 are connected in series between the first terminal and the fifth pin of the first operational amplifier U2, one end of the second resistor R2 is connected between the first resistor R1 and the third resistor R3, the other end of the second resistor R2 is grounded, one end of the third capacitor C3 is connected between the third resistor R3 and the fourth resistor R4, the other end of the third capacitor C3 is grounded, the second capacitor C2 is connected between the fifth pin of the first operational amplifier U2 and the ground, the fourth pin of the fifth pin of the first operational amplifier U2 is connected with the first pin of the first operational amplifier U2, and the first pin of the first operational amplifier U2 is grounded through the resistor R5 and the capacitor C4 connected in series.

3. A high resolution analog to digital conversion equivalent circuit means as claimed in claim 2, characterized in that: The sawtooth wave generating circuit includes the first voltage reference U1, The sixth resistor R6, the seventh resistor R7, the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, the fifth capacitor C5, the sixth capacitor C6, the first MOS Q1 and the second MOS Q2, the first voltage reference U1 is grounded through the ninth resistor R9, the sixth resistor R6 is connected between the power supply VCC and the first pin of the first voltage reference U1, the seventh resistor R7 is connected between the first pin and the second pin of the first voltage reference U1, the gate of the first MOS Q1 is connected with the third pin of the first voltage reference U1, the source of the first MOS Q1 is connected with the second pin of the first voltage reference U1, the drain of the first MOS Q1 is connected with the drain of the second MOS Q2, the fifth capacitor C5 is connected between the drain of the second MOS Q2 and the source of the second MOS Q2, the gate of the second MOS Q2 is grounded through the sixth capacitor C6, the drain of the first MOS Q1 is connected with the signal shaping circuit through the eighth resistor R8, and the gate of the second MOS Q2 is connected with the signal shaping circuit through the tenth resistor R10.

4. A high resolution analog to digital conversion equivalent circuit means as claimed in claim 3, characterized in that: The MCU analog conversion circuit comprises a first single-chip microcomputer MCU, and the third pin of the first single-chip microcomputer MCU is connected with the fourth pin of a first exclusive-OR logic gate XOR GATE.

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