Stacked integrated circuit structure

Abstract

A stacked integrated circuit structure includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first bit line, at least one first SRAM cell electrically connected to the first bit line, a first bonding metal layer, and at least one first vertical conductive structure connecting the first bit line to a first metal line of the first bonding metal. The second semiconductor structure is over and bonded to the first semiconductor structure. The second semiconductor structure includes a second bit line, at least one second SRAM cell electrically connected to the second bit line, a second bonding metal layer, and at least one second vertical conductive structure connecting the second bit line to a second metal line of the second bonding metal layer. The first metal wire of the first bonding metal layer is bonded to the second metal wire of the second bonding metal layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a stacked integrated circuit structure. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. ICs have been in use for a number of years and, generally, their physical size has decreased while their complexity has increased. Therefore, the semiconductor industry has progressively developed new process techniques to increase the density of ICs so as to increase the number of interconnected devices per chip and to lower the cost of each chip.

[0003] During the progression of IC evolution, the functionality density, i.e., the number of interconnected devices per chip area, has generally increased while the geometry size, i.e., the smallest component (or line) that can be produced using a manufacturing process, has decreased. This scaling down process generally provides benefits in increased production efficiency and lower costs. Such scaling down also increases the relative power dissipation value, which can be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. SUMMARY

[0004] According to some embodiments of the present disclosure, a stacked integrated circuit (IC) structure includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first bit line, at least one first static random access memory cell, a first metal layer, and at least one first vertical conductive structure, wherein the at least one first static random access memory cell is electrically connected to the first bit line, and the at least one first vertical conductive structure connects the first bit line to a first metal line of the first metal layer. The second semiconductor structure is above and bonded to the first semiconductor structure. The second semiconductor structure includes a second bit line, at least one second static random access memory cell, a second metal layer, and at least one second vertical conductive structure, wherein the at least one second static random access memory cell is electrically connected to the second bit line, and the at least one second vertical conductive structure connects the second bit line to a second metal line of the second metal layer, and the first metal line of the first metal layer is bonded to the second metal line of the second metal layer.

[0005] According to some embodiments of this disclosure, a stacked IC structure includes a plurality of first bit lines, a plurality of first word lines, a first SRAM array including a plurality of first SRAM cells electrically connected to the first bit lines and the first word lines, a plurality of second bit lines, a plurality of second word lines, a second SRAM array stacked above the first SRAM array, a first conductive structure, and a second conductive structure. The second SRAM array includes a plurality of second SRAM cells electrically connected to the second bit lines and the second word lines. In a top view, the first bit lines and the second bit lines extend from a first region on a first side of the first SRAM array and the second SRAM array to a second region on a second side of the first SRAM array and the second SRAM array. The first conductive structure connects the first bit lines to the second bit lines, respectively. The first conductive structure is in the first region in the top view. The second conductive structure connects the first bit lines to the second bit lines, respectively. The second conductive structure is in the second region in the top view.

[0006] According to some embodiments of this disclosure, a stacked IC structure includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first bit line, a plurality of first transistors, and a first via metal layer. The first transistors form a plurality of first functional units. The first via metal layer includes a first metal line electrically connected to the first bit line. The first transistors are between the first bit line and the first via metal layer. The second semiconductor structure includes a second bit line, a plurality of second transistors, and a second via metal layer. The plurality of second transistors form a plurality of second functional units. The second via metal layer includes a second metal line electrically connected to the second bit line. The first semiconductor structure is bonded to the second semiconductor structure. The first metal line contacts the second metal line. BRIEF DESCRIPTION OF DRAWINGS

[0007] Aspects of the disclosure are best understood from the following detailed description taken in conjunction with the accompanying drawings on file. It should be noted that the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0008] FIG. 1A is a schematic diagram of an integrated circuit device according to some embodiments of this disclosure;

[0009] FIG. 1B is FIG. 1A is a circuit diagram of a static random access memory (SRAM) cell in the integrated circuit device of

[0010] FIG. 1C is FIG. 1B is a perspective view of a structure of the SRAM cell of

[0011] FIG. 2A is a schematic diagram of a single stack structure of an integrated circuit device according to some embodiments of the present disclosure;

[0012] FIG. 2B is a cross-sectional view of the single stack structure of the integrated circuit device of FIG. 2A FIG. 2A

[0013] FIG. 2C is a cross-sectional view of the single stack structure of the integrated circuit device of FIG. 2A FIG. 2A

[0014] FIG. 3A is a schematic diagram of an integrated circuit device according to some embodiments of the present disclosure;

[0015] FIG. 3B is a cross-sectional view of the single stack structure of the integrated circuit device of FIG. 3A FIG. 3A

[0016] FIG. 3C is a cross-sectional view of the single stack structure of the integrated circuit device of FIG. 3A FIG. 3A

[0017] FIG. 4A is a top view of a bottom layer of the integrated circuit device of FIG. 1A

[0018] FIG. 4B is a top view of a top layer of the integrated circuit device of FIG. 1A

[0019] FIG. 5 is a schematic diagram illustrating per-cell parasitic capacitance and capacitance increment according to some embodiments of the present disclosure;

[0020] FIG. 6A is a circuit diagram illustrating a bottom layer of an integrated circuit device according to some embodiments of the present disclosure;

[0021] FIG. 6B is a graph illustrating SRAM array size versus super via ratio according to some embodiments of the present disclosure;

[0022] FIG. 7 is a schematic diagram of an integrated circuit device according to some embodiments of the present disclosure;

[0023] FIG. 8A is a schematic diagram illustrating word line delay and delay improvement according to some embodiments of the present disclosure;

[0024] ​​​​​​​​​​FIG. 8B is a graph illustrating bit line delay and delay improvement according to some embodiments of the present disclosure;

[0025] FIG. 9 is a graph illustrating read access time versus cell number according to some embodiments of the present disclosure;

[0026] FIG. 10A is a graph illustrating energy per cycle versus delay time according to some embodiments of the present disclosure;

[0027] FIG. 10B is a graph illustrating normalized energy delay product (EDP) according to some embodiments of the present disclosure;

[0028] FIG. 11 to FIG. 17 cross-sectional view illustrating an intermediate stage of fabricating an integrated circuit device according to some embodiments of the present disclosure.

[0029]

Symbol Description

[0030] 100: integrated circuit device

[0031] 110: substrate

[0032] 110 b : substrate

[0033] 110 t : substrate

[0034] 112: substrate portion

[0035] 120: epitaxial stack

[0036] 122B: channel layer

[0037] 122T: channel layer

[0038] 124B: sacrificial layer

[0039] 124T: sacrificial layer

[0040] 126: interlayer semiconductor layer

[0041] 130: gate structure

[0042] 130B: gate structure

[0043] 130T: gate structure

[0044] 132B: interface layer

[0045] 132T: interface layer

[0046] 134B: high-k gate dielectric layer

[0047] 134T: high-k gate dielectric layer

[0048] 136B: gate electrode layer

[0049] 136B1: work function metal layer

[0050] 136B2: fill metal

[0051] 136T: gate electrode layer

[0052] 136T1: work function metal layer

[0053] 136T2: fill metal

[0054] 140B: source / drain epitaxial structure

[0055] 140T: source / drain epitaxial structure

[0056] 150: conductive structure

[0057] 150 b : conductive structure

[0058] 150 t : conductive structure

[0059] 160: dielectric material

[0060] 170: contact

[0061] 180: MLI structure

[0062] 180 b : MLI structure

[0063] 180 t : MLI structure

[0064] 182M: metal layer

[0065] 182M b : metal layer

[0066] 182M t : metal layer

[0067] 182V: metal via

[0068] 184: dielectric layer

[0069] 184 b : dielectric layer

[0070] 184 t : dielectric layer

[0071] 190: conductive structure

[0072] 190b : conductive structure

[0073] 190 t : conductive structure

[0074] AD b : address decoder

[0075] AD t : address decoder

[0076] BI: bonding interface

[0077] BL: bit line

[0078] BL b : bit line

[0079] BLB: bit line bar

[0080] BLB b : bit line bar

[0081] BL t : bit line

[0082] BLB t : bit line bar

[0083] BM: buried metal line

[0084] CM: conductive line

[0085] CV: conductive via

[0086] DG: dummy gate structure

[0087] C WL : parasitic capacitance

[0088] C BL : parasitic capacitance

[0089] DI: dielectric layer

[0090] DL: dielectric liner

[0091] DT1- DT2: dummy transistor

[0092] FS: fin

[0093] GE: gate electrode

[0094] GI: gate dielectric

[0095] GR: region of fin

[0096] GT: gate trench

[0097] HM: hard mask

[0098] ISO: isolation structure

[0099] LD b : bottom row decoder / bit decoder

[0100] LD t : top row decoder / bit decoder

[0101] M: SRAM cell

[0102] M1-M t : metal layer

[0103] M b : SRAM cell

[0104] M b11 -M bNN : bottom SRAM cell

[0105] M t : SRAM cell

[0106] M t11 -M tNN : top SRAM cell

[0107] Out b 1-Out b N: output node

[0108] Out t 1-Out t N: output node

[0109] PD1-PD2: pull-down transistor

[0110] PG1-PG2: pass-gate transistor

[0111] PU1-PU2: pull-up transistor

[0112] SA b : sense amplifier

[0113] SA t : sense amplifier

[0114] SDR: region of fin

[0115] SV BL : super via

[0116] SV BLB : super via

[0117] SV WL : super via

[0118] T1: trench

[0119] V DD : node

[0120] V DDb : node

[0121] V DDt : node

[0122] V ss : node

[0123] V SSb : node

[0124] V SSt : node

[0125] W: single stack structure

[0126] W b : layered structure

[0127] W t : layered structure

[0128] WL b : word line

[0129] WL t : word line

[0130] XC: line

[0131] XC1-XC2: storage data node

[0132] XC b : line

[0133] XC t : line

[0134] Z1-Z4: region DETAILED DESCRIPTION

[0135] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, formation of a first feature on, over, and or on top of a second feature in the following description can include embodiments where the first and second features are formed directly one on top of the other, and can also include embodiments where additional features can be formed between the first and second features such that the first and second features can not be directly in contact. In addition, the present disclosure can make reference to a number of means + functions. Mean + function claims are understood as being synonymous with functions performed by structures or logical combinations of structures. However, structure+function claims shall not be considered limiting of claims to the structure + function in which the claim is written. For example, a depositing data node structure+function claim shall cover the depositing data node structure+function in any structure+function with which the depositing data node structure+function is associated. Such includes dual claim forms having either dependency relations, as shown in the examples provided herein (e.g., a first claim dependent upon a second claim), or in dependent relation chains (e.g., a first claim dependent upon a second claim dependent upon a third claim) or in dependent relation networks.

[0136] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0137] As used herein, "about", "approximately", "around", or "substantially" can mean within 20% or within 10% or within 5% of a given value or range. However, those skilled in the art will recognize that the values or ranges described throughout the specification are merely examples and can decrease as integrated circuits scale. Quantities given herein are approximate, meaning that the term "about", "approximately", "around", or "substantially" can be inferred if not explicitly stated.

[0138] Gate all around (GAA) transistor structures can be patterned by any suitable method. For example, one or more optical lithography processes, including double patterning or multiple patterning processes, can be used to pattern the structures. Generally, double patterning or multiple patterning processes combine optical lithography with self-alignment processes, allowing patterns to be created with smaller pitches, for example, than can be obtained using a single direct optical lithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structures.

[0139] The term "multi-gate device" is used to describe a device (e.g., a semiconductor transistor) having at least some gate material disposed on multiple sides of at least one channel of the device. In some examples, a multi-gate device can be referred to as a gate all around (GAA) device or a nanosheet device having gate material disposed on at least four sides of at least one channel of the device. A channel region can be referred to as a "nanowire," as used herein, which includes channel regions of various geometries (e.g., cylindrical shape, strip shape) and various dimensions. In some examples, a multi-gate device can be referred to as a FinFET device. However, one of skill in the art will recognize that the teachings can apply to a single channel (e.g., a single nanosheet) or any number of channels. One of skill in the art can recognize other examples of semiconductor devices that can benefit from the aspects of the disclosure.

[0140] As fin width scales in fin field effect transistors (FinFETs), variations in channel width can result in mobility loss. GAA transistors, such as nanosheet transistors, are being investigated as replacements for FinFETs. In GAA transistors, the gate of the transistor is made all around the channel (e.g., nanosheet channel or nanowire channel), such that the channel is surrounded or encapsulated by the gate. Such transistors have the advantage of improved electrostatic control of the channel by the gate, which also mitigates leakage current. Stacked transistor structures, such as complementary field effect transistors (CFETs) including vertically stacked p-type FETs and n-type FETs, can provide further area reduction and density improvement for advanced integrated circuit (IC) technology nodes, particularly as IC technology nodes develop to 3nm (N3) and below.

[0141] FIG. 1A is a schematic diagram of an integrated circuit device 100 according to some embodiments of the present disclosure. The integrated circuit device 100 can include a bottom layer, a top layer above the bottom layer, and a plurality of super vias SV BL , SV BLB , and SV WL connected between the bottom layer and the top layer. In the bottom layer, the integrated circuit device 100 includes an array of bottom SRAM cells M b11 through M bNN , bottom bit lines BL b , bottom bit bar lines BLB b , bottom word lines WL b , a bottom address decoder AD b , a bottom row decoder LD b , and bottom sense amplifiers SA b . In the top layer, the integrated circuit device 100 includes an array of top SRAM cells M t11 through M tNN , top bit lines BL t , top bit bar lines BLB t , top word lines WL t , a top address decoder AD t , a top row decoder LD t , and top sense amplifiers SA t . The bottom word lines WL b connect the bottom address decoder AD b to the bottom SRAM cells M b11 through M bNN , and the bottom bit lines BLb and bottom bit bar line BLB b Bottom-line decoder LD b Extending to the bottom sensing amplifier SA b With bottom SRAM cell M b11 To M bNN Connection. Sensing amplifier SA b Signals can be sent to the output node Out. b 1. Out b 2. Out b (N-1), and Out b N. Top character line WL t Top address decoder AD t Connected to the top SRAM cell M t11 To M tNN And the top pixel line BL t and top-level bar line BLB t From top row decoder LD t Extending to the top sensing amplifier SA t With top SRAM cell M t11 To M tNN Connection. Sensing amplifier SA t Signals can be sent to the output node Out. t 1. Out t 2. Out t (N-1), and Out t N. Top line decoder LD t and bottom row decoder LD b It can also be called a bit decoder.

[0142] Bitline BL b and BL t and bit bar line BLB b and BLB t Can be along the character line WL b and WL t It can extend in different directions. For example, in FIG. 1A In the middle, bit line BL b and BL t and bit bar line BLB b and BLB t It can extend along the Y direction, character line WL b and WL t It can extend along a direction X that is substantially orthogonal to the direction Y.

[0143] In some embodiments disclosed herein, the bit line BL b Each of them is connected through two super-through-hole SV BLeach of the bit lines BL t is connected to each of the bit bar lines BLB b through two super vias SV BLB each of the bit bar lines BLB t is connected to each of the bit lines BL t And, the top row decoders LD t are configured in mirror with respect to the bottom row decoders LD b and the bottom address decoders ADt. For example, when viewed from the top, the row decoders LD b and LD t are disposed at opposite sides of the SRAM cell array, respectively. With the configuration of the super vias SV BL and SV BLB and the opposite configuration of the row decoders LD b and LD t , the conductive paths from any one of the SRAM cells M b11 to M bNN and M t11 to M tNN to the sense amplifiers SA t and SA b are reduced. As a result, with the reduction of the conductive paths, the signal transmission length is reduced (e.g., halved). Consequently, the access time to the SRAM cells is correspondingly reduced. The super vias SV BL , SV BLB , and SV WL may extend along a direction Z that is orthogonal to the directions X and Y. In this context, the super vias SV BL , SV BLB , and SV WL may also be referred to as vertical conductive structures.

[0144] In some further embodiments, each of the two outermost word lines WL b is connected to each of the two outermost word lines WL WL through several super vias SV t And, when viewed from the top, the address decoders AD b and AD t are disposed at opposite sides of the SRAM cell array, respectively. With the configuration of the super vias SV WL and the opposite configuration of the address decoders AD b and AD t , the conductive paths from the address decoders AD b and AD t to the SRAM cells M b11 to M b1N , M bN1 to M bNN, M t11 to M t1N , and M tN1 to M tNN of any one of the foregoing. Thus, with the reduction in conductive paths, the signal transmission length is reduced (e.g., halved). As a result, the access time to the SRAM cell is further reduced.

[0145] FIG. 1B is FIG. 1A an integrated circuit device. The SRAM cell M can represent the SRAM cell M b11 to M bNN , and M t11 to M tNN of any one of the foregoing. The SRAM cell M includes pull-up transistors PU1 and PU2, which are p-type Metal-Oxide-Semiconductor (PMOS) transistors, and pull-down transistors PD1 and PD2, and gate-through transistors PG1 and PG2, which are n-type Metal-Oxide-Semiconductor (NMOS) transistors. The gates of the gate-through transistors PG1 and PG2 are controlled by a word line WL, which determines whether the SRAM cell M is selected. A latch formed by the pull-up transistors PU1 and PU2 and the pull-down transistors PD1 and PD2 stores a bit, with the complement of the bit stored in storage data nodes XC1 and XC2. The stored bit can be written into or read from the SRAM cell M via complementary bit lines including a bit line BL and a bit bar line BLB. The SRAM cell M is powered via a positive supply node V DD with a positive supply voltage. The SRAM cell M is also connected to a supply voltage node V SS , which can be an electronic ground. The transistors PU1 and PD1 form a first inverter. The transistors PU2 and PD2 form a second inverter. The first and second inverters cross-latch. For example, the input of the first inverter (e.g., the gates of the transistors PU1 and PD1) is connected to the output of the second inverter (e.g., the drains of the transistors PU2 and PD2), and the output of the first inverter (e.g., the drains of the transistors PU1 and PD1) is connected to the input of the second inverter (e.g., the gates of the transistors PU2 and PD2). The input of the first inverter is also connected to the transistor PG2. The output of the first inverter is also connected to the transistor PG1.

[0146] The sources of the pull-up transistors PU1 and PU2 are connected to the positive supply node V DD . The sources of the pull-down transistors PD1 and PD2 are connected to the supply voltage node V SSThe gates of transistors PU1 and PD1 are connected to the drains of transistors PU2 and PD2, forming a connection node referred to as a storage data node XC2. The gates of transistors PU2 and PD2 are connected to the drains of transistors PU1 and PD1, forming a connection node referred to as a storage data node XC1. The source / drain region of pass gate transistor PG1 is connected to the bit line BL. The source / drain region of pass gate transistor PG2 is connected to the bit bar line BLB.

[0147] FIG. 1C is a perspective view illustrating FIG. 1B the structure of SRAM cell M. In some embodiments of the disclosure, SRAM cell M can include CFET structures. For example, a first CFET structure includes pull-down transistor PD1 and pull-up transistor PU1 vertically stacked above pull-down transistor PD1. For example, a second CFET structure includes pull-down transistor PD2 and pull-up transistor PU2 vertically stacked above pull-down transistor PD2. For example, a third CFET structure includes pass gate transistor PG1 and dummy transistor DT1 vertically stacked above pass gate transistor PG1. For example, a fourth CFET structure includes pass gate transistor PG2 and dummy transistor DT2 vertically stacked above pass gate transistor PG2. Thus, pull-up transistors PU1 and PU2 can be interchangeably referred to as top transistors, and pull-down transistors PD1 and PD2 and pass gate transistors PG1 and PG2 can be interchangeably referred to as bottom transistors.

[0148] In some embodiments, the bottom transistors and the top transistors are GAA FET transistors. The bottom transistors (e.g., transistors PD1, PD2, PG1, and PG2) include a first semiconductor channel layer 122B disposed on top of one another, a first gate structure 130B wrapped around each of the first semiconductor channel layers 122B, and a first source / drain epitaxial structure 140B on opposite sides of each of the first semiconductor channel layers 122B. The top transistors (e.g., transistors PU1 and PU2) include a second semiconductor channel layer 122T vertically stacked on top of one another, a second metal gate structure 130T wrapped around each of the second semiconductor channel layers 122T, and a second source / drain epitaxial structure 140T on opposite sides of each of the second semiconductor channel layers 122T. In the CFET structure, the second semiconductor channel layer 122T is disposed above and spaced apart from the first semiconductor channel layer 122B.

[0149] The first gate structure 130B can include an interface layer 132B, a high-k gate dielectric layer 134B around the interface layer, and a gate electrode layer 136B around the high-k gate dielectric layer 134B. The gate electrode layer 136B can include a work function metal layer 136B1 around the high-k gate dielectric layer 134B and a fill metal 136B2 around the work function metal layer 136B1. The second gate structure 130T can include an interface layer 132T, a gate dielectric layer 134T, and one or more gate electrode layers 136T. The gate electrode layer 136T can include a work function metal layer 136T1 around the high-k gate dielectric layer 134T and a fill metal 136T2 around the work function metal layer 136T1. In an SRAM CFET structure, the first gate structure 130B and the second gate structure 130T can be electrically connected to each other. In some embodiments, the combination of the gate structure 130B and the second gate structure 130T can be referred to as a gate structure.

[0150] In some embodiments, the bottom transistors (e.g., transistors PD1, PD2, PG1, and PG2) have a first conductivity type (e.g., n-type), and the top transistors (e.g., transistors PU1 and PU2) have a second conductivity type (e.g., p-type) different from the first conductivity type. Accordingly, the first source / drain epitaxial structure 140B is doped with a dopant species of the first conductivity type (e.g., n-type), and the second source / drain epitaxial structure 140T is doped with a dopant species of the second conductivity type (e.g., p-type). In some embodiments, the second gate structure 130T can be electrically connected to the first gate structure 130B, and the combination of the first and second gate structures 130T and 130B is referred to as a gate structure 130.

[0151] FIG. 2A is a schematic diagram of a single-stack structure W of an integrated circuit device 100 according to some embodiments of the present disclosure. FIG. 2B is a cross-sectional view of the single-stack structure W of the integrated circuit device of FIG. 2A is a cross-sectional view of the single-stack structure W of the integrated circuit device of FIG. 2A taken along a middle line B-B that passes through the source / drain epitaxial structure of a transistor. FIG. 2C is a cross-sectional view of the single-stack structure W of the integrated circuit device of FIG. 2A taken along a middle line C-C that does not pass through the source / drain epitaxial structure of a transistor. FIG. 2A is a cross-sectional view of the single-stack structure W of the integrated circuit device of FIG. 1A can constitute a top layer or a bottom layer of the integrated circuit device 100.

[0152] forming a buried metal line BM (e.g., a bit line BL, a bit bar line BLB, and a power voltage node V SSThe CFET structure, including transistors PD1, PD2, PG1, PG2, PU1, and PU2 in the SRAM cell M, is formed above the substrate 110. The conductive structure 150 may be formed as an extension from one of the embedded metal lines BM to the conductive features of the transistor. For example, the conductive structure 150 may extend from the bit bar line BLB, the bit line BL, and the power supply voltage node V. SS The line extends to the first source / drain epitaxial structure 140B. Dielectric material 160 may be formed to surround the transistor in the SRAM cell M. Conductive contacts 170 are formed in the dielectric material 160 and above the gate structure 130 of the CFET structure.

[0153] A multi-level interconnect (MLI) structure 180 is formed above the contact 170. The MLI structure 180 may include multiple metal layers 182M, metal vias 182V, and one or more dielectric layers 184, which span across the metal layers 182M. The metal layers 182M may include metal lines, such as word lines WL, lines for storage data nodes XC1 and XC2, and a positive power node V. DD The line. The combination of storage data node XC1 and storage data node XC2 can be called... FIG. 2A The lines XC1 and XC2 of the storage data nodes can contact the conductive contact 170. In some embodiments, the conductive structure 190 may be formed in the MLI structure 180 and extend from one of the metal layers 182M to a conductive feature beneath the MLI structure 180. For example, some of the conductive structure 190 may extend from the word line WL to the gate structure 130 in the CFET structure. Furthermore, some of the conductive structure 190 may extend from the positive power node V... DD The line extends to the source / drain epitaxial structure 140T in the CFET structure.

[0154] In some embodiments, the semiconductor substrate 110 may be a silicon substrate. Alternatively, the substrate 110 may include another elemental semiconductor, such as germanium; a compound semiconductor, including silicon carbide; an alloy semiconductor, including silicon-germanium; or combinations thereof. In some embodiments, the substrate 110 is a semiconductor-on-insulator (SOI) substrate. The substrate 110 may include doped regions, such as p-wells and n-wells. Transistors PD1, PD2, PG1, PG2, PU1, and PU2 may be formed using suitable transistor fabrication processes and may be planar transistors, such as polysilicon gate transistors or high-k metal gate transistors, or multi-gate transistors, such as fin field-effect transistors. After the transistors are formed, one or more metal / dielectric layers in a multi-level interconnect (MLI) are formed above the transistors.

[0155] In some embodiments, the metal layer 182M and the metal via 182V may comprise suitable metals such as aluminum, aluminum alloys, copper, copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, cobalt, the like, and / or combinations thereof. In some embodiments, the dielectric layer 184 comprises silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof. For example, the dielectric layer 184 may comprise an interlayer dielectric layer such as silicon oxide, fluorosilicone glass (FSG), carbon-doped silicon oxide, tetraethyl orthosilicate (TEOS) oxide, phosphosilicate glass (PSG), or borosilicate glass (BPSG). (Applied Materials, Santa Clara, California), amorphous fluorinated carbon, low-k dielectric materials, the like, or combinations thereof. The metal layer 182M, the metal via 182V, and the dielectric layer 184 may be formed using a dual damascene process and / or a single damascene process.

[0156] exist FIG. 2C In the middle, metal layer 182M is marked as metal layers M1 to M. t Metal via 182V and metal layers M1 to M t The metal wires can be stacked and electrically connected to each other to form a supervia (SV). BL SV BLB and SV WL They fall on bit line BL, bit bar line BLB, and word line WL, respectively. Supervia SV BL SV BLB and SV WL The top end (e.g., super-through SV) BL SV BLB and SV WL Metal layer M tThe top surface of the metal wire can be exposed by the dielectric layer 184 of the MLI structure 180, thereby preparing it for subsequent bonding processes. In some embodiments, the super-via SV BL SV BLB This may include some conductive structures below the MLI structure 180 and next to the transistor, wherein the supervia SV BL SV BLB The conductive structure may include one or more of the following: conductive lines CM (e.g., metal lines), conductive vias CV (e.g., metal vias), epitaxial structures, doped regions, or other suitable conductive features.

[0157] In some embodiments, such as FIG. 2A and FIG. 2B As shown, the power supply voltage node V DD The line represents the topmost metal layer 182M, thus preparing it for subsequent bonding processes. In some alternative embodiments, metal layer 182M is designated as metal layers M1 to M. t And the power supply voltage node V DD The wire can be electrically connected to the top metal layer M. t This prepares the site for the subsequent bonding process.

[0158] FIG. 3A This is a schematic diagram of an integrated circuit device according to some embodiments of the present disclosure. FIG. 3A The structure can correspond to FIG. 1A The stacked structure shown by the dashed block. FIG. 3B It is along FIG. 3A Midline BB cut FIG. 3A A cross-sectional view of an integrated circuit device, where line BB passes through the source / drain epitaxial structure of a transistor. FIG. 3C It is along FIG. 3A The center line CC intercept FIG. 3A A cross-sectional view of an integrated circuit device, where the line CC does not pass through the source / drain epitaxial structure of the transistor. FIG. 3A to FIG. 3C In the middle, two FIG. 2A to FIG. 2C The single-stacked structures are joined face-to-face. For example, such as FIG. 3A to FIG. 3C As shown, the top layered structure W t Including substrate 110 (substrate 110) t SRAM cell M t BL bit line t , bit bar line BLB t Including a 182M metal layer t and dielectric layer 184 t MLI structure 180 t Conductive structure 150 t Conductive structure 190 tand super vias SV BLt , SV BLBt , and SV WLt . Metal layer 182M t includes lines of power supply voltage nodes V SSt , lines XC t , word lines WL t , and lines of positive power supply nodes V DDt . Also, bottom tier structure W b includes substrate 110 (substrate 110 b ), SRAM cells M b , bit lines BL b , bit bar lines BLB b , MLI structure 180 b including metal layer 182M b and dielectric layer 184 b , conductive structure 150 b , conductive structure 190 b , and super vias SV BLb , SV BLBb , and SV WLb . Metal layer 182M b includes lines of power supply voltage nodes V SSb , lines XC b , word lines WL b , and lines of positive power supply nodes V DDb . Details of the configuration of these elements are shown in FIG. 2A to FIG. 2C and thus are not repeated here.

[0159] In FIG. 3A to FIG. 3C , top tier structure W t is joined with bottom tier structure W b through a joining process. Top tier structure W t is flipped and joined / adhered with bottom tier structure W b . The process of flipping results in a mirror configuration of the top SRAM array. In the joining process, dies are stacked on top of each other and connections between the dies are provided using copper-to-copper interconnects with very fine pitch. Copper-to-copper joining enables very close to monolithic design performance with little power and signal loss. The face-to-face joining process enables two SRAM cells to share common power and footprint.

[0160] For example, topmost metal layer 182M b is well aligned and joined with topmost metal layer 182M t , and dielectric layer 184 b is well aligned and joined with dielectric layer 184 t . The joining interface BI is as shown in FIG. 3A to FIG. 3C top tier structure Wt with the bottom layer structure W b , as indicated by the dashed lines. Depending on the design of the bonding process, the bonding interface BI can be observable or non-observable. In some embodiments, an alignment step is performed such that the super vias SV BLt , SV BLBt , and SV WLt are aligned along the direction Z with the super vias SV BLb , SV BLBb , and SV WLb , respectively.

[0161] Via the bonding process, the super vias SV BLt , SV BLBt , and SV WLt are connected with the super vias SV BLb , SV BLBb , and SV WLb , respectively. The combination of the super vias SV BLt and SV BLb may be referred to as a super via SV BL . The combination of the super vias SV BLBt and SV BLBb may be referred to as a super via SV BLB . And, the combination of the super vias SV WLt and SV WLb may be referred to as a super via SV WL . Via the bonding process, an integrated circuit device of FIG. 1A is formed.

[0162] FIG. 4A is a top view of the bottom layer of the integrated circuit device of FIG. 1A . FIG. 4B is a top view of the top layer of the integrated circuit device of FIG. 1A . FIG. 4A may overlap with FIG. 4B , in which context the combination of FIG. 4A and FIG. 4B may be referred to as a top view. The regions Z1-Z4 indicate the locations of the super vias SV BL , SV BLB , and SV WL . In FIG. 4A , the regions Z1 and Z2 are disposed on opposite sides of the SRAM cell array. In FIG. 4B , the regions Z3 and Z4 are disposed on opposite sides of the SRAM cell array. Via this configuration, the SRAM cells can be addressed by the closest one of the bottom address decoders AD b and the top address decoders AD t , as well as the bottom row decoders LD b and the top row decoders LDt the closest one in the middle to access.

[0163] For example, for SRAM cell M b11 , bottom address decoder AD b can send a read voltage to SRAM cell M b via word line WL b11 , data stored in SRAM cell M b11 is read out at output node Out t N by top sense amplifier SA t via bit line BL t , bit bar line BLB BL , and super via SV BLB and SV t .

[0164] For example, for SRAM cell M bNN , top address decoder AD t can send a read voltage to SRAM cell M t via word line WL WL and super via SV bNN , data stored in SRAM cell M bNN is read out at output node Out b N by bottom sense amplifier SA b via bit line BL b and bit bar line BLB b .

[0165] For example, for SRAM cell M b1N , bottom address decoder AD b can send a read voltage to SRAM cell M b via word line WL b1N , data stored in SRAM cell M b1N is read out at output node Out t 1 by top sense amplifier SA t via bit line BL t and bit bar line BLB BL and super via SV BLB and SV t .

[0166] FIG. 5 is a schematic diagram illustrating parasitic capacitance and capacitance increment per cell according to some embodiments of the present disclosure. Parasitic capacitance C t between word line WL b and WL WL (reference FIG. 3B ) and bit line BLt with BL b between BL BL (Ref FIG. 3B ). For a double stack structure that is bonded in a face-to-face manner, due to the presence of multiple conductive structures between the top and bottom SRAM cells, the densest structures are far apart from the regions through which the electrons flow (e.g., the transistors in the top and bottom SRAM cells). In addition, for a double stack structure, the directions of the two connected top and bottom metal lines (such as WL t and WL b or bit lines BL t and BL b ) are parallel to each other, reducing the cross-sectional area therebetween, which in turn can reduce the parasitic capacitance. Furthermore, the direction of the bonding metal layer (e.g., the positive power node V DD ) will be substantially perpendicular to the direction of the word lines WL t and WL b , and thus will minimize the impact of the bonding metal layer on the parasitic capacitance between the word lines WL t and WL b . Comparing the double stack structure with the single stack structure, with increasing transistor density, the parasitic capacitance between the word lines WL t and WL b and between the bit lines BL t and BL b is prevented from increasing by the far distance and reduced cross-sectional area. For example, comparing the double stack structure with the single stack structure, it is found that the increment of these bit line and word line parasitic capacitances from the double stack SRAM is less than 1%.

[0167] FIG. 6A is a circuit diagram of a bottom layer of an integrated circuit device according to some embodiments of the present disclosure. To create regions Z1 and Z2 (Ref FIG. 4A ) for positioning super vias SV BL , SV BLB , and SV WL , the lengths of the bit lines BL b and bit bar lines BLB b are increased. For example, the distance between a bottom row decoder LD b and a bit line BL b (or a bit bar line BLB b ) is increased by a distance ED1, and the distance between a sense amplifier SA b and a bit line BL b (or a bit bar line BLB b ) is increased by a distance ED2. The distances ED1 / ED2 can be in a range from about 40 nanometers to about 100 nanometers. The bit lines BL b(or bit bar lines BLB b ) by a distance ED1 / ED2 can provide additional pitch (e.g., one to two pitches between two adjacent word lines), aspect ratio flexibility, and a larger misalignment window for the stacking process. Although only the bottom tier is illustrated here, the top tier of the integrated circuit device can also include the same configuration. For example, in FIG. 1A , the distance between the top row decoders LD t and the bit lines BL t (or bit bar lines BLB t ) is increased by a distance ED1, and the distance between the sense amplifiers SA t and the bit lines BL t (or bit bar lines BLB t ) is increased by a distance ED2.

[0168] FIG. 6B A graph illustrating the relationship between SRAM array size and super via ratio according to some embodiments of the present disclosure is shown. As the SRAM array size increases, the super via ratio decreases. Therefore, the configuration of super vias is beneficial for large SRAM arrays.

[0169] FIG. 7 is a schematic diagram of an integrated circuit device 100 according to some embodiments of the present disclosure. The dual stack SRAM array can extend, for example, along the direction X and the direction Y. Also, the row decoders and the address decoders can be repeated.

[0170] FIG. 8A is a schematic diagram illustrating word line delay and delay improvement according to some embodiments of the present disclosure. FIG. 8B is a schematic diagram illustrating bit line delay and delay improvement according to some embodiments of the present disclosure. In FIG. 8A , via the configuration of super vias, the signal transmission length is reduced, and the overall delay time of the word lines can be improved by 30%. In FIG. 8B , via the configuration of super vias, the signal transmission length is reduced, and the overall delay time of the bit lines can be improved by 21%.

[0171] FIG. 9 is a graph illustrating read access time versus number of cells according to some embodiments of the present disclosure. As described above, the read access time is reduced using the configuration of super vias. Also, the reduction in read access time is more pronounced using more SRAM cells.

[0172] FIG. 10A is a graph illustrating energy per cycle versus delay time according to some embodiments of the present disclosure. FIG. 10Bis a diagram illustrating normalized energy-delay product (EDP) according to some embodiments of the present disclosure. A dual-stack structure including a super via can achieve a 30% EDP reduction compared to a single-stack structure.

[0173] FIG. 11 to FIG. 17 is a cross-sectional diagram illustrating an intermediate stage of fabricating an integrated circuit device according to some embodiments of the present disclosure. Reference is made to FIG. 11 A epitaxial stack 120 is formed over the substrate 110. In some embodiments, the substrate 110 can include silicon (Si). Alternatively, the substrate 110 can include germanium (Ge), silicon germanium (SiGe), a group III-V material (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaAnAs, InAs, GaInP, InP, InSb, and / or GaInAsP; or combinations thereof) or other suitable semiconductor material. In some embodiments, the substrate 110 can include a semiconductor on insulator (SOI) structure such as a buried dielectric layer. Additionally, the substrate 110 can include a buried dielectric layer such as a buried oxide (BOX) layer formed by a separation by implantation of oxygen (SIMOX) technique, wafer bonding, selective epitaxial growth (SEG), or another suitable method.

[0174] The epitaxial stack 120 includes a channel layer 122B, a sacrificial layer 124B, an interlayer semiconductor layer 126, a channel layer 122T, and a sacrificial layer 124T stacked over the substrate 110. The sacrificial layers 124B and 124T can have a different semiconductor composition than the channel layers 122B and 122T. In some embodiments, the layers 122B, 124B, 126, 122T, and 124T can include SiGe having various semiconductor compositions. For example, the Si concentration in the sacrificial layers 124B and 124T is less than the Si concentration in the channel layers 122B and 122T. In other words, in embodiments, the Ge concentration in the sacrificial layers 124B and 124T is greater than the Ge concentration in the channel layers 122B and 122T. For example, the channel layers 122B and 122T are Si x Ge 1-x , the sacrificial layers 124B and 124T are Si y Ge 1-y , the interlayer semiconductor layer 126 is Si z Ge 1-zwhere x and y are in the range of 0 to 1, and x > y. However, other embodiments are possible, including embodiments that provide materials / compositions with different oxidation rates and / or etch selectivity. In some embodiments where the sacrificial layers 124B and 124T and the channel layers 122B and 122T include Si, the Si oxidation rate of the channel layers 122B and 122T is less than the SiGe oxidation rate of the sacrificial layers 124B and 124T.

[0175] The channel layers 122B and 122T, or portions thereof, can form nanosheet channels of a multi-gate transistor. The term nanosheet is used herein to refer to any material portion having a nanoscale, or even a microscale, dimension, and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated material portions of circular and substantially circular cross-section, as well as beam-shaped or rod-shaped material portions including, for example, cylindrical shapes or substantially rectangular cross-sections. The channel layers 122B and 122T can be referred to in context as semiconductor channels. The use of the channel layers 122B and 122T to define one or more channels in a device is discussed further below.

[0176] For example, epitaxial growth of the layers in the stack 120 can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, epitaxially grown layers such as the channel layers 122B and 122T and the sacrificial layers 124B and 124T include a suitable semiconductor material such as Si, Ge, Sn, SiGe, GeSn, a III-V semiconductor, the like, or combinations thereof. In some embodiments, the channel layers 122B and 122T and the sacrificial layers 124B and 124T can include the same semiconductor material as the semiconductor material of the substrate 110. In some embodiments, the epitaxially grown sacrificial layers 124B and 124T include a different material than the substrate 110. For example, the sacrificial layers 124B and 124T include a suitable semiconductor material such as Si, Ge, SiGe, GeSn, a III-V semiconductor, the like, or combinations thereof. In some other embodiments, at least one of the layers 122B, 124B, 126, 122T, and 124T can include other materials such as compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. As described above, the materials of the layers 122B, 124B, 126, 122T, and 124T can be selected based on providing different oxidation and / or etching selectivity properties. In some embodiments, the layers 122B, 124B, 126, 122T, and 124T are intrinsic semiconductor layers that are not intentionally doped, e.g., do not have intentionally placed dopants, but rather have doping caused by process contaminants. In some embodiments, the layers 122B, 124B, 126, 122T, and 124T are substantially free of dopants (i.e., have a non-intrinsic dopant concentration of about 0 cm -3 to about 1 x 1018 18 cm -3 , e.g., no intentional doping is performed during the epitaxial growth process.

[0177] The interlayer semiconductor layer 126 can include a material that is different than the materials of the sacrificial layers 124B and 124T and the channel layers 122B and 122T. In some embodiments, the interlayer semiconductor layer 126 can include a semiconductor material such as SiGe, Ge, or other suitable semiconductor material having a semiconductor composition that is different than the semiconductor composition of the channel layers 122B and 122T and the sacrificial layers 124B and 124T. For example, the channel layers 122B and 122T are Six Ge 1-x The sacrificial layers 124B and 124T are Si y Ge 1-y The interlayer semiconductor layer 126 is Si z Ge 1-z where x, y, and z are in the range of 0 to 1, and x > y > z.

[0178] Referring FIG. 12 A plurality of semiconductor fins FS extending from the substrate 110 are formed. In various embodiments, each of the fins FS includes a portion of the substrate portion 112 formed from the substrate 110, and a portion of each of the epitaxial layers formed from the epitaxial stack 120, which includes the epitaxial layers 122B, 124B, 126, 122T, and 124T. The fins FS can be fabricated using suitable processes including a double patterning or multiple patterning process. Generally, a double patterning or multiple patterning process combines optical lithography with a self-alignment process, allowing a pattern to be created with, for example, a smaller pitch than is obtainable using a single direct optical lithography process. For example, in some embodiments, a sacrificial layer is formed over the substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, can then be used to pattern the fins FS by etching the initial epitaxial stack 120. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0179] The fins FS can then be fabricated using suitable processes including optical lithography and etching processes. The optical lithography process can include forming a photoresist layer (not shown), exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the resist to form a patterned mask including resist. In some embodiments, patterning the resist to form the patterned mask elements can be performed using an e-beam lithography process or an extreme ultraviolet (EUV) lithography process. The patterned mask can then be used to protect regions of the substrate 110, and layers formed thereon, while an etching process forms trenches T1 through the epitaxial stack 120, and into the substrate 110, in unprotected regions, leaving a plurality of extended fins FS. The trenches T1 can be etched using dry etching (e.g., reactive ion etching), wet etching, and / or combinations thereof. Many other embodiments of methods of forming fins on a substrate can also be used, including, for example, defining fin regions (e.g., by masking or isolating regions) and epitaxially growing the epitaxial stack 120 in the form of fins FS.

[0180] Referring FIG. 13A dielectric liner DL is formed in the trench T1, and one or more conductive materials are deposited into the trench T1 and over the dielectric liner DL. In some embodiments, the dielectric liner DL includes a low-k dielectric material, SiN, SiCN, SiOC, SiOCN, or the like. The conductive material can include a suitable metal, such as aluminum, an aluminum alloy, copper, a copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, cobalt, the like, and / or combinations thereof. One or more etching processes can be performed to remove a portion of the deposited conductive material, with the remaining portion of the conductive material forming a buried metal line BM. The buried metal line BM can be used as a bit line BL, a bit bar line BLB, and a power voltage node V SS

[0181] An isolation structure ISO is formed in the trench T1 between the fins FS. The isolation structure ISO can be a single layer structure or a multi-layer structure. In some embodiments, the isolation structure ISO includes a low-k dielectric material, SiN, SiCN, SiOC, SiOCN, or the like. The formation of the isolation structure ISO can include depositing a dielectric material over the structure in the trench T1, followed by an etch-back process. Via the etch-back process, a top surface of the isolation structure ISO can be planar with or lower than a top surface of the substrate portion 112. In some embodiments, the top surface of the isolation structure ISO is planar with the top surface of the substrate portion 112. In some alternative embodiments, the top surface of the isolation structure ISO is lower than the top surface of the substrate portion 112. FIG. 12

[0182] Referring to FIG. 14 One or more dummy gate structures DG are formed over the epitaxial stack 120. The dummy gate structure DG can include a gate dielectric GI, a gate electrode GE, and a hard mask HM. The gate dielectric GI can include one or more layers of dielectric materials, such as silicon oxide, silicon nitride, a high-k dielectric material, and / or other suitable dielectric materials. In some embodiments, the gate electrode GE includes a different material than the gate dielectric GI. In some embodiments, the gate dielectric GI can be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, an FCVD process, an ALD process, a PVD process, or other suitable processes. The gate electrode GE can include polysilicon. The hard mask HM can include a silicon oxide layer and a silicon nitride layer. In some embodiments, the materials of the dummy gate structure DG are formed by various processes, such as layer deposition, e.g., CVD, PVD, ALD, thermal oxidation, or other suitable deposition techniques, or combinations thereof.

[0183] ​​The dummy gate structure DG can be formed by first depositing a blanket gate dielectric layer, a gate electrode layer, and a mask layer, followed by a patterning and etching process. For example, the patterning process includes a lithography process (e.g., optical lithography or e-beam lithography), which can further include resist coating (e.g., spin-on coating), soft bake, mask alignment, exposure, post-exposure bake, resist development, rinsing, drying (e.g., spin-drying and / or hard bake), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process can include dry etching (e.g., RIE), wet etching, other etching methods, and / or combinations thereof. By patterning the dielectric layer, the gate electrode layer, and the mask layer, the dummy gate structure DG is formed over the region GR of the fin FS, while the region SDR of the fin is exposed on the opposite side of the dummy gate structure DG. In some embodiments, the bottom surface of the dummy gate structure DG (e.g., the bottom surface of the gate dielectric GI) is flush with the top surface of the substrate portion 112, such that a replacement high-k / metal gate stack of the dummy gate structure DG can be wrapped around the nanosheet but not wrapped around the top portion of the substrate portion 112. In some alternative embodiments, the bottom surface of the dummy gate structure DG (e.g., the bottom surface of the gate dielectric GI) is lower than the top surface of the substrate portion 112, such that a replacement high-k / metal gate stack of the dummy gate structure DG can be wrapped around the nanosheet and the top portion of the substrate portion 112. FIG. 15

[0184] Referring to FIG. 15 In the region SDR of the fin, a source / drain epitaxial structure 140B is formed on the opposite side of the channel layer 122B, and a source / drain epitaxial structure 140T is formed on the opposite side of the channel layer 122T. After forming the source / drain epitaxial structure 140B, and before forming the source / drain epitaxial structure 140T, a dielectric layer DI is formed over the source / drain epitaxial structure 140B. The dielectric layer DI can isolate the source / drain epitaxial structure 140B from the source / drain epitaxial structure 140T. In some embodiments, the dielectric layer DI can include a low-k dielectric material, SiN, SiCN, SiOC, SiOCN, or the like.

[0185] During various steps, one or more dielectric materials can be formed around the source / drain epitaxial structures 140B and 140T. The combined dielectric materials can be referred to as dielectric material 160.

[0186] ​In some embodiments, conductive structures 150 are formed in dielectric material 160 to connect source / drain epitaxial structures 140B to buried metal lines BM. Conductive structures 150 can comprise suitable conductive materials, such as aluminum, aluminum alloys, copper, copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, cobalt, the like, and / or combinations thereof. Formation of conductive structures 150 can include etching openings in dielectric material 160 and isolation structures ISO to expose buried metal lines BM, depositing a conductive material into the openings, and then performing a suitable etching or polishing process to remove excess portions of the conductive material. Via the configuration of conductive structures 150, source / drain epitaxial structures 140B can be connected to any of bit lines BL, bit bar lines BLB, and power supply voltage nodes VDD, VSS, and VDDQ in the memory array 100. SS

[0187] Referring FIG. 16 . Dummy gate structures DG in regions GR of the fins (referenced FIG. 14 ) and sacrificial layers 124B and 124T are replaced by high-k / metal gate structures 130. In FIG. 16 , dummy gate structures DG (referenced FIG. 14 ) are removed, followed by removal of sacrificial layers 124B and 124T (referenced FIG. 14 ). In the illustrated embodiment, dummy gate structures DG (referenced FIG. 14 ) are removed by using a selective etching process (e.g., a selective dry etching, a selective wet etching, or a combination thereof) that etches track gates GE (referenced FIG. 14 ) at a faster etching rate than other materials. Gate dielectric GI (referenced FIG. 14 ) can be removed by a suitable etching and / or cleaning process. As a result, sacrificial layers 124B and 124T (referenced FIG. 14 ) are exposed. Subsequently, sacrificial layers 124B and 124T (referenced FIG. 14 ) are etched by using another selective etching process that etches sacrificial layers 124B and 124T (referenced FIG. 14 ) at a faster etching rate than channel layers 122B and 122T.), thereby forming openings / spaces between adjacent channel layers 122B and 122T. In this way, the channel layers 122B and 122T become nanosheets suspended above the substrate 110 and between the source / drain epitaxial structures 140B and 140T, and the channel layers 122B and 122T become nanosheets suspended above the substrate 110 and between the source / drain epitaxial structures 140B and 140T. This step is also referred to as a channel release process. In this intermediate processing step, the openings / spaces around the nanosheets 122B and 122T can be filled with ambient conditions (e.g., air, nitrogen, etc.). In some embodiments, the nanosheets 122B and 122T can be interchangeably referred to as nanowires, nanosheets, and nanorings, depending on their geometry. For example, in some other embodiments, due to the selective etching process used to completely remove the sacrificial layers 124B and 124T, the channel layers 122B and 122T can be trimmed to have a substantially circular shape (i.e., cylindrical) (refer to FIG. 14 ). In this case, the resulting channel layers 122B and 122T can be referred to as nanowires.

[0188] In some embodiments, the sacrificial layers 124B and 124T (refer to FIG. 14 ) are removed by using a selective dry etching process (refer to FIG. 14 ). In some embodiments, the sacrificial layers 124B and 124T (refer to FIG. 14 ) are SiGe, and the channel layers 122B and 122T are silicon, thereby allowing the sacrificial layers 124B and 124T (refer to FIG. 16 ) to be selectively removed (refer to x ). For example, the oxidation can be provided by an O2 plasma, followed by removal of the SiGeO x by a chloride-based plasma (e.g., CF4 / C4F8 plasma) that selectively etches SiGeO x at a faster etching rate than Si, and terminates on SiGe. The steps of SiGe oxidation and SiGeO x removal can be repeated until the sacrificial layers 124B and 124T (refer to FIG. 16 ) are removed. Furthermore, because the oxidation rate of Si is much lower (sometimes 30 times lower) than that of SiGe, the channel layers 122B and 122T, as well as the substrate portion 112, can remain substantially intact during the channel release process.

[0189] refer to FIG. 1CReplacement gate structures 130 are formed in the gate trenches GT to surround each of the nanosheets 122B and 122T suspended in the gate trenches GT, respectively. The gate structures 130 can be the final gates of the GAA FETs. The final gate structures can be high-k / metal gate stacks, although other compositions are possible. In some embodiments, each of the gate structures 130 forms a gate associated with the multi-channel provided by the plurality of nanosheets 122B and 122T. For example, the high-k / metal gate structures 130 are formed within the openings / spaces provided by the release of the nanosheets 122B and 122T.

[0190] In various embodiments, the high-k / metal gate structures 130 include a gate dielectric layer formed around the nanosheets 122B and 122T and a gate electrode layer 136B / 136T formed around the gate dielectric layer. The formation of the high-k / metal gate structures 130 can include one or more deposition processes to form various gate materials, followed by a CMP process to remove excess gate materials, resulting in the high-k / metal gate structures 130 having a top surface that is flush with the top surface of the dielectric material 160. Thus, a transistor (e.g., a GAA FET) is formed, and the high-k / metal gate structures 130 surround each of the nanosheets 122B and 122T, and thus are referred to as the gates of the transistor (e.g., the GAA FET).

[0191] The gate dielectric layer can include an interface layer 132B / 132T (referenced FIG. 1C ) and a high-k gate dielectric layer 134B / 134T (referenced FIG. 1C ) over the interface layer 132B / 132T (referenced FIG. 1C ). In some embodiments, the interface layer 132B / 132T (referenced FIG. 1C ) is silicon oxide formed on the exposed surface of the semiconductor material by using, for example, thermal oxidation, chemical oxidation, wet oxidation, or the like. As a result, the surface of the layer 122B and 122T is partially oxidized into silicon oxide to form the interface layer. In some embodiments, the high-k gate dielectric layer 134B / 134T (referenced FIG. 17 ) includes a dielectric material such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO; HZO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), and aluminum oxide (Al2O3), the like, or a combination thereof.

[0192] In some embodiments, the gate electrode layer 136B / 136T includes one or more metal layers. For example, the gate electrode layer 136B / 136T can include one or more work function metal layers 136B1 / 136T1 and a fill metal 136B2 / 136T2 stacked on top of each other. The one or more work function metal layers 136B1 / 136T1 in the gate electrode layer 136B / 136T provide a suitable work function for the high-k / metal gate structure GS. For an n-type GAA FET, the gate electrode layer 136B can include one or more n-type work function metal (n-metal) layers 136B1. The n-type work function metal can illustratively include, but is not limited to, titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, titanium nitride (TiN), tungsten (W), and / or other suitable materials. On the other hand, for a p-type GAA FET, the gate electrode layer 136T can include one or more p-type work function metal (p-metal) layers 136T1. The p-type work function metal can illustratively include, but is not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials. In some embodiments, the fill metal 136B2 / 136T2 in the gate electrode layer 136B / 136T can illustratively include, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0193] The gate structure 130 can be formed at a location above a top surface of the buried metal lines BM (e.g., bit lines BL, bit bar lines BLB, and power voltage node V SS The buried metal lines BM (e.g., bit lines BL, bit bar lines BLB, and power voltage node V SS are below a top surface of the gate structure 130.

[0194] Reference is made to ​. A contact 170 is formed over the gate structure 130. A multi-level interconnect (MLI) structure 180 is formed over the contact 170. The multi-level interconnect (MLI) structure 180 can include a plurality of metal layers 182M, metal vias, and one or more dielectric layers 184 that span the metal layers 182M from one another. Via this process, a CFET structure is formed between the buried metal lines BM (e.g., bit lines BL, bit bar lines BLB, and power voltage nodes V SS ) and the metal layers 182M.

[0195] Based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments can provide additional advantages, not all advantages need be disclosed herein, and no particular advantage is required for all embodiments. One advantage is direct stacking of face-to-face (F2F) double-stacked CFET 6T-SRAM. One SRAM cell is flipped and adhered to another SRAM array to share common power and footprint. By mirroring the configuration of the top SRAM array to the bottom SRAM array, the direction of BL / WL propagation can be compensated, thereby shortening the transmission length. Another advantage is that common power (V DD ) is shared by the top SRAM array and the bottom SRAM array, thereby saving footprint. Still another advantage is that transistor density can be increased while avoiding an increase in parasitic capacitance compared to a single-stacked structure. Still another advantage is that delay time is reduced more than the additional resistance caused by the through-layer super vias.

[0196] According to some embodiments of the present disclosure, a stacked integrated circuit (IC) structure (or device) includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first bit line, at least one first static random access memory cell, a first metal layer of a first bonding metal, and at least one first vertical conductive structure, wherein the at least one first static random access memory cell is electrically connected to the first bit line, and the at least one first vertical conductive structure connects the first bit line to a first metal line of the first bonding metal. The second semiconductor structure is above and bonded to the first semiconductor structure. The second semiconductor structure includes a second bit line, at least one second static random access memory cell, a second metal layer of a second bonding metal, at least one second vertical conductive structure, wherein the at least one second static random access memory cell is electrically connected to the second bit line, and the at least one second vertical conductive structure connects the second bit line to a second metal line of the second bonding metal, and the first metal line of the first bonding metal is bonded to the second metal line of the second bonding metal.

[0197] In some embodiments, the first vertical conductive structure is vertically aligned with the second vertical conductive structure.

[0198] In some embodiments, the first semiconductor structure further comprises a first word line electrically connected with the first static random access memory cell and a third vertical conductive structure connecting the first word line to a third metal line of the first bonding metal layer, and the second semiconductor structure further comprises a second word line electrically connected with the second static random access memory cell and a fourth vertical conductive structure connecting the second word line to a fourth metal line of the second bonding metal layer, wherein the third metal line of the first bonding metal layer is bonded with the fourth metal line of the second bonding metal layer.

[0199] In some embodiments, the third vertical conductive structure is vertically aligned with the fourth vertical conductive structure.

[0200] In some embodiments, the first static random access memory cell comprises a plurality of first n-type transistors and a plurality of first p-type transistors stacked over the plurality of first n-type transistors, and the second static random access memory cell comprises a plurality of second n-type transistors and a plurality of second p-type transistors stacked over the plurality of second n-type transistors.

[0201] In some embodiments, the first static random access memory cell comprises a plurality of first transistors between the first bit line and the first bonding metal layer, and the second static random access memory cell comprises a plurality of second transistors between the second bit line and the second bonding metal layer.

[0202] In some embodiments, the first vertical conductive structure is laterally aligned with a plurality of transistors in the first static random access memory cell, and the second vertical conductive structure is laterally aligned with a plurality of transistors in the second static random access memory cell.

[0203] In some embodiments, a plurality of the first static random access memory cells are arranged, and in a top view, two of the plurality of first vertical conductive structures are respectively over two portions of the first bit line on opposite sides of the plurality of arranged first static random access memory cells.

[0204] In some embodiments, a plurality of the second static random access memory cells are arranged, and in a top view, two of the plurality of second vertical conductive structures are respectively over two portions of the second bit line on opposite sides of the plurality of arranged second static random access memory cells.

[0205] According to some embodiments of the present disclosure, a stacked IC structure (or device) includes a plurality of first bit lines, a plurality of first word lines, a first SRAM array including a plurality of first SRAM cells electrically connected to the first bit lines and the first word lines, a plurality of second bit lines, a plurality of second word lines, a second SRAM array stacked above the first SRAM array, a first conductive structure, and a second conductive structure. The second SRAM array includes a plurality of second SRAM cells electrically connected to the second bit lines and the second word lines. In a top view, the first bit lines and the second bit lines extend from a first region on a first side of the first SRAM array and the second SRAM array to a second region on a second side of the first SRAM array and the second SRAM array. The first conductive structure connects the first bit lines to the second bit lines, respectively. The first conductive structure is in the first region in the top view. The second conductive structure connects the first bit lines to the second bit lines, respectively. The second conductive structure is in the second region in the top view.

[0206] In some embodiments, the stacked IC structure further includes a first bit decoder and a second bit decoder. The first bit decoder is connected to the plurality of first bit lines, wherein the first region is between the first bit decoder and the first SRAM array and the second SRAM array in a top view. The second bit decoder is connected to the plurality of second bit lines, wherein the second region is between the second bit decoder and the first SRAM array and the second SRAM array in a top view.

[0207] In some embodiments, the stacked IC structure further includes a plurality of first bit bars electrically connected to the plurality of first SRAM cells, a plurality of second bit bars electrically connected to the plurality of second SRAM cells, wherein the plurality of first bit bars and the plurality of second bit bars extend from the first region to the second region in a top view, a plurality of third conductive structures connecting the plurality of first bit bars to the plurality of second bit bars, respectively, wherein the plurality of third conductive structures are in the first region in the top view, and a plurality of fourth conductive structures connecting the plurality of first bit bars to the plurality of second bit bars, respectively, wherein the plurality of fourth conductive structures are in the second region in the top view.

[0208] In some embodiments, the stacked IC structure further includes a plurality of fifth conductive structures connecting the plurality of first word lines to the plurality of second word lines, respectively, wherein the plurality of fifth conductive structures are in the first region and the second region in a top view.

[0209] In some embodiments, a height of the first conductive structures is greater than a height of the fifth conductive structures.

[0210] In some embodiments, the stacked integrated circuit structure further comprises a first word line decoder and a second word line decoder. The first word line decoder is connected to the first word lines. The second word line decoder is connected to the second word lines, wherein the first and second word line decoders are on opposite sides of the first and second SRAM arrays in a top view.

[0211] According to some embodiments of the present disclosure, a method for fabricating a stacked IC structure (or device) is provided. The method includes forming first bit lines over a first substrate; forming a plurality of first transistors over the first substrate, the plurality of first transistors constituting a plurality of first functional units over the first substrate, wherein a top surface of the first bit lines is below a top surface of a gate structure of the first transistors; forming a first bonding metal layer over the first transistors, wherein the first bonding metal layer includes a first metal line electrically connected to the first bit lines; forming second bit lines over a second substrate; forming a plurality of second transistors over the second substrate, the plurality of second transistors constituting a plurality of second functional units over the second substrate, wherein a top surface of the second bit lines is below a top surface of a gate structure of the second transistors; forming a second bonding metal layer over the second transistors, wherein the second bonding metal layer includes a second metal line electrically connected to the second bit lines; and bonding the first substrate and the second substrate such that the first metal line and the second metal line are in contact.

[0212] In some embodiments, the method further includes forming a first vertical conductive structure over the first bit lines, wherein forming the first bonding metal layer is performed such that the first metal line is in contact with the first vertical conductive structure; and forming a second vertical conductive structure over the second bit lines, wherein forming the second bonding metal layer is performed such that the second metal line is in contact with the second vertical conductive structure.

[0213] In some embodiments, bonding the first substrate and the second substrate is performed such that the first vertical conductive structure and the second vertical conductive structure are aligned.

[0214] In some embodiments, the method further includes forming a first word line over the first substrate, wherein forming the first bonding metal layer is performed such that the first bonding metal layer includes a third metal line electrically connected to the first word line; and forming a second word line over the second substrate, wherein forming the second bonding metal layer is performed such that the second bonding metal includes a fourth metal line electrically connected to the second word line, wherein bonding the first substrate and the second substrate is performed such that the third metal line and the fourth metal line are in contact.

[0215] In some embodiments, forming the plurality of first transistors includes forming a first channel layer and a second channel layer over and spaced apart from the first channel layer; forming a first epitaxial structure on a side of the first channel layer; and forming a second epitaxial structure on a side of the second channel layer, wherein the first epitaxial structure and the second epitaxial structure comprise opposite conductivity types.

[0216] According to some embodiments of the present disclosure, a stacked integrated circuit structure includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first bit line, a plurality of first transistors, and a first metal layer. The first transistors form a plurality of first functional units. The first metal layer includes a first metal line electrically connected to the first bit line, the first transistors being between the first bit line and the first metal layer. The second semiconductor structure includes a second bit line, a plurality of second transistors, and a second metal layer. The plurality of second transistors form a plurality of second functional units. The second metal layer includes a second metal line electrically connected to the second bit line. The first semiconductor structure is bonded to the second semiconductor structure, the first metal line and the second metal line being in contact.

[0217] In some embodiments, the first semiconductor structure further includes a first vertical conductive structure and a second vertical conductive structure. The first vertical conductive structure connects the first bit line to the first metal line. The second vertical conductive structure connects the second bit line to the first metal line.

[0218] The foregoing outlines features of several embodiments so that a thorough comprehension of the present disclosure can be attained. Those of ordinary skill in the art, however, should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein without departing from the spirit and scope of the present disclosure. Those of ordinary skill in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A stacked integrated circuit structure, comprising: comprises a first bit line, at least one first static random access memory cell, a first bonding metal layer, and at least one first vertical conductive structure, wherein the at least one first static random access memory cell is electrically connected to the first bit line, the at least one first vertical conductive structure connects the first bit line to a first metal line of the first bonding metal layer; and a second semiconductor structure above and bonded to the first semiconductor structure, wherein the second semiconductor structure comprises a second bit line, at least one second static random access memory cell, a second bonding metal layer, at least one second vertical conductive structure, wherein the at least one second static random access memory cell is electrically connected to the second bit line, the at least one second vertical conductive structure connects the second bit line to a second metal line of the second bonding metal layer, the first metal line of the first bonding metal layer is bonded to the second metal line of the second bonding metal layer. wherein the first vertical conductive structure is vertically aligned with the second vertical conductive structure. wherein the first semiconductor structure further comprises a first word line electrically connected to the first static random access memory cell and a third vertical conductive structure connecting the first word line to a third metal line of the first bonding metal layer, and the second semiconductor structure further comprises a second word line electrically connected to the second static random access memory cell and a fourth vertical conductive structure connecting the second word line to a fourth metal line of the second bonding metal layer, wherein the third metal line of the first bonding metal layer is bonded to the fourth metal line of the second bonding metal layer.

2. The stacked integrated circuit structure of claim 1, wherein, wherein the third vertical conductive structure is vertically aligned with the fourth vertical conductive structure.

3. The stacked integrated circuit structure of claim 1, wherein, wherein the first static random access memory cell comprises a plurality of first n-type transistors and a plurality of first p-type transistors stacked above the plurality of first n-type transistors, and the second static random access memory cell comprises a plurality of second n-type transistors and a plurality of second p-type transistors stacked above the plurality of second n-type transistors.

4. The stacked integrated circuit structure of claim 3, wherein, comprises a plurality of first bit lines; 5. The stacked integrated circuit structure of any one of claims 1 to 4, wherein, a plurality of first word lines; 6. A stacked integrated circuit structure, comprising: a first static random access memory array comprising a plurality of first static random access memory cells electrically connected to the plurality of first bit lines and the plurality of first word lines; a plurality of second bit lines; a plurality of second word lines; ​ ​ ​ a second static random access memory array stacked on the first static random access memory array, wherein the second static random access memory array includes a plurality of second static random access memory cells electrically connected to a plurality of second bit lines and a plurality of second word lines, wherein in a top view, the plurality of first bit lines and the plurality of second bit lines extend from a first region on a first side of the first static random access memory array and the second static random access memory array to a second region on a second side of the first static random access memory array and the second static random access memory array; a plurality of first conductive structures respectively connecting the plurality of first bit lines to the plurality of second bit lines, wherein the plurality of first conductive structures are in the first region in a top view; and a plurality of second conductive structures respectively connecting the plurality of first bit lines to the plurality of second bit lines, wherein the plurality of second conductive structures are in the second region in a top view.

7. The stacked integrated circuit structure of claim 6, wherein, Further comprising: a first bit decoder connected to the plurality of first bit lines, wherein in a top view, the first region is between the first bit decoder and the first static random access memory array and the second static random access memory array; and a second bit decoder connected to the plurality of second bit lines, wherein in a top view, the second region is between the second bit decoder and the first static random access memory array and the second static random access memory array.

8. The stacked integrated circuit structure of claim 6 or 7, wherein, Further comprising: a plurality of first bit bars electrically connected to the plurality of first static random access memory cells; a plurality of second bit bars electrically connected to the plurality of second static random access memory cells, wherein in a top view, the plurality of first bit bars and the plurality of second bit bars extend from the first region to the second region; a plurality of third conductive structures respectively connecting the plurality of first bit bars to the plurality of second bit bars, wherein in a top view the plurality of third conductive structures are in the first region; and a plurality of fourth conductive structures respectively connecting the plurality of first bit bars to the plurality of second bit bars, wherein the plurality of fourth conductive structures are in the second region in a top view.

9. A stacked integrated circuit structure, comprising: Comprising: a first semiconductor structure comprising: a first bit line; a plurality of first transistors forming a plurality of first functional units; and a first via metal layer, wherein the first via metal layer includes a first metal line electrically connected to the first bit line, the plurality of first transistors being between the first bit line and the first via metal layer; and a second semiconductor structure comprising: a second bit line; a plurality of second transistors forming a plurality of second functional units; and a second via metal layer, wherein the second via metal layer includes a second metal line electrically connected to the second bit line, the plurality of second transistors being between the second bit line and the second via metal layer, wherein the first semiconductor structure is bonded to the second semiconductor structure, the first metal line contacting the second metal line.

10. The stacked integrated circuit structure of claim 9, wherein, The first semiconductor structure further comprises a first vertical conductive structure connecting the first bit line to the first metal line, and the second semiconductor structure further comprises a second vertical conductive structure connecting the second bit line to the second metal line.

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