LED packaging structure and backlight plate
By integrating a control chip into the LED packaging structure, the problems of thick packaging structures and poor light mixing effects in existing technologies are solved, achieving the effects of thinness and uniform light output.
Patent Information
- Application Number
- CN202422382810.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-11-28
- Estimated Expiration
- 2034-09-29
AI Technical Summary
Existing LED backlight panels suffer from problems such as thick packaging structure, poor light mixing effect and unclear bright-dark boundary, and the control chip needs to be packaged separately, taking up space.
The LED packaging structure with integrated control chip integrates the control chip and LED chip by setting walls and sealing points on the substrate. The sealing points reflect the emitted light from the surrounding LED chips to achieve uniform light output. At the same time, the overlap structure and height of the sealing points and walls are reasonably set to separate the light in the pixel area.
It achieves a thinner and smaller LED packaging structure while ensuring uniform light output and light mixing effect, avoiding the problem of unclear bright and dark boundaries.
Smart Images
Figure CN223613771U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] At least one embodiment of the present application relates to a specially designed LED packaging structure, and also relates to a backlight panel. BACKGROUND
[0002] The existing LED backlight panel is generally formed by electrically connecting the LED packaging structure, the control chip and the power driver respectively, the control chip needs to be packaged separately, and occupies space, so that the package is large and thick. At the same time, the LED packaging structure of the existing backlight panel is thick itself, and the light mixing effect is poor, and the boundary of bright and dark is not clear, and the edge of the backlight source has a bright line problem. CONTENT OF THE INVENTION
[0003] Embodiments of the present application provide an LED packaging structure with uniform light output and integrated control chip, which can realize direct internal single-chip control and avoid light mixing problems.
[0004] In order to achieve the above purpose, the present application provides the following technical scheme:
[0005] An LED packaging structure comprises:
[0006] A substrate having opposite first and second surfaces; a circuit layer is arranged on the first surface of the substrate;
[0007] A fence is arranged on the first surface and comprises a plurality of horizontal walls extending in a first direction and a plurality of vertical walls extending in a second direction, the first direction and the second direction are orthogonal, and the plurality of horizontal walls and the plurality of vertical walls intersect to form a plurality of pixel regions;
[0008] A plurality of control chips are arranged on the first surface and located at the intersection points of the horizontal walls and the vertical walls, and the plurality of control chips are electrically connected to the circuit layer;
[0009] A plurality of sealing points are arranged to seal the plurality of control chips respectively;
[0010] A plurality of LED chips are arranged on the first surface and located in the plurality of pixel regions, and the plurality of LED chips are electrically connected to the circuit layer;
[0011] A sealing layer is arranged on the first surface and covers at least a part of the plurality of LED chips, the fence and the plurality of sealing points.
[0012] In the embodiments of the present application, the plurality of horizontal walls comprises a plurality of first horizontal walls provided with the control chip and a plurality of second horizontal walls not provided with the control chip; along the second direction, the plurality of first horizontal walls are arranged at least with one second horizontal wall in between; the circuit layer comprises a plurality of first test points, and the plurality of first test points on both sides of each first horizontal wall are symmetrically arranged with the first horizontal wall as the axis of symmetry.
[0013] In the embodiments of the present application, the distance between each pair of symmetrically arranged first test points on both sides of the first horizontal wall is not all the same.
[0014] In the embodiments of the present application, the plurality of first test points are arranged in the pixel area, and each pixel area comprises at most two first test points; and among the plurality of pixel areas on both sides of the first horizontal wall, some pixel areas have two first test points, some pixel areas have one first test point, and some pixel areas are not provided with a first test point.
[0015] In the embodiments of the present application, the height of the sealing point is greater than the height of the enclosing wall; the horizontal wall and the vertical wall are broken at the sealing point and each has an end head portion at the sealing point, and the end head portion is lapped on the sealing point.
[0016] In the embodiments of the present application, the ratio of the height of the sealing point to the thickness of the enclosing wall is 2-4, and the height of the sealing point is 0.4-0.8 mm.
[0017] In the embodiments of the present application, the sealing point is semispherical, and the top thereof is exposed from the top surface of the sealing layer.
[0018] In the embodiments of the present application, at the intersection of the horizontal wall and the vertical wall, the vertical wall is arranged above the horizontal wall.
[0019] In the embodiments of the present application, four LED chips are arranged in each pixel area, and the connection line of the center points of the LED chips is a rectangle or a parallelogram.
[0020] The present application also provides a backlight plate comprising at least one LED packaging structure as described above.
[0021] The present application integrates the control chip and the LED chip to ensure the thinness and small volume of the LED packaging structure, and simultaneously seals the control chip with a sealing point for reflecting the light emitted by the peripheral LED chips, so as to realize more uniform light emission. Meanwhile, the lapping structure and height of the sealing point and the enclosing wall are reasonably arranged to ensure that the enclosing wall can separate the light of the plurality of pixel areas from each other, and simultaneously realize the light scattering of the sealing point and the enclosing wall. BRIEF DESCRIPTION OF DRAWINGS
[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only represent some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative effort based on these drawings.
[0023] Figure 1 is a top view of the LED packaging structure of the present application;
[0024] Figure 2 is an enlarged view of the A area of Figure 1
[0025] Figure 3 is a cross-sectional view of the C1C2 line of Figure 2
[0026] Figure 4 is a cross-sectional view of the D1D2 line of Figure 2
[0027] Figure 5 is an arrangement pattern of LED chips in a single pixel area of the present application.
[0028] Explanation of reference signs:
[0029] 1, substrate; 2, circuit layer; 3, wall; 4, pixel area; 5, LED chip; 6, terminal part; 7, control chip; 8, sealing point; 9, sealing layer. DETAILED DESCRIPTION
[0030] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and embodiments, by which the implementation process of how the present application applies technical means to solve technical problems and achieves corresponding technical effects can be fully understood and implemented. The embodiments of the present application and each feature in the embodiments can be combined with each other without conflict, and the technical solutions formed thereby are all within the protection scope of the present application. In the accompanying drawings, the sizes and relative sizes of layers and regions can be exaggerated for clarity. The same reference signs represent the same elements throughout.
[0031] It should be understood that although the terms "first", "second", "third" and the like can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part without departing from the teachings of the present application.
[0032] It will be understood that the spatially relative terms "above", "below", "up", "down", and like terms, are intended to be interpreted as referenced with respect to the orientation of the device as shown in the drawings and are used merely for convenience. For example, if the device in the drawings were turned over, then the descriptions "above" and "below" can be interpreted as taking the opposite orientation.
[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0034] The embodiments of the present application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. The cross-sectional illustrations are schematic illustrations of idealized embodiments and intermediate structures during the manufacturing of embodiments of the present application.
[0035] For a thorough understanding of the present application, reference should be made to the following detailed description, in conjunction with the accompanying drawings, in which:
[0036] The LED package structure provided by the present application is shown in Figure 1 The LED package structure provided by the present application is shown in
[0037] The circuit layer 2 can be a single layer metal layer structure, or a double layer structure including a seed layer and a metal layer, or a more layer structure, for example, including a barrier layer. The thickness of the circuit layer 2 can be 50-300 microns. There is also a connecting area near one edge of the first surface of the substrate 1, and an external connecting terminal part 6 is arranged on the connecting area, which can be embedded into a power driving module or a screen module by insertion. The panel area is arranged at other positions except the connecting area.
[0038] A fence 3 is arranged on the first surface of the substrate 1, which is formed by a dispensing process or a printing process, and the fence 3 is a light-cured or heat-cured resin material. The fence 3 is a grid structure, which includes a plurality of horizontal walls extending in a horizontal direction Figure 1 in the first surface and a plurality of vertical walls extending in a vertical direction Figure 1 , the first direction and the second direction are orthogonal, and the plurality of horizontal walls and the plurality of vertical walls intersect to form a plurality of pixel areas 4. At the intersection of the horizontal wall and the vertical wall, the vertical wall is arranged above the horizontal wall.
[0039] As shown in Figure 1 and Figure 2 , the pixel area 4 is a rectangular frame structure, and each pixel area 4 has four LED chips 5, which are all electrically connected to the circuit layer 2. The four LED chips 5 can all be white LED package chips, or one blue LED bare chip, one green LED bare chip, one red LED bare chip and one white LED chip, or one blue LED bare chip, one green LED bare chip and two red LED bare chips. Of course, each pixel area 4 can have only three LED chips, for example, including one blue LED bare chip, one green LED bare chip and one red LED bare chip.
[0040] As shown in Figure 5 , the connecting line of the center points of the four LED chips 5 is a rectangle or a parallelogram. Preferably, the connecting line of the center points of the four LED chips 5 is a parallelogram, so that the light mixing effect can be balanced in the case that the red LED chip is weak.
[0041] Referring to Figures 1-3 , a plurality of control chips 7 are also arranged on the first surface, each of which is electrically connected to the circuit layer 2 and electrically interconnected with the surrounding LED chips 5 through the circuit layer 2, so as to realize the control of the surrounding LED chips 5 by the control chip 7. The control chip 7 is arranged on the first surface and located at the intersection point position of the intersection of the horizontal wall and the vertical wall.
[0042] The plurality of control chips 7 are respectively sealed by a plurality of sealing points 8 in one-to-one correspondence. The sealing points 8 are light-cured or heat-cured resin materials which are the same as the material of the enclosing wall 3. The sealing points 8 are in an arched or hemispherical structure, and the position and shape of the sealing points 8 are arranged so that the LED chips in the four pixel areas 4 on the periphery are reflected by the sealing points 8, so that the light emission is more uniform. The sealing points 8 are generally circular in shape when viewed from above, and the diameter of the circular shape is greater than the width of the horizontal wall and the vertical wall.
[0043] In particular, the height of the sealing point 8 is greater than the height of the enclosing wall 3, and the enclosing wall 3 and the sealing point 8 have an overlapping portion, i.e., see Figure 3 , the horizontal wall and the vertical wall are broken at the sealing point 8 and each have an end portion at the sealing point 8, which overlaps the sealing point 8. Moreover, the height of the end portion position is also lower than the height of the sealing point 8.
[0044] Preferably, the ratio of the height of the sealing point 8 to the thickness (i.e., height) of the enclosing wall 3 is 2-4. This height ratio can make the enclosing wall 3 separate the light interference between adjacent pixel areas 4, and the light emission at a higher position of the enclosing wall 3 can be effectively reflected by the sealing point 3 to ensure the uniformity of the light emission. The height of the sealing point 8 is 0.4-0.8 mm, for example, it can be 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm; the height of the enclosing wall 3 is 0.2-0.3 mm, for example, it can be 0.2 mm, 0.22 mm, 0.25 mm, 0.28 mm, 0.3 mm.
[0045] Further, the height of the LED chip 5 can be 0.1-0.2 mm, for example, it can be 0.1 mm, 0.15 mm, 0.2 mm, and the height of the LED chip 5 is less than or equal to the height of the enclosing wall 3; the height of the control chip 7 is 0.2-0.4 mm, for example, it can be 0.2 mm, 0.25 mm, 0.3 mm, 0.35 mm, 0.4 mm, and the height of the control chip 7 is greater than the height of the enclosing wall 3.
[0046] Further, the LED packaging structure further comprises a sealing layer 9 disposed on the first surface, the sealing layer 9 has a water vapor prevention function and is formed of a heat-cured or light-cured resin material. The sealing layer 9 covers a plurality of the LED chips 5, the enclosing wall 3, and a part of the plurality of the sealing points 8. See Figure 4 , the sealing layer 9 exposes the top of the sealing point 8, so that the sealing effect can be ensured while achieving close engagement with the sealing point 8, and the optimization of the reflection effect is ensured. Preferably, the exposed part of the sealing point 8 accounts for 5%-15% of the total surface area of the sealing point 8.
[0047] The first test points 10 are arranged on both sides of the first horizontal walls, and are symmetrically arranged with the first horizontal walls as the symmetric axis. Further, the horizontal walls 3 include first horizontal walls provided with the control chips 7 and second horizontal walls not provided with the control chips 7; along the second direction, the first horizontal walls are arranged at intervals of at least one (preferably one) second horizontal wall. Figure 2 The first test points 10 are arranged on both sides of the first horizontal walls, and are symmetrically arranged with the first horizontal walls as the symmetric axis. Further, the horizontal walls 3 include first horizontal walls provided with the control chips 7 and second horizontal walls not provided with the control chips 7; along the second direction, the first horizontal walls are arranged at intervals of at least one (preferably one) second horizontal wall.
[0048] The distance between each pair of symmetrically arranged first test points 10 on both sides of the first horizontal walls is not the same. Such arrangement can easily distinguish which LED chip each first test point 10 is testing, and can shorten the circuit path between the test points and the LED chips 5. The first test points 10 are arranged in the pixel area 4, and each pixel area 4 includes at most two first test points 10; among the pixel areas 4 on both sides of the first horizontal walls, some pixel areas 4 have two first test points 10, some pixel areas 4 have one first test point 10, and some pixel areas are not provided with first test points 10. Such arrangement can prevent the first test points 10 from being too dense, and thus can improve the accuracy of the test.
[0049] Further, a plurality of second test points are arranged on one side of the second horizontal walls, and are arranged in the middle of the areas surrounded by the four control chips 7.
[0050] The application also discloses a backlight plate comprising the above LED packaging structure, or composed of a plurality of LED packaging structures.
[0051] The above is merely specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any changes or replacements within the technical scope disclosed by the present application can be easily thought of by those skilled in the art, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. An LED package structure, comprising: a substrate having opposite first and second surfaces; a circuit layer disposed on the first surface of the substrate; a fence disposed on the first surface and comprising a plurality of horizontal walls extending in a first direction and a plurality of vertical walls extending in a second direction, the first and second directions being orthogonal, and the plurality of horizontal walls and the plurality of vertical walls intersecting to enclose a plurality of pixel regions; a plurality of control chips disposed on the first surface at intersection positions of the horizontal walls and the vertical walls, the plurality of control chips being electrically connected to the circuit layer; a plurality of sealing points each sealing a control chip; a plurality of LED chips disposed on the first surface within the plurality of pixel regions, the plurality of LED chips being electrically connected to the circuit layer; a sealing layer disposed on the first surface and covering at least the plurality of LED chips, the fence, and a portion of the plurality of sealing points. 2.The LED package structure of claim 1, wherein: the plurality of horizontal walls comprises a plurality of first horizontal walls each having a control chip disposed thereon and a plurality of second horizontal walls each not having a control chip disposed thereon; in the second direction, the plurality of first horizontal walls are disposed at least one second horizontal wall apart; and the circuit layer comprises a plurality of first test points, the plurality of first test points on each side of the first horizontal walls being symmetrically disposed about the first horizontal wall as a symmetry axis. 3.The LED package structure of claim 2, wherein: distances between each pair of symmetrically disposed first test points on opposite sides of the first horizontal wall are not all the same. 4.The LED package structure of claim 2, wherein: the plurality of first test points are disposed within the pixel regions, and each of the pixel regions includes at most two first test points; and of the plurality of pixel regions on opposite sides of the first horizontal wall, some pixel regions have two first test points, some pixel regions have one first test point, and some pixel regions have no first test point disposed thereon. 5.The LED package structure of claim 1, wherein: a height of the sealing points is greater than a height of the fence; the horizontal walls and the vertical walls are broken at the sealing points and each have an end portion at the sealing point, the end portion being lapped on the sealing point. 6.The LED package structure of claim 1, wherein: a ratio of the height of the sealing points to a thickness of the fence is 2-4, and the height of the sealing points is 0.4-0.8 mm. 7.The LED package structure of claim 1, wherein: the sealing points are hemispherical, and a top portion of each of the sealing points is exposed from a top surface of the sealing layer. 8.The LED package structure of claim 1, wherein: at intersections of the horizontal walls and the vertical walls, the vertical walls are disposed on the horizontal walls. 9.The LED package structure of any one of claims 1-8, wherein: Four LED chips are arranged in each pixel region, and the connecting lines of the center points of the LED chips are in the shape of a rectangle or a parallelogram.
10. A backlight panel comprising the LED package structure according to any one of claims 1-9.