Test seat for QFN chip

Abstract

The utility model belongs to the technical field of QFN chip test application, and particularly discloses a test seat for a QFN chip, which comprises an upper pin mounting plate, a lower pin mounting plate, a groove, a plurality of first pin holes, a plurality of second pin holes, a chip guide frame, a chip placement through groove, two groups of first screw holes, two groups of second screw holes, two groups of third screw holes, screws and the like. The beneficial effects of the testing seat used for the QFN chip are that 1, the whole body is a split combined type reasonable design, the manufacturing cost is low, the assembling, the use, the disassembly and the maintenance are convenient, the operation is convenient, the detection efficiency is improved, and the popularization is facilitated; and 2, when in use, the whole structure is mounted on a tested circuit board frame through the bolt through holes by using bolts, screw pads, nuts and cover-type nuts which are matched for use, and the assembly and the use are convenient.

Description

Technical Field

[0001] This utility model belongs to the field of QFN chip testing application technology, specifically relating to a test socket for QFN chips. Background Technology

[0002] QFN is a leadless package that is square or rectangular in shape. There is a large exposed pad at the center of the bottom of the package for heat conduction, and conductive pads around the perimeter of the package for electrical connection.

[0003] Chip manufacturing involves several stages, including chip design, wafer fabrication, packaging, and testing. Chip testing essentially involves evaluating the chip's performance, reliability, and other key data to obtain crucial information for improving chip manufacturing and increasing yield.

[0004] Currently, test sockets used for QFN chips suffer from problems such as complex structure, high manufacturing and usage costs, and inconvenience in disassembly and maintenance.

[0005] To address the aforementioned issues, this invention provides a QFN chip test socket with heat dissipation function. Utility Model Content

[0006] Purpose of the utility model: The purpose of this utility model is to address the shortcomings of the existing technology by providing a QFN chip test socket, which solves the problems existing in the background technology, namely, the overall design is simple and reasonable, easy to assemble / disassemble and maintain, low manufacturing and use costs, and reduces testing cost investment.

[0007] Technical Solution: This utility model provides a QFN chip test socket, including an upper pin plate, a lower pin plate, test probes, and a chip to be tested. One side of the upper pin plate has a groove, and a plurality of first pin holes are provided on one side of the upper pin plate within the groove. The lower pin plate has a plurality of second pin holes that match the first pin holes. A chip guide frame is mounted on one side of the upper pin plate via the groove, and a chip placement slot is provided within the chip guide frame. Two sets of first screw holes are provided on one side of the upper pin plate outside the plurality of first pin holes. Two sets of second screw holes are provided on the lower pin plate outside the plurality of second pin holes. Two sets of third screw holes are provided on the chip guide frame outside the chip placement slot. The upper pin plate, lower pin plate, and chip guide frame are fixed together by screws through the two sets of first screw holes, two sets of second screw holes, and two sets of third screw holes.

[0008] The QFN chip test socket of this technical solution further includes bolt through holes set in the four corners of the upper needle plate, bolts used to cooperate with the bolt through holes, and washers, nuts and cap nuts used to cooperate with the bolts respectively.

[0009] In this technical solution, the connecting surfaces of the groove and the chip guide frame are set as matching polygons.

[0010] Compared with the prior art, the advantages of this utility model for a QFN chip test socket are as follows: 1. The overall design is a modular assembly, which is reasonable, has low manufacturing cost, is easy to assemble, use and disassemble, and is easy to operate, improving testing efficiency and facilitating promotion; 2. When in use, the overall structure is installed on the test circuit board frame through the bolt through holes using matching bolts, washers, nuts and cap nuts, which is convenient to assemble and use. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is an exploded view of an exploded structure of a QFN chip test socket according to this utility model;

[0013] The numbers in the diagram are as follows: 1-Upper needle plate, 2-Lower needle plate, 3-Chip guide frame, 4-Test probe, 5-Chip under test, 6-Bolt, 7-Screw, 8-Washer, 9-Nut, 10-Cap nut, 101-Groove, 102-First pin hole, 103-First screw hole, 104-Bolt through hole, 201-Second pin hole, 202-Second screw hole, 301-Through groove, 302-Third screw hole. Detailed Implementation

[0014] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the protection scope of the present utility model.

[0015] In the description of this utility model, it should be noted that the terms "top," "bottom," "one side," "the other side," "front," "back," "middle part," "inner," "top," and "bottom," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this utility model and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, unless otherwise explicitly specified and limited, the terms "installed," "connected," and "joined" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0016] Example 1

[0017] like Figure 1 The QFN chip test socket shown includes an upper probe plate 1, a lower probe plate 2, test probes 4, and a chip under test 5.

[0018] A groove 101 is provided on one side of the upper loading needle plate 1.

[0019] One side of the upper needle plate 1, and located within the groove 101, is provided with a plurality of first needle insertion holes 102.

[0020] The lower needle plate 2 is provided with a number of second needle holes 201 that are matched with the first needle hole 102.

[0021] A chip guide frame 3 is mounted on one side of the upper loading needle plate 1 via a groove 101.

[0022] The chip guide frame 3 is provided with a chip placement slot 301.

[0023] Two sets of first screw holes 103 are provided on one side of the upper needle plate 1, and on the outer layer of a plurality of first needle insertion holes 102.

[0024] Inside the lower needle plate 2, and on the outer layer of several second needle insertion holes 201, are two sets of second screw holes 202.

[0025] Two sets of third screw holes 302 are provided inside the chip guide frame 3 and on the outer layer of the chip placement slot 301.

[0026] The upper needle plate 1, the lower needle plate 2, and the chip guide frame 3 are fixed together by screws 7 through two sets of first screw holes 103, two sets of second screw holes 202, and two sets of third screw holes 302.

[0027] The working principle is as follows: Insert the upper pin plate 1 and the lower pin plate 2 into the first pin hole 102 and the second pin hole 201, then place the chip to be tested 7 horizontally in the chip placement slot 301, and finally place the chip guide frame 3 horizontally in the upper pin plate 1 through the groove 101. At this time, one end of the test probe 6 contacts the solder ball pin of the chip to be tested 7, and the other end contacts the PAD on the PCB to perform power-on testing.

[0028] Example 2

[0029] Based on Embodiment 1, the QFN chip test socket also includes bolt through holes 104 disposed in the four corners of the upper needle plate 1, bolts 6 used in conjunction with the bolt through holes 104, and washer 8, nut 9 and cap nut 10 used in conjunction with the bolts 6 respectively.

[0030] The above design structure allows for rapid assembly and use of the entire assembly with the test circuit board frame via bolt through holes 104 using bolts 6, washers 8, nuts 9, and cap nuts 10.

[0031] In addition, preferably the connecting surfaces of the groove 101 and the chip guide frame 3 are set as matching polygons to prevent the chip guide frame 3 from sliding horizontally during use, which would affect the accuracy of the test and damage the test probe 4 and the chip under test 5.

[0032] It should be noted that, in this document, terms such as "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0033] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A test socket for QFN chips, comprising an upper probe plate (1), a lower probe plate (2), test probes (4), and a chip under test (5), characterized in that: The upper needle plate (1) has a groove (101) on one side. One side of the upper needle plate (1) is provided with a plurality of first needle insertion holes (102) located in the groove (101). The lower needle plate (2) is provided with a plurality of second needle holes (201) that are matched with the first needle hole (102). A chip guide frame (3) is mounted in a groove (101) on one side of the upper mounting plate (1). The chip guide frame (3) is provided with a chip placement slot (301). On one side of the upper needle plate (1), and on the outer layer of a plurality of first needle insertion holes (102), two sets of first screw holes (103) are provided. The lower needle plate (2) is provided with two sets of second screw holes (202) on the outer layer of several second needle insertion holes (201). Two sets of third screw holes (302) are provided inside the chip guide frame (3) and on the outer layer of the chip placement slot (301). The upper needle plate (1), lower needle plate (2), and chip guide frame (3) are fixed together by screws (7) through two sets of first screw holes (103), two sets of second screw holes (202), and two sets of third screw holes (302).

2. A test socket for QFN chips according to claim 1, characterized in that: The QFN chip test socket also includes bolt through holes (104) set in the four corners of the upper needle plate (1), bolts (6) used in conjunction with the bolt through holes (104), and washer (8), nut (9) and cap nut (10) used in conjunction with the bolts (6).

3. A test socket for QFN chips according to claim 1, characterized in that: The connection surfaces of the groove (101) and the chip guide frame (3) are set as matching polygons.

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