Embedded chip packaging structure and electronic equipment

Abstract

The utility model relates to the technical field of semiconductors, and discloses an embedded chip packaging structure and electronic equipment, the packaging structure comprises a printed circuit board, a substrate, and a control chip and a storage chip arranged on the substrate; the substrate is connected with the printed circuit board through the solder balls; a first solder ball array is arranged below the first area of the substrate; wherein the first area is an area where the control chip is located in the substrate and the periphery of the area where the control chip is located; a second solder ball array is arranged below the second area of the substrate; wherein the second area is an area where the storage chip is located in the substrate and the periphery of the area where the storage chip is located; the area where the first solder ball array is located needs to cover the area, on the substrate, of the control chip. According to the invention, the heat dissipation capability of the embedded chip can be enhanced, and the thermal resistance value of the embedded chip can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an embedded chip packaging structure and electronic device. Background Technology

[0002] With the development of semiconductor technology, memory chips are becoming smaller while their capacities are increasing. However, this trend leads to increased power consumption, which in turn causes temperature issues. Currently, embedded products typically use a controller plus flash memory storage model. In these embedded products, the solder ball distribution of the chips is usually designed according to fixed standards (such as...). Figure 1 As shown in the figure, this distribution of solder balls results in poor heat dissipation of the controller components, which in turn affects the overall thermal resistance of the chip. Utility Model Content

[0003] In view of this, embodiments of this application provide an embedded chip packaging structure and electronic device, which can effectively solve the heat dissipation problem of embedded chips and reduce the thermal resistance of embedded chips.

[0004] In a first aspect, embodiments of this application provide an embedded chip packaging structure, including: a printed circuit board, a substrate, and a control chip and a memory chip disposed on the substrate;

[0005] The substrate is connected to the printed circuit board via solder balls;

[0006] A first solder ball array is disposed below a first region of the substrate; wherein, the first region is the region where the control chip is located in the substrate and the area surrounding the region where the control chip is located;

[0007] A second array of solder balls is disposed below a second region of the substrate; wherein, the second region is the region where the memory chip is located in the substrate and the area surrounding the region where the memory chip is located;

[0008] The area where the first solder ball array is located needs to cover the area of ​​the control chip on the substrate.

[0009] In some embodiments, all the solder balls in the first solder ball array are arranged in the first region with the control chip as the center, according to a first preset spacing rule;

[0010] All the solder balls in the second solder ball array are arranged in the second region according to the second preset spacing rule.

[0011] In some embodiments, the total number of solder balls is 153; the number of solder balls in the first solder ball array ranges from 50 to 80.

[0012] In some embodiments, the number of solder balls in the first solder ball array is 66.

[0013] In some embodiments, the first preset spacing rule includes a first horizontal spacing and a first vertical spacing;

[0014] The first lateral spacing ranges from 0.4mm to 0.6mm;

[0015] The first longitudinal spacing ranges from 0.4mm to 0.6mm.

[0016] In some embodiments, the second preset spacing rule includes a second horizontal spacing and a second vertical spacing;

[0017] The second lateral spacing ranges from 0.6mm to 1.0mm;

[0018] The second longitudinal spacing ranges from 0.6mm to 1.0mm.

[0019] In some embodiments, the first lateral spacing is 0.5 mm; the first longitudinal spacing is 0.5 mm;

[0020] The second horizontal spacing is 0.7 mm; the second vertical spacing is 1.0 mm.

[0021] In some embodiments, the second solder ball array is disposed on the side of the second region closer to the first region.

[0022] In some embodiments, the solder balls in the first solder ball array, except for those in the outermost row and column, are arranged in complete rows and columns.

[0023] Except for the solder balls in the outermost row and column, the solder balls in the second solder ball array are arranged in complete rows and columns.

[0024] Secondly, embodiments of this application provide an electronic device, which includes the aforementioned embedded chip packaging structure.

[0025] The embodiments of this application have the following beneficial effects: By dividing all the solder balls into two parts, the solder balls of the first solder ball array are arranged in the first region, and the solder balls of the second solder ball array are arranged in the second region. Since the control component is small in size, has a large heat flux density, and a greater temperature pressure, this method of the application can increase the number of solder balls in the control component region, thereby enhancing the heat dissipation of the control component region and reducing the thermal resistance of the chip. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This diagram illustrates the arrangement of solder balls in the prior art.

[0028] Figure 2 A schematic diagram of the embedded chip packaging structure according to an embodiment of this application is shown;

[0029] Figure 3 This paper shows a schematic diagram of the first arrangement of solder balls in the embedded chip packaging structure according to an embodiment of the present application;

[0030] Figure 4 A schematic diagram of the second arrangement of solder balls in the embedded chip package structure of this application embodiment is shown.

[0031] Explanation of key component symbols:

[0032] 10 - Memory chip; 20 - Control chip; 30 - Solder ball; 40 - First solder ball array; 50 - Second solder ball array; 60 - Substrate; 70 - Printed circuit board. Detailed Implementation

[0033] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0034] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0035] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0036] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0037] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0038] Currently, embedded storage devices use a controller plus flash memory storage model. Their solder ball distribution is designed according to specified standards, without fully considering heat dissipation. Since most of the chip's heat is transferred from the core in both vertical and horizontal directions, under natural heat dissipation without additional cooling measures, and because the upper casing is in contact with air with relatively high thermal resistance, most of the chip's heat flows towards the solder balls, which have lower thermal resistance. The heat is then transferred to the PCB (Printed Circuit Board) via the solder balls, and then dissipated into the air through convection and radiation within the PCB. Therefore, the distribution of the solder balls has a significant impact on temperature.

[0039] like Figure 1 As shown, the embedded storage device includes a control chip 20 and a storage chip 10, which typically includes 153 solder balls 30, such as EMMC (Embedded MultiMediaCard) or UFS (Universal Flash Storage). These solder balls 30 serve as electrical connection points to enable the chip to interact with external circuits, and also act as heat conductors to help dissipate heat from the chip.

[0040] In existing technologies, chips with 153 solder balls 30 are arranged in a U-shape. Most of the solder balls 30 are located in the memory chip area, with some positioned between the control chip 20 and the memory chip 10. Fewer solder balls 30 are located below the control chip 20. However, due to the relatively small size but high heat flux density of the control chip 20, this area experiences the highest temperature on the entire chip. Existing designs for the solder ball arrangement do not adequately consider heat dissipation in the control chip 20 area, resulting in poor overall chip heat dissipation and a high overall thermal resistance.

[0041] right Figure 1 The chip with a 30-ball arrangement shown was subjected to thermal simulation in a JEDEC standard test chamber. According to the simulation results, the junction temperature of the corresponding chip is 45.95 degrees Celsius, and the ambient temperature is 25 degrees Celsius. Therefore, the thermal resistance of the corresponding chip can be calculated as follows: Thermal resistance Rja_1=(Tj_1-Ta_1) / P=(45.95-25) / 0.426=49.18℃ / W; where Rja_1 is... Figure 1 The corresponding thermal resistance of the chip, Tj_1 is Figure 1 The corresponding junction temperature of the chip, Ta_1 is the ambient temperature, and P is the preset heating power.

[0042] Based on the problems of poor heat dissipation and high overall thermal resistance of chips with 153 solder balls 30 in the existing technology, this application proposes a solder ball 30 arrangement structure, packaging component and electronic device for memory chips. The design optimizes the distribution of solder balls 30 without changing the number of solder balls 30, so that the optimized solder ball 30 distribution is more conducive to heat dissipation of the chip, thereby making the chip have a lower thermal resistance value without the addition of external heat dissipation measures.

[0043] The embedded chip packaging structure will be described below with reference to some specific embodiments.

[0044] like Figure 2 As shown, the embedded chip package structure includes: a printed circuit board 70, a substrate 60, and a control chip and a memory chip disposed on the substrate 60. The substrate 60 is connected to the printed circuit board 70 through solder balls.

[0045] Figure 3 This diagram shows the first arrangement of solder balls at the bottom of substrate 60; Figure 4 This diagram shows a second arrangement of solder balls at the bottom of substrate 60; as shown. Figure 3 and Figure 4As shown, a first solder ball array 40 is disposed below a first region of the substrate 60; wherein, the first region is the region where the control chip is located in the substrate 60 and the area surrounding the region where the control chip is located; a second solder ball array 50 is disposed below a second region of the substrate 60; wherein, the second region is the region where the memory chip is located in the substrate 60 and the area surrounding the region where the memory chip is located.

[0046] It should be noted that the area surrounding the control chip refers to the region extending outwards from the area of ​​the substrate 60 corresponding to the control chip by a first preset distance. This first preset distance can be reasonably set based on the size of the control chip and its distance from the memory chip. The area surrounding the memory chip refers to the region extending outwards from the area of ​​the substrate 60 corresponding to the memory chip by a second preset distance. This second preset distance can also be reasonably set based on the size of the memory chip and its distance from the control chip.

[0047] It is understood that in this embodiment, all the solder balls 30 in the embedded chip package structure are divided into two parts. The first solder ball array 40 is arranged in the first region of the control chip 20, but not only below the control chip 20; it can extend beyond the control chip 20 itself. The second solder ball array 50 is arranged in the region of the memory chip 10, but not only below the memory chip 10; it can also extend beyond the memory chip 10 itself. Because the control chip 20 is small in size and has a high heat flux density, arranging the solder balls 30 in this way allows for a greater number of solder balls 30 compared to existing technologies. Furthermore, the solder balls 30 are distributed throughout and around the control chip 20, meaning there are solder balls 30 at every location on the control chip 20. This enhances heat dissipation at the control chip 20. Simultaneously, solder balls are also arranged around the substrate 60 corresponding to the control chip 20. Due to the high heat flux density at the control chip 20, the temperature around the control chip 20 is also prone to rise. Therefore, the first solder ball array 40 in this embodiment extends to the surrounding area of ​​the substrate 60 corresponding to the control chip 20, further improving the heat dissipation of the area around the substrate 60. For the memory chip 10, since the contact area between the memory chip 10 and the substrate 60 is large and heat dissipation is relatively good, this arrangement has almost no impact on the heat dissipation of the memory chip 10 itself, but it enhances the overall heat dissipation of the chip, thereby reducing the thermal resistance of the embedded chip.

[0048] Furthermore, the area where the first solder ball array 40 is located must cover the area of ​​the control chip on the substrate 60. It can be understood that this embodiment aims to enhance heat dissipation at the control chip; therefore, the first solder ball array 40 must cover the entire area of ​​the control chip on the substrate 60, meaning the area where the first solder ball array 40 is located must completely cover the area below the control chip.

[0049] In some embodiments, all solder balls 30 in the first solder ball array 40 are evenly arranged in a first region with the control chip 20 as the center, according to a first preset spacing rule; all solder balls 30 in the second solder ball array 50 are arranged in a second region according to a second preset spacing rule.

[0050] It is understandable that, due to the smaller size of the control chip 20, its contact area with the substrate 60 is smaller; while the larger size of the memory chip 10 results in a larger contact area with the substrate 60. Furthermore, to improve the heat dissipation performance of the control chip area, the number of solder balls 30 in the control chip area must be sufficient. Therefore, the arrangement of the solder balls 30 in the control chip area differs from that in the memory chip area; overall, the solder balls 30 in the control chip area are denser than those in the memory chip area. This arrangement of solder balls 30 in this embodiment not only ensures electrical connection between the chip and the circuit board but also provides good heat dissipation for the control chip 20 area.

[0051] In some embodiments, the second solder ball array 50 is disposed in the second region on the side close to the first region.

[0052] It is understandable that the second solder ball array 50 needs to be arranged closer to the first region. This arrangement can further ensure the overall heat dissipation of the chip. The reason is that because the control chip 20 is small in size and has a high heat flux density, the heat around the control chip 20 increases rapidly. However, the memory chip 10 is small in size, and its heat dissipation is not as good as that of the control chip 20. Therefore, when arranging the second solder ball array 50, it can be biased towards the first region, so that there are solder balls near the first region, thereby improving the heat dissipation of this part.

[0053] In some embodiments, the solder balls 30 in the first solder ball array 40 are arranged in whole rows and columns except for the solder balls 30 in the outermost row and column; the solder balls 30 in the second solder ball array 50 are arranged in whole rows and columns except for the solder balls 30 in the outermost row and column.

[0054] For the first solder ball array 40, if both the first and second horizontal spacings are set to 0.5mm, an 8x3 array of solder balls could potentially cover the area below the control chip 20. However, to ensure good heat dissipation around the control chip 20, this 8x3 array can extend outwards. If the first solder ball array 40 has 60 solder balls, it can be set to 5x11, 6x10, or 5x10, with the remaining 10 solder balls positioned in the outer two columns of the 5x10 array. If the first solder ball array 40 has 62 solder balls, it can be set to 6x10, with the remaining two positioned outside the 6x10 array. It is understood that the above configuration of the first solder ball array 40 is merely illustrative; other configurations are possible, which will not be elaborated upon here, nor are they specifically limited. Similarly, the configuration of the second solder ball array 50 is the same as that of the first solder ball array 40, and will not be elaborated upon here.

[0055] It is understandable that the first solder ball array 40 needs to be arranged around the control chip 20, and the portion of the first solder ball array 40 extending beyond the control chip 20 is also uniform, meaning the number of solder balls 30 around the control chip 20 is roughly the same, thus ensuring uniform heat dissipation in the control chip area. However, to adjust the spacing between the first solder ball array 40 and the second solder ball array 50, this spacing can be adjusted by changing the number of solder balls 30 in the two edge columns, such as... Figure 3 The solder ball arrangement shown has 66 solder balls 30 in the first solder ball array 40, arranged in an 11x6 grid. However, if this arrangement results in a large gap between the first solder ball array 40 and the second solder ball array 50, an 11x5 grid array can be initially set up. Then, the remaining 11 solder balls 30 can be divided into two parts and placed on the outer sides of the 11x5 grid array to form two new columns. This compensates for the large gap between the first and second solder ball arrays 40 and 50, thus improving heat dissipation in the area between the control chip 20 and the memory chip 10. Similarly, the arrangement of the second solder ball array 50 is similar to that of the first solder ball array 40 and will not be described further here.

[0056] In some implementations, the first preset spacing rule includes a first horizontal spacing and a first vertical spacing; the value range of the first horizontal spacing is 0.4mm-0.6mm; the value range of the first vertical spacing is 0.4mm-0.6mm.

[0057] The second preset spacing rules include a second horizontal spacing and a second vertical spacing; the value range of the second horizontal spacing is 0.6mm-1.0mm; the value range of the second vertical spacing is 0.6mm-1.0mm.

[0058] It is understandable that the spacing between two adjacent solder balls 30 in the first solder ball array 40 is less than or equal to the spacing between two adjacent solder balls 30 in the second solder ball array 50. This setting is more in line with the size difference between the control chip 20 and the memory chip 10. Since the control chip 20 is smaller, its spacing is also set relatively smaller, which ensures that all solder balls 30 in the control chip area can be arranged. On the other hand, the memory chip 10 is larger, so the spacing can be set relatively larger, which allows the second solder ball array 50 to cover as much of the space under the memory chip 10 as possible. This also ensures uniform heat dissipation in the memory chip area and good heat dissipation effect.

[0059] In a preferred embodiment, the first lateral spacing is 0.5 mm; the first longitudinal spacing is 0.5 mm; the second lateral spacing is 0.7 mm; and the second longitudinal spacing is 1.0 mm.

[0060] The spacing of the solder balls 30 in the first solder ball array 40 is set in such a way that it can ensure the heat dissipation requirements of the control chip area, and it is also relatively simple in terms of process implementation, that is, it will not increase the difficulty of the process. Since the memory chip 10 is rectangular, the horizontal spacing in the second solder ball array 50 is smaller than the vertical spacing, so that the second solder ball array 50 can cover the entire area under the memory chip 10.

[0061] In some embodiments, since this application is applicable to chips with 153 solder balls 30, that is, the total number of solder balls 30 is 153, the number of solder balls 30 in the control chip area can be in the range of 50-80, that is, the first preset number is in the range of 50-80, including 50 and 80. After the first preset number is determined, the second preset number, that is, the number of solder balls 30 in the memory chip area, can be directly determined.

[0062] like Figure 3 As shown, the first preset quantity is 66, and the second preset quantity is 87. This means there are 66 solder balls 30 located below the control chip 20 and 87 solder balls 30 located below the memory chip 10. The arrangement of the solder balls 30 is as follows: Figure 3 As shown. For Figure 3 The chip with the 30-ball arrangement shown was subjected to thermal simulation in a JEDEC standard test chamber. According to the simulation results, the junction temperature of the corresponding chip is 43.9 degrees Celsius, and the ambient temperature is 25 degrees Celsius. Therefore, the thermal resistance of the corresponding chip can be calculated as follows: Thermal resistance Rja = (Tj - Ta) / P = (43.9 - 25) / 0.426 = 44.37℃ / W; where Rja is the thermal resistance of the corresponding chip, Tj is the junction temperature of the corresponding chip, Ta is the ambient temperature, and P is the preset heat dissipation power.

[0063] like Figure 4As shown, the first preset quantity is 77, and the second preset quantity is 76. This means there are 77 solder balls 30 located below the control chip 20 and 76 solder balls 30 located below the memory chip 10. The arrangement of the solder balls 30 is as follows: Figure 4 As shown. For Figure 4 The chip with the 30-ball arrangement shown was subjected to thermal simulation in a JEDEC standard test chamber. According to the simulation results, the junction temperature of the corresponding chip is 43.91 degrees Celsius, and the ambient temperature is 25 degrees Celsius. Therefore, the thermal resistance of the corresponding chip can be calculated as follows: Thermal resistance Rja=(Tj-Ta) / P=(43.91-25) / 0.426=44.39℃ / W; where Rja is the thermal resistance of the corresponding chip, Tj is the junction temperature of the corresponding chip, Ta is the ambient temperature, and P is the preset heat dissipation power.

[0064] The solder balls 30 of the chip were arranged in the manner described above, and the corresponding chip was subjected to thermal simulation in a JEDEC standard test chamber to calculate the corresponding thermal resistance. The results are shown in the table below:

[0065]

[0066] As shown in the table above, a preferred implementation is to set the first preset quantity to 66. When arranging the solder balls 30 in the control chip area and the memory chip area in the above manner, the specific arrangement has little impact on the thermal resistance; the main impact lies in the number of solder balls 30. Therefore, according to the table above, the thermal resistance is relatively minimized when 66 solder balls 30 are arranged in the control chip area and 87 solder balls 30 are arranged in the memory chip area.

[0067] This application divides all the solder balls 30 into two parts: the solder balls 30 of the first solder ball array 40 are arranged in the first region, and the solder balls 30 of the second solder ball array 50 are arranged in the second region. Since the control chip 20 is small in size, has a high heat flux density, and a greater temperature pressure, this method can increase the number of solder balls 30 in the region of the control chip 20, thereby enhancing the heat dissipation of the region of the control chip 20 and reducing the thermal resistance of the chip.

[0068] This application also provides an electronic device, which includes the above-described embedded chip packaging structure.

[0069] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. An embedded chip packaging structure, characterized in that, include: Printed circuit board, substrate, and control chip and memory chip disposed on said substrate; The substrate is connected to the printed circuit board via solder balls; A first solder ball array is disposed below a first region of the substrate; wherein, the first region is the region where the control chip is located in the substrate and the area surrounding the region where the control chip is located; A second array of solder balls is disposed below a second region of the substrate; wherein, the second region is the region where the memory chip is located in the substrate and the area surrounding the region where the memory chip is located; The area where the first solder ball array is located needs to cover the area of ​​the control chip on the substrate.

2. The embedded chip packaging structure according to claim 1, characterized in that, All the solder balls in the first solder ball array are arranged in the first region with the control chip as the center, according to a first preset spacing rule; All the solder balls in the second solder ball array are arranged in the second region according to the second preset spacing rule.

3. The embedded chip packaging structure according to claim 1, characterized in that, The total number of solder balls is 153; the number of solder balls in the first solder ball array ranges from 50 to 80.

4. The embedded chip packaging structure according to claim 3, characterized in that, The number of solder balls in the first solder ball array is 66.

5. The embedded chip packaging structure according to claim 2, characterized in that, The first preset spacing rule includes a first horizontal spacing and a first vertical spacing; The first lateral spacing ranges from 0.4mm to 0.6mm; The first longitudinal spacing ranges from 0.4mm to 0.6mm.

6. The embedded chip packaging structure according to claim 5, characterized in that, The second preset spacing rule includes a second horizontal spacing and a second vertical spacing; The second lateral spacing ranges from 0.6mm to 1.0mm; The second longitudinal spacing ranges from 0.6mm to 1.0mm.

7. The embedded chip packaging structure according to claim 6, characterized in that, The first lateral spacing is 0.5 mm; the first longitudinal spacing is 0.5 mm; The second horizontal spacing is 0.7 mm; the second vertical spacing is 1.0 mm.

8. The embedded chip packaging structure according to claim 2, characterized in that, The second solder ball array is positioned in the second region on the side closest to the first region.

9. The embedded chip packaging structure according to claim 2, characterized in that, Except for the solder balls in the outermost row and column, all other solder balls in the first solder ball array are arranged in complete rows and columns; Except for the solder balls in the outermost row and column, the solder balls in the second solder ball array are arranged in complete rows and columns.

10. An electronic device, characterized in that, The electronic device includes the embedded chip packaging structure according to any one of claims 1-9.

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