Level shifter

Abstract

The utility model discloses a level shifter, which comprises a first phase inverter, a second phase inverter, a third phase inverter, a first delay matching unit and a second delay matching unit, the first phase inverter and the second delay matching unit are used for receiving the first voltage signal and the second voltage signal; the first delay matching unit is connected with the output end of the first phase inverter, and the first delay matching unit is connected with the second phase inverter and the third phase inverter; the second delay matching unit is connected with the third phase inverter and the second phase inverter; the output end of the second phase inverter and the output end of the third phase inverter output voltage signals of a second voltage domain. According to the level shifter provided by the utility model, high-speed level shifting can be greatly facilitated by adopting an input mode of the delay matching units, and meanwhile, the two delay matching units enable mismatch influence on two signal transmission paths to be well controlled, so that the design stability can be improved.

Description

Technical Field

[0001] This utility model belongs to the field of integrated circuit technology, and specifically relates to a level converter. Background Technology

[0002] A level shifter is a circuit that spans different voltage domains, enabling the conversion of signals from one voltage domain to another in multi-power-domain designs. The voltage domains involved vary across different system applications, making the conversion between floating voltage domains particularly challenging for traditional level shifters.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of this utility model and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Utility Model Content

[0004] The purpose of this invention is to provide a level converter that can realize signal conversion between fixed voltage domain and floating voltage domain, between fixed voltage domain and fixed voltage domain, and between floating voltage domain and floating voltage domain.

[0005] To achieve the above objectives, a specific embodiment of the present invention provides a level converter, including: a first inverter operating in a first voltage domain, a second inverter and a third inverter operating in a second voltage domain, as well as a first delay matching unit and a second delay matching unit;

[0006] The input terminal of the first inverter and the first terminal of the second delay matching unit are used to receive the first voltage signal and the second voltage signal of the first voltage domain; the first terminal of the first delay matching unit is connected to the output terminal of the first inverter, the second terminal of the first delay matching unit is connected to the input terminal of the second inverter, and the third terminal of the first delay matching unit is connected to the output terminal of the third inverter; the second terminal of the second delay matching unit is connected to the input terminal of the third inverter, and the third terminal of the second delay matching unit is connected to the output terminal of the second inverter; the output terminals of the second inverter and the third inverter output the voltage signal of the second voltage domain.

[0007] In one or more embodiments of the present invention, the first delay matching unit includes a first coupling unit and a first matching unit. The first end of the first coupling unit is connected to the output end of the first inverter. The second end of the first coupling unit is connected to the input end of the second inverter and the first end of the first matching unit. The second end of the first matching unit is connected to the output end of the third inverter.

[0008] In one or more embodiments of the present invention, the second delay matching unit includes a second coupling unit and a second matching unit. The first end of the second coupling unit is used to receive a first voltage signal and a second voltage signal of a first voltage domain. The second end of the second coupling unit is connected to the input end of a third inverter and the first end of the second matching unit. The second end of the second matching unit is connected to the input end of a second inverter.

[0009] In one or more embodiments of the present invention, the level converter further includes a first output unit and a second output unit operating in a second voltage domain. The input terminal of the first output unit is connected to the output terminal of a second inverter, and the input terminal of the second output unit is connected to the output terminal of a third inverter. The output terminals of the first output unit and the second output unit are used to output a third voltage signal and a fourth voltage signal in the second voltage domain.

[0010] In one or more embodiments of the present invention, the first output unit includes one or more fourth inverters connected in series.

[0011] In one or more embodiments of this utility model, a first feedback capacitor is provided between the input terminal of the first stage inverter and the output terminal of the second stage inverter and the fourth stage inverter of any two stages.

[0012] In one or more embodiments of the present invention, the second output unit includes one or more fifth inverters connected in series.

[0013] In one or more embodiments of this utility model, a second feedback capacitor is provided between the input terminal of the preceding stage inverter and the output terminal of the following stage inverter in any two stages of the third and fifth inverters.

[0014] In one or more embodiments of this utility model, the first coupling unit includes a first capacitor, a first terminal of which is connected to the output terminal of a first inverter, and a second terminal of which is connected to the input terminal of a second inverter and the first terminal of a first matching unit; and / or

[0015] The first matching unit includes a first resistor, the first end of which is connected to the input of the second inverter and the second end of the first coupling unit, and the second end of the first resistor is connected to the output of the third inverter.

[0016] In one or more embodiments of this utility model, the second coupling unit includes a second capacitor, a first terminal of the second capacitor is used to receive a first voltage signal and a second voltage signal of a first voltage domain, and a second terminal of the second capacitor is connected to the input terminal of a third inverter and the first terminal of a second matching unit; and / or

[0017] The second matching unit includes a second resistor, the first end of which is connected to the second end of the second coupling unit and the input end of the third inverter, and the second end of which is connected to the output end of the second inverter.

[0018] Compared with existing technologies, the level converter of this invention, by employing an input method with delay matching units, greatly facilitates high-speed level conversion. Simultaneously, the two delay matching units effectively control the mismatch effects on the two signal transmission paths, improving design stability. This level converter is applicable to level conversion between both fixed and floating level domains. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a circuit schematic of a level converter in one embodiment. Detailed Implementation

[0021] To enable those skilled in the art to better understand the technical solutions of this utility model, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this utility model.

[0022] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in utility models, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0023] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0024] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0025] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0026] Various components and devices may be referred to or shown in the singular (e.g., “transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0027] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used with respect to embodiments of this disclosure are synonymous.

[0028] like Figure 1 As shown in the figure, a level converter in this embodiment of the present invention includes: a first inverter N1 operating in a first voltage domain, a second inverter N2 and a third inverter N3 operating in a second voltage domain, a first output unit and a second output unit operating in the second voltage domain, and a first delay matching unit 10 and a second delay matching unit 20. The first delay matching unit 10 and the second delay matching unit 20 can match high-speed level conversion and improve conversion stability. The first voltage domain can be a fixed voltage domain or a floating voltage domain, and the second voltage domain can also be a fixed voltage domain or a floating voltage domain.

[0029] The input terminal of the first inverter N1 and the first terminal of the second delay matching unit 20 are used to receive the first voltage signal AVDDL and the second voltage signal AVSSL of the first voltage domain; the first terminal of the first delay matching unit 10 is connected to the output terminal of the first inverter N1, the second terminal of the first delay matching unit 10 is connected to the input terminal of the second inverter N2, and the third terminal of the first delay matching unit 10 is connected to the output terminal of the third inverter N3; the second terminal of the second delay matching unit 20 is connected to the input terminal of the third inverter N3, and the third terminal of the second delay matching unit 20 is connected to the output terminal of the second inverter N2; the output terminals of the second inverter N2 and the third inverter N3 output the voltage signal of the second voltage domain.

[0030] The input terminal of the first output unit is connected to the output terminal of the second inverter N2, and the input terminal of the second output unit is connected to the output terminal of the third inverter N3. The output terminal VOUTN of the first output unit and the output terminal VOUTP of the second output unit are used to output the third voltage signal AVDDH and the fourth voltage signal AVSSH in the second voltage domain.

[0031] In one embodiment, the first delay matching unit 10 includes a first coupling unit and a first matching unit. The first end of the first coupling unit is connected to the output end of the first inverter N1, the second end of the first coupling unit is connected to the input end of the second inverter N2 and the first end of the first matching unit, and the second end of the first matching unit is connected to the output end of the third inverter N3.

[0032] Specifically, the first coupling unit includes a first capacitor C1, and the first matching unit includes a first resistor R1. The first terminal of the first capacitor C1 is connected to the output terminal of the first inverter N1, the second terminal of the first capacitor C1 is connected to the input terminal of the second inverter N2 and the first terminal of the first resistor R1 in the first matching unit, and the second terminal of the first resistor R1 is connected to the output terminal of the third inverter N3. In other embodiments, the first coupling unit and the first matching unit can be other coupling circuits.

[0033] In one embodiment, the second delay matching unit 20 includes a second coupling unit and a second matching unit. The first end of the second coupling unit is used to receive the first voltage signal AVDDL and the second voltage signal AVSSL of the first voltage domain. The second end of the second coupling unit is connected to the input end of the third inverter N3 and the first end of the second matching unit. The second end of the second matching unit is connected to the input end of the second inverter N2.

[0034] Specifically, the second coupling unit includes a second capacitor C2, and the second matching unit includes a second resistor R2. The first terminal of the second capacitor C2 is used to receive the first voltage signal AVDDL and the second voltage signal AVSSL of the first voltage domain. The second terminal of the second capacitor C2 is connected to the input terminal of the third inverter N3 and the first terminal of the second resistor R2 of the second matching unit. The second terminal of the second resistor R2 is connected to the output terminal of the second inverter N2. In other embodiments, the second coupling unit and the second matching unit can be other coupling circuits.

[0035] like Figure 1 As shown, the first output unit includes three fourth inverters N41, N42, and N43 connected in series. In other embodiments, the number of fourth inverters can be selected and set as needed.

[0036] In one embodiment, a first feedback capacitor is provided between the input terminal of the preceding inverter and the output terminal of the following inverter in any two stages of the second inverter N2 and the fourth inverters N41, N42, and N43. That is, for example, the first feedback capacitor may be provided between the input terminal of the second inverter N2 and the output terminal of the fourth inverter N41 to achieve positive feedback, and / or between the input terminal of the second inverter N2 and the output terminal of the fourth inverter N42 to achieve positive feedback, and / or between the input terminal of the second inverter N2 and the output terminal of the fourth inverter N43 to achieve positive feedback; alternatively, the first feedback capacitor may be provided between the input terminal of the fourth inverter N41 and the output terminal of the fourth inverter N43, and / or between the input terminal of the fourth inverter N41 and the output terminal of the fourth inverter N42, and / or between the input terminal of the fourth inverter N42 and the output terminal of the fourth inverter N43, etc.

[0037] like Figure 1 As shown, the second output unit includes three fifth inverters N51, N52, and N53 connected in series. In other embodiments, the number of fifth inverters can be selected and set as needed.

[0038] In one embodiment, a second feedback capacitor is provided between the input terminal of the preceding inverter and the output terminal of the following inverter in any two stages of the third inverter N3 and the fifth inverters N51, N52, and N53. For example, a second feedback capacitor can be provided between the input terminal of the third inverter N3 and the output terminal of the fifth inverter N51 to achieve positive feedback, and / or a second feedback capacitor can be provided between the input terminal of the third inverter N3 and the output terminal of the fifth inverter N52 to achieve positive feedback, and / or a second feedback capacitor can be provided between the input terminal of the third inverter N3 and the output terminal of the fifth inverter N53 to achieve positive feedback, or a second feedback capacitor can be provided between the input terminal of the fifth inverter N51 and the output terminal of the fifth inverter N53, and / or a second feedback capacitor can be provided between the input terminal of the fifth inverter N51 and the output terminal of the fifth inverter N52, and / or a second feedback capacitor can be provided between the input terminal of the fifth inverter N52 and the output terminal of the fifth inverter N53, and so on.

[0039] By adding a feedback capacitor to achieve positive feedback between the two inverter stages, the signal gain and amplitude can be enhanced, and a hysteresis effect can be produced to prevent false triggering caused by noise interference.

[0040] In one embodiment, the second inverter N2, the third inverter N3, the fourth inverters N41, N42, N43, and the fifth inverters N51, N52, N53 have the same structure, all composed of N-type MOSFETs and P-type MOSFETs. In other embodiments, the second inverter N2, the third inverter N3, the fourth inverters N41, N42, N43, and the fifth inverters N51, N52, N53 can also be other inverter structures.

[0041] like Figure 1 As shown, the second inverter N2 includes the first MOSFET M1 and the second MOSFET M2, the fourth inverter N41 includes the fifth MOSFET M5 and the sixth MOSFET M6, the fourth inverter N42 includes the seventh MOSFET M7 and the eighth MOSFET M8, and the fourth inverter N43 includes the ninth MOSFET M9 and the tenth MOSFET M10.

[0042] The sources of the first MOSFET M1, the fifth MOSFET M5, the seventh MOSFET M7, and the ninth MOSFET M9 are connected to the third voltage signal AVDDH. The sources of the second MOSFET M2, the sixth MOSFET M6, the eighth MOSFET M8, and the tenth MOSFET M10 are connected to the fourth voltage signal AVSSH. The gates of the first MOSFET M1 and the second MOSFET M2 are connected to form the input terminal of the second inverter N2. The drains of the first MOSFET M1 and the second MOSFET M2 are connected to form the output terminal of the second inverter N2. The gates of the fifth MOSFET M5 and the sixth MOSFET M9 are connected to the third voltage signal AVDDH. The gates of transistors M6 and M7 are connected to form the input terminal of the fourth inverter N41. The drains of transistors M5 and M6 are connected to form the output terminal of the fourth inverter N41. The gates of transistors M7 and M8 are connected to form the input terminal of the fourth inverter N42. The drains of transistors M7 and M8 are connected to form the output terminal of the fourth inverter N42. The gates of transistors M9 and M10 are connected to form the input terminal of the fourth inverter N43. The drains of transistors M9 and M10 are connected to form the output terminal of the fourth inverter N43.

[0043] The third inverter N3 includes the third MOSFET M3 and the fourth MOSFET M4; the fifth inverter N51 includes the eleventh MOSFET M11 and the twelfth MOSFET M12; the fifth inverter N52 includes the thirteenth MOSFET M13 and the fourteenth MOSFET M14; and the fifth inverter N53 includes the fifteenth MOSFET M15 and the sixteenth MOSFET M16.

[0044] The sources of the third MOSFET M3, the eleventh MOSFET M11, the thirteenth MOSFET M13, and the fifteenth MOSFET M15 are connected to the third voltage signal AVDDH. The sources of the fourth MOSFET M4, the twelfth MOSFET M12, the fourteenth MOSFET M14, and the sixteenth MOSFET M16 are connected to the fourth voltage signal AVSSH. The gates of the third MOSFET M3 and the fourth MOSFET M4 are connected to form the input terminal of the third inverter N3. The drains of the third MOSFET M3 and the fourth MOSFET M4 are connected to form the output terminal of the third inverter N3. The gates of the eleventh MOSFET M11 and the twelfth MOSFET M12 are connected to the third voltage signal AVSSH. The gates of the 11th MOSFET M11 and the 12th MOSFET M12 are connected to form the input terminal of the fifth inverter N51. The gates of the 13th MOSFET M13 and the 14th MOSFET M14 are connected to form the input terminal of the fifth inverter N52. The drains of the 13th MOSFET M13 and the 14th MOSFET M14 are connected to form the output terminal of the fifth inverter N52. The gates of the 15th MOSFET M15 and the 16th MOSFET M16 are connected to form the input terminal of the fifth inverter N53. The drains of the 15th MOSFET M15 and the 16th MOSFET M16 are connected to form the output terminal of the fifth inverter N53.

[0045] In one embodiment, taking the application scenario of converting a fixed voltage domain signal into a floating voltage domain signal as an example, the first voltage signal AVDDL and the second voltage signal AVSSL can be considered as fixed levels, the fourth voltage signal AVSSH is a floating ground, that is, it may change (the range of change may be from negative voltage to positive voltage), and the third voltage signal AVDDH is positioned as AVSSH+V1, where V1 represents the voltage difference between the floating domain power supply and ground.

[0046] like Figure 1 As shown, the total input terminal VIN corresponds to the fixed voltage domain signal, and the total output terminals VOUTN and VOUTP correspond to the floating voltage domain signals, ultimately achieving the effect of converting the input signal from the fixed voltage domain (first voltage signal AVDDL, second voltage signal AVSSL) to the floating voltage domain (third voltage signal AVDDH, fourth voltage signal AVSSH).

[0047] The input signals (first voltage signal AVDDL and second voltage signal AVSSL) are coupled to the input terminal of the third inverter N3 through the second capacitor C2AC. The output signal of the third inverter N3 is the floating voltage domain signal (third voltage signal AVDDH and fourth voltage signal AVSSH). After passing through the three-stage inverter consisting of the fifth inverters N51, N52, and N53, the signal is output. The output signal of the total output terminal VOUTP is the floating voltage domain signal (third voltage signal AVDDH and fourth voltage signal AVSSH).

[0048] The input signals are simultaneously input to the first inverter N1, which operates in a fixed voltage domain (first voltage signal AVDDL, second voltage signal AVSSL). After passing through the first capacitor C1AC, they are coupled to the input terminal of the second inverter N2. The output signal of the second inverter N2 is the signal in the floating voltage domain (third voltage signal AVDDH, fourth voltage signal AVSSH). After passing through the fourth inverters N41, N42, and N43, the signal is output. The output signal of the total output terminal VOUTN is the signal in the floating voltage domain (third voltage signal AVDDH, fourth voltage signal AVSSH). The signals output by the total output terminals VOUTN and VOUTP are inverted signals.

[0049] The first capacitor C1 and the second capacitor C2 can adapt to high-speed level conversion, ensure the stability of high-speed level conversion, and avoid errors in subsequent inverter logic flipping.

[0050] From an overall structural perspective, the second inverter N2 and the third inverter N3 form a latch structure to latch the signal level. The input signal is coupled into the latch through capacitor AC, overturning the previously latched state and causing the latch to latch the new logic state. The signal is then output through the subsequent inverter, ultimately achieving the conversion between the fixed input level domain and the floating output level domain. Because it is based on a latch structure, the mismatch between the two paths of the second inverter N2 and the third inverter N3 has a significant impact on the final conversion result. Furthermore, relying solely on the second inverter N2 and the third inverter N3 makes it difficult to match and control the charging speed of the first capacitor C1 and the second capacitor C2. In this embodiment, a scheme of adding a first resistor R1 and a second resistor R2 is adopted. The matching of the charging speed of the second inverter N2 and the third inverter N3 to the first capacitor C1 and the second capacitor C2 is transformed into the matching of the RC delay formed by the first resistor R1 and the first capacitor C1, the second resistor R2 and the second capacitor C2. This can better control the mismatch on the two paths and greatly improve the stability of the design. At the same time, this level converter circuit has no static power consumption.

[0051] This application also discloses a chip including the aforementioned level converter.

[0052] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0053] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A level converter, characterized in that, include: A first inverter operating in a first voltage domain, a second inverter and a third inverter operating in a second voltage domain, as well as a first delay matching unit and a second delay matching unit; The input terminal of the first inverter and the first terminal of the second delay matching unit are used to receive the first voltage signal and the second voltage signal of the first voltage domain; the first terminal of the first delay matching unit is connected to the output terminal of the first inverter, the second terminal of the first delay matching unit is connected to the input terminal of the second inverter, and the third terminal of the first delay matching unit is connected to the output terminal of the third inverter; the second terminal of the second delay matching unit is connected to the input terminal of the third inverter, and the third terminal of the second delay matching unit is connected to the output terminal of the second inverter; the output terminals of the second inverter and the third inverter output the voltage signal of the second voltage domain.

2. The level converter according to claim 1, characterized in that, The first delay matching unit includes a first coupling unit and a first matching unit. The first end of the first coupling unit is connected to the output of the first inverter. The second end of the first coupling unit is connected to the input of the second inverter and the first end of the first matching unit. The second end of the first matching unit is connected to the output of the third inverter.

3. The level converter according to claim 1, characterized in that, The second delay matching unit includes a second coupling unit and a second matching unit. The first end of the second coupling unit is used to receive a first voltage signal and a second voltage signal of the first voltage domain. The second end of the second coupling unit is connected to the input end of the third inverter and the first end of the second matching unit. The second end of the second matching unit is connected to the input end of the second inverter.

4. The level converter according to claim 1, characterized in that, The level converter further includes a first output unit and a second output unit operating in a second voltage domain. The input terminal of the first output unit is connected to the output terminal of the second inverter, and the input terminal of the second output unit is connected to the output terminal of the third inverter. The output terminals of the first output unit and the second output unit are used to output a third voltage signal and a fourth voltage signal in the second voltage domain.

5. The level converter according to claim 4, characterized in that, The first output unit includes one or more fourth inverters connected in series.

6. The level converter according to claim 5, characterized in that, A first feedback capacitor is provided between the input terminal of the preceding stage inverter and the output terminal of the following stage inverter in any two stages of the second and fourth inverters.

7. The level converter according to claim 4, characterized in that, The second output unit includes one or more fifth inverters connected in series.

8. The level converter according to claim 7, characterized in that, A second feedback capacitor is provided between the input terminal of the preceding inverter and the output terminal of the following inverter in any two stages of the third and fifth inverters.

9. The level converter according to claim 2, characterized in that, The first coupling unit includes a first capacitor, a first terminal of which is connected to the output terminal of a first inverter, and a second terminal of which is connected to the input terminal of a second inverter and the first terminal of a first matching unit; and / or The first matching unit includes a first resistor, the first end of which is connected to the input of the second inverter and the second end of the first coupling unit, and the second end of the first resistor is connected to the output of the third inverter.

10. The level converter according to claim 3, characterized in that, The second coupling unit includes a second capacitor, the first terminal of which is used to receive a first voltage signal and a second voltage signal from a first voltage domain, and the second terminal of which is connected to the input terminal of a third inverter and the first terminal of a second matching unit; and / or The second matching unit includes a second resistor, the first end of which is connected to the second end of the second coupling unit and the input end of the third inverter, and the second end of which is connected to the output end of the second inverter.

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