Signal gain circuit and electronic equipment

Abstract

The embodiment of the utility model provides a signal gain circuit and electronic equipment. The signal gain circuit comprises a sampling and holding module, a first operational amplifier follower circuit, a second operational amplifier follower circuit, a subtraction operation circuit and a signal amplification module, in the first working mode of the photosensitive element, the sampling holding module obtains and stores a first sampling signal output by the photosensitive element; in the second working mode of the photosensitive element, the sampling holding module outputs the first sampling signal; the second operational amplifier follower circuit obtains a second sampling signal output by the photosensitive element; the first sampling signal and the second sampling signal are input into a subtraction operation circuit for subtraction operation; and the operation result is output to the signal amplification module to gain the signal. According to the circuit disclosed by the embodiment of the invention, the dynamic range of the effective signal in the photoelectric sensing signal is improved by eliminating the influence of the bias voltage in the photoelectric sensing signal, and the effective signal is adjusted and gained, so that the detection capability of the OES on the weak signal is improved, and the resolution of the signal can be effectively improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of scientific instruments, and in particular to a signal gain circuit and an electronic device. BACKGROUND

[0002] The existing direct-reading spectrometer (OES) using a complementary metal oxide semiconductor (CMOS) as a photosensitive element contains a bias voltage in the photoelectric sensing signal. The existing signal gain circuit is affected by the bias voltage, resulting in a small dynamic range of the effective signal in the amplified photoelectric sensing signal, limiting the amplification multiple of the effective signal, and further limiting the detection ability of the OES to weak signals. To solve the existing problems, a new circuit is needed. SUMMARY

[0003] The embodiments of the present disclosure provide a signal gain circuit and an electronic device to solve the problem of low amplification multiple of the photoelectric sensing signal, small dynamic range of the effective signal, and weak detection ability to weak signals of the existing signal gain circuit.

[0004] Based on the above problems, in a first aspect, the embodiments of the present disclosure provide a signal gain circuit, a sample and hold module, a first operational amplifier follower circuit, a second operational amplifier follower circuit, a subtraction operation circuit, and a signal amplification module.

[0005] The input end of the sample and hold module and the input end of the second operational amplifier follower circuit receive an output signal of a photosensitive element, respectively; and the output end of the sample and hold module is connected to the input end of the first operational amplifier follower circuit.

[0006] In a case where the photosensitive element works in a first working mode, the sample and hold module is configured to acquire and store a first sampling signal output by the photosensitive element.

[0007] In a case where the photosensitive element works in a second working mode, the sample and hold module is configured to output the first sampling signal to the first operational amplifier follower circuit; the second operational amplifier follower circuit is configured to acquire a second sampling signal output by the photosensitive element; input the first sampling signal and the second sampling signal into the subtraction operation circuit to perform subtraction operation; and output the subtraction operation result to the signal amplification module to perform gain on the signal.

[0008] In combination with the first aspect, in a possible implementation, the signal gain circuit further includes a control module; and the sample and hold module includes a switch chip, a first resistor, and a first capacitor.

[0009] The first end of the switch chip receives an output signal of the photosensitive element; the second end of the switch chip is connected with one end of the first resistor, and the other end of the first resistor and one end of the first capacitor are connected with the input end of the first operational amplifier follow-up circuit; the other end of the first capacitor is grounded; and the control end of the switch chip is used for receiving a control signal of the control module;

[0010] In a case where the photosensitive element works in the first working mode, the control signal instructs the switch chip to be turned on, and the first capacitor acquires and stores the first sampling signal;

[0011] In a case where the photosensitive element works in the second working mode, the control signal instructs the switch chip to be turned off, and the first capacitor outputs the stored first sampling signal to the first operational amplifier follow-up circuit.

[0012] With reference to the first aspect, in a possible implementation, the application further provides a control module.

[0013] The clock CLK end and the start ST end of the photosensitive element are connected with the control module respectively.

[0014] The control module is used for sending a clock pulse signal to the CLK end and sending a start pulse signal to the ST end, so as to control the photosensitive element to switch between the first working mode and the second working mode through the start pulse signal.

[0015] The control module is further used for generating a corresponding control signal according to different working stages of the photosensitive element and sending the control signal to the sampling and holding module.

[0016] With reference to the first aspect, in a possible implementation, the signal amplification module comprises a signal amplification circuit, a differential amplification circuit and a voltage division calculation circuit.

[0017] The input end of the signal amplification circuit is connected with the output end of the subtraction operation circuit; the output end of the signal amplification circuit is connected with the positive input end of the differential amplification circuit, and the differential amplification circuit outputs an amplified signal.

[0018] The negative input end of the differential amplification circuit is connected with the output end of the voltage division calculation circuit, receives a bias signal output by the voltage division calculation circuit, and amplifies the amplified signal and the bias signal based on a common-mode voltage respectively, and generates a differential signal based on the amplified amplified signal and bias signal.

[0019] The differential signal is used for outputting for subsequent processing after being subjected to analog-to-digital conversion by an analog-to-digital conversion circuit; and the bias signal is acquired from a control module through a communication end of the voltage division calculation circuit.

[0020] With reference to the first aspect, in a possible implementation, the first operational amplifier follower circuit comprises a first operational amplifier.

[0021] The positive input terminal of the first operational amplifier is connected with the output terminal of the sample-and-hold module; the output terminal of the first operational amplifier is connected with the negative output terminal; and the output terminal of the first operational amplifier is connected with the subtraction operation circuit.

[0022] With reference to the first aspect, in a possible implementation, the second operational amplifier follower circuit comprises a second operational amplifier.

[0023] The positive input terminal of the second operational amplifier receives an output signal of a photosensitive element; the output terminal of the second operational amplifier is connected with the negative output terminal; and the output terminal of the second operational amplifier is connected with the subtraction operation circuit.

[0024] With reference to the first aspect, in a possible implementation, the subtraction operation circuit comprises a third operational amplifier.

[0025] The positive input terminal of the third operational amplifier is connected with the output terminal of the second operational amplifier follower circuit; the negative input terminal of the third operational amplifier is connected with the output terminal of the first operational amplifier follower circuit; the output terminal of the third operational amplifier is connected with the negative input terminal through a parallel connection of a capacitor and a resistor; and the output terminal of the third operational amplifier outputs a subtraction operation result.

[0026] With reference to the first aspect, in a possible implementation, the signal amplification circuit comprises a fourth operational amplifier, a second resistor and a third resistor.

[0027] The positive input terminal of the fourth operational amplifier is connected with the output terminal of the subtraction operation circuit; the negative input terminal of the fourth operational amplifier is connected with the output terminal through a parallel connection of a capacitor and a second resistor; the negative input terminal of the fourth operational amplifier is connected with the ground through a third resistor; the positive electrode and the negative electrode of the fourth operational amplifier are connected with the positive electrode and the negative electrode of an operational amplifier power supply, respectively; and the output terminal of the fourth operational amplifier outputs an amplified signal.

[0028] With reference to the first aspect, in a possible implementation, the differential amplification circuit comprises a differential driver, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor.

[0029] The positive input terminal of the differential driver is connected with the output terminal of the signal amplification circuit through the fourth resistor; the negative output terminal of the differential driver is connected with the positive input terminal of the differential driver through the fifth resistor;

[0030] The differential driver negative input end is connected with the voltage division calculation circuit output port through the sixth resistor; and the differential driver positive output end is connected with the differential driver negative input port through the seventh resistor.

[0031] The differential driver positive output end and the differential driver negative output end are connected with the analog-to-digital conversion circuit.

[0032] With reference to the first aspect, in a possible implementation, the voltage division calculation circuit comprises: an analog-to-digital conversion chip, a fifth operational amplifier.

[0033] The communication port of the analog-to-digital conversion chip is connected with the communication port of the control module; the analog-to-digital conversion chip is controlled by the control module to output a bias signal through the communication port of the analog-to-digital conversion chip; the output port of the analog-to-digital conversion chip is connected with the positive input end of the fifth operational amplifier to output the bias signal; the output end of the fifth operational amplifier is connected with the reverse input end of the fifth operational amplifier; and the output end of the fifth operational amplifier is connected with the differential amplification circuit to input the bias signal sampled by the fifth operational amplifier into the differential amplification circuit.

[0034] With reference to the first aspect, in a possible implementation, the first working mode comprises an integration working state of the photosensitive element; and the second working mode comprises a signal output working state of the photosensitive element.

[0035] The second aspect provides an electronic device, comprising the signal gain circuit of the first aspect.

[0036] The beneficial effects of the embodiments of the present disclosure include:

[0037] The signal gain circuit and the electronic device provided by the embodiment of the present disclosure comprise a sample and hold module, a first operational amplifier follow-up circuit, a second operational amplifier follow-up circuit, a subtraction operation circuit and a signal amplification module; wherein the input end of the sample and hold module and the input end of the second operational amplifier follow-up circuit respectively receive an output signal of a photosensitive element; the output end of the sample and hold module is connected with the input end of the first operational amplifier follow-up circuit; in the case that the photosensitive element works in a first working mode, the sample and hold module is used for obtaining and storing a first sampling signal output by the photosensitive element; in the case that the photosensitive element works in a second working mode, the sample and hold module is used for outputting the first sampling signal to the first operational amplifier follow-up circuit; the second operational amplifier follow-up circuit is used for obtaining a second sampling signal output by the photosensitive element; the first sampling signal and the second sampling signal are input into the subtraction operation circuit for subtraction operation; and the subtraction operation result is output to the signal amplification module to perform gain on the signal. In the application scenario that the first sampling signal is used as a bias voltage and the second sampling signal is a photoelectric sensing signal containing the bias voltage and an effective signal, the circuit in the embodiment of the present disclosure eliminates the influence of the bias voltage in the photoelectric sensing signal, improves the dynamic range of the effective signal in the photoelectric sensing signal, adjusts and gains the effective signal, improves the detection ability of the OES to weak signals, and effectively improves the resolution of the signal. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 A structural diagram of the signal gain circuit provided by the embodiment of the present disclosure is provided.

[0039] Figure 2 A structural diagram of the signal gain circuit provided in the background art is provided.

[0040] Figure 3 A structural diagram of the sample and hold module provided by the embodiment of the present disclosure is provided.

[0041] Figure 4 A structural diagram of the signal amplification module provided by the embodiment of the present disclosure is provided.

[0042] Figure 5 A structural diagram of the signal amplification circuit provided by the embodiment of the present disclosure is provided.

[0043] Figure 6 A structural diagram of the differential amplification circuit provided by the embodiment of the present disclosure is provided. DETAILED DESCRIPTION

[0044] The embodiment of the present disclosure provides a signal gain circuit and electronic equipment, and the preferred embodiments of the present disclosure are described below in conjunction with the drawings of the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure. Furthermore, the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0045] The embodiment of the present disclosure provides a signal gain circuit, as shown in the figure, comprising: a sample and hold module 1, a first operational amplifier follow-up circuit 2, a second operational amplifier follow-up circuit 3, a subtraction operation circuit 4 and a signal amplification module 7. Figure 1

[0046] The input end of the sample and hold module 1 and the input end of the second operational amplifier follow-up circuit 3 respectively receive the output signal of the photosensitive element 5; the output end of the sample and hold module 1 is connected with the input end of the first operational amplifier follow-up circuit 2.

[0047] In the case that the photosensitive element 5 works in the first working mode, the sample and hold module 1 is used to acquire and store the first sampling signal output by the photosensitive element 5.

[0048] In the case that the photosensitive element 5 works in the second working mode, the sample and hold module 1 is used to output the first sampling signal to the first operational amplifier follow-up circuit 2; the second operational amplifier follow-up circuit 3 is used to acquire the second sampling signal output by the photosensitive element 5.

[0049] The first sampling signal and the second sampling signal are input into the subtraction operation circuit 4 for subtraction operation; and the subtraction operation result is output to the signal amplification module 7 for signal gain.

[0050] In the embodiment of the present disclosure, taking the CMOS type photosensitive element as an example, the working phase thereof includes: an integration working state (i.e. the first working mode) and a signal output working state (i.e. the second working mode). In the integration working state, the photosensitive element collects light signals, converts each photon incident on the photosensitive element into corresponding electric charges, and stores the electric charges on the photosensitive element; in the signal output working state, the photosensitive element transfers the stored electric charges and transmits them out through the output end of the photosensitive element.

[0051] Further, in the case that the photosensitive element 5 is in the integration working state, the output end of the photosensitive element 5 outputs the first sampling signal (i.e. the bias voltage); in the case that the photosensitive element 5 is in the signal output working state, the output end of the photosensitive element 5 outputs the second sampling signal (i.e. the photoelectric sensing signal containing the bias voltage and the effective signal).

[0052] ​The input end of the sample and hold module 1 receives the output signal of the photosensitive element 5, in the case that the photosensitive element 5 is in the integral working state, the sample and hold module 1 obtains the first sample signal output by the photosensitive element 5 and stores the bias voltage; in the case that the photosensitive element 5 is in the signal output working state, the sample and hold module 1 disconnects the connection with the output end of the photosensitive element 5, and uses the stored bias voltage to maintain the output of the bias voltage. The input end of the second operational amplifier follow-up circuit 3 receives the second sample signal of the photosensitive element 5, and samples the second sample signal output by the photosensitive element 5 in real time.

[0053] Further, the first operational amplifier follow-up circuit 2 is connected with the output end of the sample and hold module 1, and transmits the signal output by the sample and hold module 1 to the subtraction operation circuit 4; the second operational amplifier follow-up circuit 3 transmits the output signal sampled from the output end of the photosensitive element 5 to the subtraction operation circuit.

[0054] Further, the subtraction operation circuit 4 performs subtraction operation on the signals transmitted by the first operational amplifier follow-up circuit 2 and the second operational amplifier follow-up circuit 3, obtains the subtraction operation result (i.e. the second sample signal in which the bias voltage is eliminated), and transmits this signal to the signal amplification module 7 to amplify the signal.

[0055] Compared with the signal gain circuit provided by the background art as shown in the background art, Figure 2 the signal gain circuit provided by the embodiment of the present disclosure eliminates the bias voltage in the second sample signal through the subtraction operation circuit 4, provides a larger dynamic range for the effective signal in the second sample signal, and facilitates the amplification circuit to further amplify the effective signal.

[0056] In still another embodiment of the present disclosure, a control module 6 is further included.

[0057] The sample and hold module 1 includes a switch chip 101, a first resistor 102 and a first capacitor 103, as shown in Figure 3

[0058] The first end of the switch chip 101 receives the output signal of the photosensitive element 5; the second end of the switch chip 101 is connected with one end of the first resistor 102, the other end of the first resistor 102 and one end of the first capacitor 103 are connected with the input end of the first operational amplifier follow-up circuit 2; the other end of the first capacitor 103 is grounded; and the control end of the switch chip 101 is used to receive the control signal of the control module 6;

[0059] In the case that the photosensitive element 5 works in the first working mode, the control signal instructs the switch chip 101 to be turned on, and the first capacitor 103 obtains and stores the first sample signal;

[0060] ​In the case that the photosensitive element 5 works in the second working mode, the control signal instructs the switch chip 101 to be turned off, and the first capacitor 103 outputs the stored first sampling signal to the first operational amplifier follow-up circuit 2.

[0061] In the embodiment of the present disclosure, the switch chip 101 in the sample and hold module 1 is controlled by the control signal sent by the control module 6 to be turned on in the case that the photosensitive element 5 is in the integration working state, and the capacitor in the sample and hold module 1 stores the bias voltage.

[0062] Further, the switch chip 101 in the sample and hold module 1 is controlled by the control signal to be turned off in the case that the photosensitive element 5 is in the signal output working state, and the capacitor in the sample and hold module 1 outputs the bias voltage.

[0063] Further, according to the capacitor charging and discharging model, the capacitor charging constant τ = R1×C1, wherein R1 is the resistance value of the first resistor 102, and C1 is the capacitance value of the first capacitor 103. The capacitor charging constant τ is the time required for the voltage across the capacitor to reach 0.63 times the maximum value. When the charging time is 2-3 times τ or more, the capacitor charging reaches the target value. That is, when the duration of the integration working state is greater than 2-3 times τ, the sample and hold module 1 can store the target bias voltage.

[0064] We can get that V in = V out , and the sample and hold module 1 can completely output the stored bias voltage, wherein V in is the input bias voltage, and V out is the output bias voltage.

[0065] In the process of circuit design, according to the lower limit of the integration working state time of the photosensitive element, the values of R1 and C1 corresponding thereto can be obtained.

[0066] In yet another embodiment of the present disclosure, the signal gain circuit further comprises a control module 6.

[0067] The clock CLK end and the start ST end of the photosensitive element 5 are connected to the control module 6 respectively;

[0068] The control module 6 is configured to send a clock pulse signal to the CLK end and send a start pulse signal to the ST end, so as to control the photosensitive element 5 to switch between the first working mode and the second working mode through the start pulse signal.

[0069] The control module 6 is further configured to generate corresponding control signals according to different working stages of the photosensitive element 5 and send the control signals to the sample and hold module 1.

[0070] In the embodiment of the present disclosure, the working state of the photosensitive element 5 is controlled by the control module 6 through the clock pulse period signal and the start pulse period signal.

[0071] The control module 6 sends a start pulse signal, and after the photosensitive element 5 receives the high level of the start pulse signal, it enters the integration working state after a preset number of clock periods; after the photosensitive element 5 receives the low level of the start pulse signal, it enters the signal output working state after a preset number of clock periods. The control method of the start pulse signal on the photosensitive element 5 is only illustrative, and is not limited here.

[0072] After the photosensitive element 5 enters the integration working state, the control module 6 controls the switch chip 101 in the sample and hold module 1 to close; after the photosensitive element 5 enters the signal output working state, the control module 6 controls the switch chip 101 in the sample and hold module 1 to turn off.

[0073] In another embodiment of the present disclosure, as shown in Figure 4 The signal amplification module 7 includes: a signal amplification circuit 710, a differential amplification circuit 720, and a voltage division calculation circuit 730.

[0074] The input end of the signal amplification circuit 710 is connected with the output end of the subtraction operation circuit 4; the output end of the signal amplification circuit 710 is connected with the positive input end of the differential amplification circuit 720, and outputs an amplified signal to the differential amplification circuit 720.

[0075] The negative input end of the differential amplification circuit 720 is connected with the output end of the voltage division calculation circuit 730, receives a bias signal output by the voltage division calculation circuit 730, and amplifies the amplified signal and the bias signal based on the common-mode voltage, respectively, to generate a differential signal based on the amplified signal and the bias signal.

[0076] The differential signal is used to be output to the control module 6 for subsequent processing after being subjected to analog-to-digital conversion by the analog-to-digital conversion circuit 8; and the value of the bias signal is obtained from the control module 6 through the communication end of the voltage division calculation circuit 730.

[0077] In the embodiment of the present disclosure, the subtraction operation result obtained through the subtraction operation circuit 4 is a single-ended signal; the single-ended signal is amplified by a preset multiple through the signal amplification circuit 710 to output an amplified signal.

[0078] Further, the amplified signal is input to the positive input end of the differential amplification circuit 720, and a preset bias signal obtained through the voltage division circuit is input to the negative input end of the differential amplification circuit 720, and the common-mode input end of the differential amplification circuit 720 inputs a common-mode voltage to convert the amplified signal into a differential signal and amplify it by a preset multiple.

[0079] Further, the preset bias signal is obtained by the voltage division calculation circuit 730, the preset bias signal is set by the control module 6 and transmitted to the voltage division calculation circuit 730; the preset bias signal is half of the maximum value of the obtained amplification signal. The voltage division calculation circuit 730 can be a digital potentiometer and a supporting circuit or a digital-to-analog converter and a supporting circuit; the voltage division calculation circuit 730 converts the bias signal into a bias signal input into the differential amplification circuit 720.

[0080] Compared with the prior art, the bias signal configuration method provided in the embodiment of the present disclosure realizes digitalization and improves production efficiency.

[0081] The controller involved in the embodiment of the present disclosure provides a plurality of control functions, which can be implemented by the same device or different devices, and is set according to actual needs, which is not limited here.

[0082] In another embodiment of the present disclosure, the first operational amplifier follower circuit 2 comprises: a first operational amplifier;

[0083] The positive input end of the first operational amplifier is connected with the output end of the sample and hold module 1; the output end of the first operational amplifier is connected with the reverse output end; and the output end of the first operational amplifier is connected with the subtraction operation circuit 4.

[0084] In the embodiment of the present disclosure, the first operational amplifier follower circuit 2 is used to output the bias voltage output by the sample and hold circuit to the subtraction operation circuit 4, and also serves to reduce signal loss, isolate the front and rear circuits, and eliminate the influence of the front and rear circuits.

[0085] In another embodiment of the present disclosure, the second operational amplifier follower circuit 3 comprises: a second operational amplifier; the positive input end of the second operational amplifier receives the output signal of the photosensitive element 5; the output end of the second operational amplifier is connected with the reverse output end; and the output end of the second operational amplifier is connected with the subtraction operation circuit 4.

[0086] In the embodiment of the present disclosure, the second operational amplifier follower circuit 3 is used to output the second sampling signal of the photosensitive element 5 to the subtraction operation circuit 4, and also serves to reduce signal loss, isolate the front and rear circuits, and eliminate the influence of the front and rear circuits.

[0087] In another embodiment of the present disclosure, the subtraction operation circuit 4 comprises: a third operational amplifier;

[0088] The third operational amplifier positive input end is connected with the second operational amplifier follow-up circuit 3 output end; the third operational amplifier reverse input end is connected with the first operational amplifier follow-up circuit 2 output end; the third operational amplifier output end is connected with the reverse input end through parallel connection of a capacitor and a resistor; and the third operational amplifier output end outputs a subtraction operation result.

[0089] In the embodiment of the present disclosure, the subtraction operation circuit 4 performs subtraction operation on the second sampling signal of the photosensitive element 5 and the bias voltage output by the sampling follow-up circuit through the third operational amplifier, so as to remove the bias voltage in the second sampling signal.

[0090] Further, when the photosensitive element 5 is in the integral working state, the signal output by the photosensitive element 5 only includes the bias voltage; the first sampling signal output by the sampling holding module 1 through the first operational amplifier follow-up circuit 2 is the same as the second sampling signal obtained through the second operational amplifier follow-up circuit 3; and after calculation by the subtraction operation circuit 4, zero is output.

[0091] Further, when the photosensitive element 5 is in the signal output working state, the photosensitive element 5 outputs the second sampling signal including the bias voltage and the effective signal; the sampling holding module 1 is disconnected by the switch chip 101, the sampling holding module 1 outputs the stored bias voltage, and after subtraction operation, the subtraction operation result (i.e. the second sampling signal from which the bias voltage is removed) is output.

[0092] In still another embodiment of the present disclosure, as shown in Figure 5 The signal amplification circuit 710 includes: a fourth operational amplifier 711, a second resistor 712, and a third resistor 713.

[0093] The fourth operational amplifier 711 positive input end is connected with the subtraction operation circuit 4 output end; the fourth operational amplifier 711 reverse input end is connected with the output end through parallel connection of a capacitor and the second resistor 712; the fourth operational amplifier 711 reverse input end is grounded through the third resistor 713; and the fourth operational amplifier 711 output end outputs an amplified signal.

[0094] In the embodiment of the present disclosure, the signal amplification circuit 710 amplifies the input subtraction operation result by a preset multiple, and the amplification multiple is determined based on the second resistor 712 and the third resistor 713. The signal amplification circuit 710 amplification multiple Wherein, R2 is the resistance value of the second resistor 712, and R3 is the resistance value of the third resistor 713. Taking R2=R3=499Ω as an example, the signal amplification circuit 710 amplification multiple λ1=2, and the subtraction operation result obtains 2 times gain after being amplified by the signal amplification circuit 710.

[0095] In still another embodiment of the present disclosure, as shown in Figure 6As shown, the differential amplification circuit 720 comprises: a differential driver 721, a fourth resistor 722, a fifth resistor 723, a sixth resistor 724, and a seventh resistor 725.

[0096] The positive input port of the differential driver 721 is connected to the output end of the signal amplification circuit 710 through the fourth resistor 722; and the negative output port of the differential driver 721 is connected to the positive input port of the differential driver 721 through the fifth resistor 723.

[0097] The negative input port of the differential driver 721 is connected to the output port of the voltage division calculation circuit 730 through the sixth resistor 724; and the positive output port of the differential driver 721 is connected to the negative input port of the differential driver 721 through the seventh resistor 725.

[0098] The positive output of the differential driver 721 and the negative output of the differential driver 721 are connected to the analog-to-digital conversion circuit 8.

[0099] In the embodiment of the present disclosure, the amplified signal and the bias signal obtained based on the maximum value of the amplified signal are input into the differential driver, the common-mode input voltage is combined, the amplified signal is converted into a differential signal and amplified. The differential amplification factor wherein R4 is the resistance value of the fourth resistor 722, R5 is the resistance value of the fifth resistor 723, R6 is the resistance value of the sixth resistor 724, and R7 is the resistance value of the seventh resistor 725.

[0100] For example, R4 = R6 = 499Ω, R5 = R7 = 1000Ω, and the differential amplification factor λ2 ≈ 2.

[0101] The differential signal output by the differential driver is transmitted to the analog-to-digital conversion circuit 8, which performs subsequent processing.

[0102] In another embodiment of the present disclosure, the voltage division calculation circuit 730 comprises: an analog-to-digital conversion chip and a fifth operational amplifier.

[0103] The communication port of the analog-to-digital conversion chip is connected to the communication port of the control module; the analog-to-digital conversion chip outputs a bias signal under the control of the control module through the communication port of the analog-to-digital conversion chip; the output port of the analog-to-digital conversion chip is connected to the positive input end of the fifth operational amplifier, and outputs the bias signal; the output end of the fifth operational amplifier is connected to the negative input end of the fifth operational amplifier; and the output end of the fifth operational amplifier is connected to the differential amplification circuit 720, and the bias signal sampled by the fifth operational amplifier is input into the differential amplification circuit 720.

[0104] In the embodiment of the present disclosure, the analog-digital conversion chip is controlled by the control module 6 through the communication port, and converts the digital signal transmitted by the control module 6 into an analog signal that can be input into the differential amplification circuit 720. The bias signal value output by the voltage division calculation circuit 730 is half of the maximum value of the amplified signal obtained by the control module 6, and the bias signal is used to convert the amplified signal into a differential signal.

[0105] In yet another embodiment of the present disclosure, the first working mode includes an integration working state of the photosensitive element 5, and the second working mode includes a signal output working state of the photosensitive element 5.

[0106] In the embodiment of the present disclosure, the photosensitive element 5 outputs a bias voltage in the integration working state of the photosensitive element 5, and outputs a second sampling signal in the signal output working state of the photosensitive element 5, the second sampling signal containing an effective signal and a bias voltage.

[0107] The embodiment of the present disclosure provides an electronic device, which includes the signal gain circuit according to any one of the above embodiments.

[0108] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments of the present disclosure can be implemented by hardware, or can be implemented by means of software and a necessary general hardware platform. Based on such understanding, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a U disk, a mobile hard disk, etc.), and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments of the present disclosure.

[0109] Those skilled in the art can understand that the drawings are only schematic diagrams of a preferred embodiment, and the modules or flows in the drawings are not necessarily required for implementing the present disclosure.

[0110] Those skilled in the art can understand that the modules in the device in the embodiments can be distributed in the device in the embodiments according to the description of the embodiments, or can be changed and located in one or more devices different from the embodiments. The modules of the above embodiments can be combined into one module, or can be further split into a plurality of sub-modules.

[0111] The above serial numbers of the embodiments of the present disclosure are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0112] Obviously, those skilled in the art can make various modifications and changes to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and changes of the present disclosure belong to the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and changes.

Claims

1. A signal gain circuit, characterized by, The application relates to a signal processing circuit. The signal processing circuit comprises a sampling and holding module, a first operational amplifier follower circuit, a second operational amplifier follower circuit, a subtraction operation circuit and a signal amplification module. The input end of the sampling and holding module and the input end of the second operational amplifier follower circuit receive output signals of a photosensitive element respectively. When the photosensitive element works in a first working mode, the sampling and holding module is used for acquiring and storing a first sampling signal output by the photosensitive element. When the photosensitive element works in a second working mode, the sampling and holding module is used for outputting the first sampling signal to the first operational amplifier follower circuit. The second operational amplifier follower circuit is used for acquiring a second sampling signal output by the photosensitive element.

2. The circuit of claim 1, wherein, The first sampling signal and the second sampling signal are input to the subtraction operation circuit to perform subtraction operation, and the subtraction operation result is output to the signal amplification module to perform gain on the signal. The signal processing circuit further comprises a control module. The sampling and holding module comprises a switch chip, a first resistor and a first capacitor. The first end of the switch chip receives the output signal of the photosensitive element. The second end of the switch chip is connected with one end of the first resistor. The other end of the first resistor and one end of the first capacitor are connected with the input end of the first operational amplifier follower circuit.

3. The circuit of claim 1, wherein, The other end of the first capacitor is grounded. The control end of the switch chip is used for receiving a control signal of the control module. When the photosensitive element works in the first working mode, the control signal indicates that the switch chip is turned on, and the first capacitor acquires and stores the first sampling signal. When the photosensitive element works in the second working mode, the control signal indicates that the switch chip is turned off, and the first capacitor outputs the stored first sampling signal to the first operational amplifier follower circuit. The signal processing circuit further comprises a control module. The clock CLK end and the start ST end of the photosensitive element are connected with the control module respectively.

4. The circuit of claim 1, wherein, The control module is used for sending a clock pulse signal to the CLK end. The control module is also used for generating a corresponding control signal according to different working stages of the photosensitive element and sending the control signal to the sampling and holding module. The signal amplification module comprises a signal amplification circuit, a differential amplification circuit and a voltage division calculation circuit. The input end of the signal amplification circuit is connected with the output end of the subtraction operation circuit. The output end of the signal amplification circuit is connected with the positive input end of the differential amplification circuit. The negative input end of the differential amplification circuit is connected with the output end of the voltage division calculation circuit. The differential amplification circuit amplifies the amplified signal and the bias signal based on the common-mode voltage and generates a differential signal based on the amplified signal and the bias signal. The differential signal is used for outputting after analog-digital conversion by the analog-digital conversion circuit for subsequent processing; the bias signal is obtained from the control module through the communication end of the voltage division calculation circuit.

5. The circuit of claim 1, wherein, The first operational amplifier following circuit comprises a first operational amplifier; The positive input end of the first operational amplifier is connected with the output end of the sample and hold module; the output end of the first operational amplifier is connected with the reverse output end; the output end of the first operational amplifier is connected with the subtraction operation circuit.

6. The circuit of claim 1, wherein, The second operational amplifier following circuit comprises a second operational amplifier; The positive input end of the second operational amplifier receives the output signal of the photosensitive element; the output end of the second operational amplifier is connected with the reverse output end; the output end of the second operational amplifier is connected with the subtraction operation circuit.

7. The circuit of claim 1, wherein, The subtraction operation circuit comprises a third operational amplifier; The positive input end of the third operational amplifier is connected with the output end of the second operational amplifier following circuit; the reverse input end of the third operational amplifier is connected with the output end of the first operational amplifier following circuit; the output end of the third operational amplifier is connected with the reverse input end through the parallel connection of a capacitor and a resistor; the output end of the third operational amplifier outputs the subtraction operation result.

8. The circuit of claim 4, wherein, The signal amplification circuit comprises a fourth operational amplifier, a second resistor and a third resistor; The positive input end of the fourth operational amplifier is connected with the output end of the subtraction operation circuit; the reverse input end of the fourth operational amplifier is connected with the output end through the parallel connection of a capacitor and a second resistor; the reverse input end of the fourth operational amplifier is connected with the ground through a third resistor; the positive and negative poles of the fourth operational amplifier are connected with the positive and negative poles of the operational amplifier power supply respectively; the output end of the fourth operational amplifier outputs the amplified signal.

9. The circuit of claim 4, wherein, The differential amplification circuit comprises a differential driver, a fourth resistor, a fifth resistor, a sixth resistor and a seventh resistor; The positive input end of the differential driver is connected with the output end of the signal amplification circuit through the fourth resistor; the negative output end of the differential driver is connected with the positive input end of the differential driver through the fifth resistor; The negative input end of the differential driver is connected with the output end of the voltage division calculation circuit through the sixth resistor; the positive output end of the differential driver is connected with the negative input end of the differential driver through the seventh resistor; The positive output end and the negative output end of the differential driver are connected with the analog-digital conversion circuit.

10. The circuit of claim 4, wherein, The voltage division calculation circuit comprises an analog-digital conversion chip and a fifth operational amplifier; The communication port of the analog-digital conversion chip is connected with the communication port of the control module; the analog-digital conversion chip outputs the bias signal controlled by the control module through the communication port of the analog-digital conversion chip; the output port of the analog-digital conversion chip is connected with the positive input end of the fifth operational amplifier, and outputs the bias signal; the output end of the fifth operational amplifier is connected with the reverse input end of the fifth operational amplifier; the output end of the fifth operational amplifier is connected with the differential amplification circuit, and the bias signal sampled by the fifth operational amplifier is input into the differential amplification circuit.

11. The circuit of any one of claims 1-3, wherein, The first working mode comprises an integration working state of the photosensitive element; and the second working mode comprises a signal output working state of the photosensitive element.

12. An electronic device, comprising: Comprising: The signal gain circuit of any one of claims 1-11.

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