Digital isolation automatic transmit-receive RS485 circuit
By replacing transistors and high-speed optocouplers in traditional RS485 circuits with digital isolation chips and NOT gate logic devices, the problems of long transmission delay and high cost are solved, achieving low-cost, high-speed and accurate signal transmission.
Patent Information
- Application Number
- CN202520051313.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-09
- Publication Date
- 2025-12-05
- Estimated Expiration
- 2035-01-09
AI Technical Summary
Existing RS485 transceiver circuits suffer from problems such as long transmission delay and high cost, especially the high transmission delay of transistors and the high price of high-speed optocouplers.
Digital isolation chips and NOT gate logic devices are used to replace traditional transistors and high-speed optocouplers. The automatic transmission and reception function of RS485 circuit is realized through digital isolation chips and NOT gate logic devices, and the bus level is controlled by pull-up resistors and pull-down resistors.
It reduced circuit costs, improved signal transmission speed and accuracy, and achieved error-free transmission.
Smart Images
Figure CN223639261U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to electronic communication signal technical field, in particular to a kind of digital isolation automatic transceiving RS485 circuit. BACKGROUND
[0002] RS485 is a balanced transmission standard widely used in industrial field.RS485 communication standard defines electrical characteristics, mechanical characteristics, functional characteristics and process characteristics, and is particularly suitable for long distance and multipoint communication.RS485 provides long distance, high speed communication capability with differential transmission, and is commonly used in industrial automation and other fields.
[0003] The current common RS485 transceiving automatic reversing scheme usually uses triode to build reverse circuit, and simultaneously uses high-speed optocoupler to isolate communication signal, to enhance anti-interference capability.But the transmission delay of triode is high, and only low-speed communication can be met.In addition, high-speed optocoupler is expensive, and the cost is high.Therefore, it is very necessary to develop a kind of digital isolation automatic transceiving RS485 circuit. UTILITY MODEL CONTENT
[0004] In view of the problems in the prior art, the utility model provides a kind of digital isolation automatic transceiving RS485 circuit with low cost, signal transmission is fast and accurate.
[0005] To achieve the above purpose, the technical scheme adopted by the utility model is: a kind of digital isolation automatic transceiving RS485 circuit, including digital isolation chip, NAND gate logic device and 485 control chip, the input of the NAND gate logic device is connected with the VO2 pin of the digital isolation chip, the output of the NAND gate logic device is connected with the RE, DE pin of the 485 control chip, the output A, B of the 485 control chip is connected with A, B bus respectively, the output A is connected with 5V isolation area power supply voltage through pull-up resistor, and the output B is connected with isolation area ground wire through pull-down resistor R2.
[0006] Based on the above, using digital isolation chip instead of traditional high-speed optocoupler, while ensuring anti-interference capability, make circuit more simple, reduce manufacturing cost.TXD signal is isolated through the digital isolation chip, and then input to the RE, DE pin of the 485 control chip through the NAND gate logic device, and the A, B bus is pulled up to ISO5V and pulled down to ISOGND through the pull-up resistor and the pull-down resistor respectively, so that the initial state of the A, B bus maintains high level.The automatic transceiving function of RS485 circuit is realized by NAND gate logic device, compared with traditional signal transmission through triode, has higher transmission speed, can stably transmit data, realizes error-free transmission.
[0007] Furthermore, the VDDA pin of the digital isolation chip is connected to a 3.3V power supply voltage, the GNDA pin is connected to ground, the VO1 pin is connected to the RXD signal, the VI2 pin is connected to the TXD signal, the VDDB pin is connected to the 5V isolation zone power supply voltage, the VI1 pin is connected to the RO terminal of the 485 control chip, and the CNDB pin is connected to the isolation zone ground.
[0008] To more clearly illustrate the above-mentioned features of this utility model and the objectives it aims to achieve, the present utility model will be further described below in conjunction with the accompanying drawings and specific embodiments. Attached Figure Description
[0009] Figure 1 This is the circuit schematic diagram of this utility model. Detailed Implementation
[0010] like Figure 1 As shown, a digitally isolated automatic RS485 transceiver circuit includes a digital isolation chip U1, a NOT gate logic device U2, and an RS485 control chip U3. The input terminal of the NOT gate logic device U2 is connected to the VO2 pin of the digital isolation chip U1, and the output terminal of the NOT gate logic device U2 is connected to the RE and DE pins of the RS485 control chip U3. The output A and output B terminals of the RS485 control chip U3 are respectively connected to the A and B buses. The output A terminal is connected to the 5V isolation zone power supply voltage through a pull-up resistor R1, and the output B terminal is connected to the isolation zone ground through a pull-down resistor R2.
[0011] The digital isolation chip U1 has its VDDA pin connected to a 3.3V power supply, its GNDA pin connected to ground GND, its VO1 pin connected to the RXD signal, its VI2 pin connected to the TXD signal, its VDDB pin connected to the 5V isolation zone power supply, its VI1 pin connected to the RO terminal of the 485 control chip U3, and its CNDB pin connected to the isolation zone ground.
[0012] Working principle: When the link is in the transmitting state:
[0013] TXD sends a high level 1, which becomes a low level 0 after passing through the NOT gate logic device U2. The 485 control chip U3 is in the receiving state and is in a high impedance state. The A and B buses are pulled up by pull-up resistor R1 and pulled down by pull-down resistor R2, respectively. The voltage between the A and B buses is greater than 0, realizing the transmission of high level 1.
[0014] When TXD sends a low level 0, it becomes a low level 1 after passing through the NOT gate logic device U2. The 485 control chip U3 is in the transmitting state, and the DI terminal of the 485 control chip U3 is grounded, which is equivalent to a low level 0. The voltage between the A and B buses is equal to 0, realizing the transmission of low level 0.
[0015] The above merely describes the best solution embodiment of the present application, and is not used to limit the present application. Various modifications or replacements of the present application made by those skilled in the art without departing from the essence and protection scope of the present application shall be within the protection scope of the present application.
Claims
1. A digital isolated auto-receive RS485 circuit, characterized in that: It includes digital isolation chip (U1), NOT gate logic device (U2) and 485 control chip (U3), the input of the NOT gate logic device (U2) is connected with the VO2 pin of the digital isolation chip (U1), the output of the NOT gate logic device (U2) is connected with the RE, DE pin of the 485 control chip (U3), the output A end and the output B end of the 485 control chip (U3) are connected with A, B bus respectively, the output A end is connected with 5V isolation area power voltage through pull-up resistor (R1), the output B end is connected with isolation area ground wire through pull-down resistor (R2).
2. The digital isolated automatic transceiver RS485 circuit according to claim 1, wherein: The VDDA pin of the digital isolation chip (U1) is connected with 3.3V power voltage, the GNDA pin is connected with ground wire (GND), the VO1 pin is connected with RXD signal, the VI2 pin is connected with TXD signal, the VDDB pin is connected with 5V isolation area power voltage, the VI1 pin is connected with the RO end of the 485 control chip (U3), the CNDB pin is connected with isolation area ground wire.