Arrangement having alternating rows of respective first and second row architectures

Abstract

An apparatus comprising: an alternating plurality of first and second rows, respectively comprising a plurality of first cell regions and a plurality of second cell regions, each of the first and second cell regions respectively comprising an active region; in the first metallization layer over the active region, each of the first cell region and the second cell region includes first and second grid (PG) segments and one or more routing (RTE) segments; in the first buried metallization layer under the active region, each first cell region includes first and second buried PG (BPG) segments, and each second cell region includes one or more buried local interconnect (BLI) structures, and each first cell region does not include a BLI structure.

Description

TECHNICAL FIELD

[0001] The utility model relates to a device with corresponding first and second row structures of alternate rows. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry fabricates various analog and digital devices to solve problems in many different fields. The development of semiconductor process technology nodes has gradually reduced the size of elements and shrunk the pitch, thereby gradually increasing the transistor density. ICs are becoming smaller and smaller. SUMMARY

[0003] According to an embodiment of the utility model, a device includes: a plurality of first rows and a plurality of second rows alternating, respectively including a plurality of first cell regions and a plurality of second cell regions; each first cell region and second cell region correspondingly includes a plurality of active regions; in a first metallization layer above the active regions: each of the first cell regions and the second cell regions includes: first and second power grid (PG) segments and one or more routing (RTE) segments; in a first buried metallization layer below the active regions: each first cell region includes: first and second buried power grid (BPG) segments; each second cell region includes: one or more buried local interconnect (BLI) structures; each first cell region does not include a BLI structure.

[0004] According to another embodiment of the utility model, a device includes: a plurality of first rows and a plurality of second rows alternating, respectively including a plurality of first cell regions and a plurality of second cell regions; each first cell region and second cell region correspondingly includes a plurality of active regions; in a first metallization layer above the active regions: each of the first cell regions and the second cell regions includes: first and second power grid (PG) segments and one or more routing (RTE) segments; in a first buried metallization layer below the active regions: each first cell region includes: first and second buried power grid (BPG) segments; each second cell region includes: one or more buried local interconnect (BLI) structures; each first cell region does not include a BLI structure; and in at least one second cell region, a shape of at least one of the one or more buried BLI structures is different from a smallest rectangular shape of instances of the one or more buried BLI structures, the smallest rectangular shape having a smallest width of a conductive segment in the first buried metallization layer. BRIEF DESCRIPTION OF DRAWINGS

[0005] One or more embodiments are illustrated by way of example in the drawings and described in detail below in connection with embodiments thereof. Those skilled in the art will readily recognize that the embodiments described herein are merely illustrative and should not be taken as limiting the scope of the application. Unless otherwise expressly specified, the drawings are not drawn to scale.

[0006] Figure 1A-1C is a corresponding layout diagram of a device according to some embodiments.

[0007] Figure 2A-2C is a corresponding layout view of a corresponding device according to some embodiments.

[0008] Figures 3A-3F is a corresponding layout view of a corresponding device according to some embodiments.

[0009] Figures 4A-4F is a corresponding layout view of a corresponding device according to some embodiments.

[0010] Figure 5A is a corresponding schematic circuit diagram according to some embodiments.

[0011] Figures 5B-5C is a corresponding layout view of a corresponding device according to some embodiments.

[0012] Figure 6 and Figures 7A-7B is a corresponding flow diagram of a corresponding method of manufacturing a memory device according to some embodiments.

[0013] Figure 8 is a corresponding block diagram of an electronic design automation (EDA) system according to some embodiments.

[0014] Figure 9 is a corresponding block diagram of an integrated circuit (IC) fabrication system and an IC fabrication flow associated therewith according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure discloses many different embodiments or examples of different features used to implement the present application. The examples of components, materials, values, steps, operations, arrangements, etc. are set forth in the following description and are illustrative only. They are not intended to be limiting in any way. Other components, values, operations, materials, arrangements, etc. can be used. For example, the formation of a first feature over or on a second feature in the following description refers to the first feature being formed directly on the second feature or alternatively that there can be one or more additional features formed between the first and second features such that the first and second features are indirectly connected. Also, the present disclosure repeats the use of the phrase "example of" any array of features throughout the specification. This is done for the purpose of liberaiy and clarity and indicates that the described example is one of a possible array of alternatives. The different instances of this phrase do not imply that a process or method would be loosed to operate only with the described example, but that the example is one of a possible array.

[0016] Moreover, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In some embodiments, the term "standard cell structure" refers to a standardized building block included in a library of various standard cell structures. In some embodiments, various standard cell structures are selected from their library and used as elements in a layout map representing a circuit.

[0017] In some embodiments, an apparatus includes: alternating first and second rows, respectively including first and second cell regions, each of the first and second cell regions respectively including an active region; in a first metallization layer over the active region, each of the first and second cell regions includes first and second power grid (PG) segments and one or more routing (RTE) segments; in a first buried metallization layer under the active region, each first cell region includes first and second buried power grid (BPG) segments, and each second cell region includes one or more buried local interconnect (BLI) structures; each first cell region does not include a BLI structure.

[0018] Another approach is to not use the BM0 LI structure, which results in a M0 rte segment contention problem, i.e., a M0 routability congestion problem. Another approach is to alleviate the M0 routability congestion problem by making a given cell region wider, i.e., increasing the pitch of the given cell region. However, widening a cell region to reduce M0 routability congestion has the disadvantage of reducing the cell region density of an apparatus including the widened cell region. At least some embodiments provide, in contrast, the BM0 LI structure in even rows according to the architectures of the alternating row-arrangements disclosed herein, which has the benefit of reducing M0 routability congestion compared to other approaches and the benefit of not having to increase the cell pitch.

[0019] Figure 1A is a layout map of an apparatus 100A according to some embodiments.

[0020] Figure 1ALayouts of the type representative of transistor-based devices, such as semiconductor devices. Structures in a device are represented by patterns (also referred to as shapes) in a layout. For simplicity of discussion, Figure 1A Components in a layout of the type (and components in other layouts disclosed herein) will be considered structures rather than patterns per se. For example, Figure 1A An instance of pattern 112 in FIG. 1 represents an instance of an M0 wire segment. In the following discussion, the instance of component 112 is referred to as an instance of M0 wire segment 112 rather than an instance of M0 routing pattern.

[0021] In Figure 1A and other layouts disclosed herein, an orthogonal Cartesian coordinate system is assumed in which a first direction is parallel to an X-axis, a second direction is parallel to a Y-axis, and a third direction is parallel to a Z-axis. The layout itself is a top view. Shapes in the layout are two-dimensional with respect to, for example, the X-axis and the Y-axis, while the represented device is three-dimensional. Accordingly, shapes in such a layout are described as having a width / length with respect to the X-axis and a height with respect to the Y-axis. With respect to the Z-axis, a front face of the represented device is stacked on a back face of the device. In some embodiments, the first through third directions correspond to directions other than the X-axis, the Y-axis, and the Z-axis.

[0022] Generally, with respect to the Z-axis, the device is organized as a stack of layers in which respective structures are located, i.e., belong. More specifically, each shape in the layout represents a component in a respective layer of the respective device. Also, generally, a layout represents relative depths, i.e., positions along the Z-axis, of shapes and corresponding layers by superimposing a second shape on a first shape such that the second shape at least partially overlaps the first shape. Some structures are stacked along the Z-axis in the layout; however, to simplify the illustration, the order of the stack along the Z-axis is distorted with respect to the respective device in some respects. For example, in Figure 1A-1C In FIG. 1, BM0 LI structures 120(1)-120(x) are shown above respective instances of BVG contact 122 and BVD contact 124.

[0023] In Figure 1A FIG. 2, cross-section line IIA-IIA' and cross-section line IIB-IIB' both extend parallel to the Y-axis. Cross-section line IIA-IIA' corresponds to cross-sectional view 225A of FIG. 2A. Cross-section line IIB-IIB' corresponds to cross-sectional view 225B of FIG. 2B. Figure 2A Figure 2B

[0024] ​​The layout diagrams differ in the amount of detail represented. In some cases, for example, for simplicity purposes, selected layers of the layout diagram are combined / extracted as a single layer. Alternatively and / or additionally, in some cases, not all layers of the respective semiconductor device are shown, i.e., selected layers of the layout diagram are omitted, for example, for simplicity of illustration. Alternatively, and / or additionally, in some cases, not all elements of a given depicted layer of the respective semiconductor device are represented, i.e., selected elements of the given depicted layer of the layout diagram are omitted, for example, for simplicity of illustration. Figure 1A The layout diagrams disclosed herein are examples of layout diagrams in which selected layers and / or selected elements of a given depicted layer are omitted. In some embodiments, Figure 1A The layout diagram of

[0025] With respect to Figure 1A , and more generally for the disclosure, the numbering convention is assumed as follows: the first metallization layer above the active area of the transistor Figure 2A-2B is numbered as layer zero and is referred to as layer MET0; the first interconnect layer above the MET0 layer (not shown) is referred to as VIA0 layer; the first metallization layer below the active area of the transistor Figure 2A-2B , i.e., the first buried layer, is numbered as buried layer zero and is referred to as layer BMET0; the first interconnect layer below the layer BMET0 (not shown) is referred to as layer BVIA0 (not shown). In some embodiments, in accordance with the numbering convention of the respective process node at which the device is manufactured, the first layer above the active area of the transistor Figure 2A-2B is numbered as the first layer and is referred to as layer MET1, the first layer interconnect above the MET1 layer (not shown) is referred to as layer VIA1, the first metallization layer below the transistor active area Figure 2A-2B is numbered as buried layer one and is referred to as layer BMET1, and the first layer interconnect below the layer BMET0 (not shown) is referred to as layer BVIA1.

[0026] In Figure 1A , the layout diagram shows part 108A and part 110A of device 100A. Part 108A of device 100A represents structures in layer MET0. Part 110A of device 100A represents structures in backside layers, i.e., structures in layers below the active area of the transistor Figure 2A-2B In Figure 1A , for simplicity of illustration, part 108A is shown to the left of part 110A instead of above part 110A. Also, for simplicity of illustration, the dimensions / lengths of the structures in part 108A with respect to the X-axis are truncated.

[0027] The device 100A includes first cell regions and second cell regions. For simplicity of illustration, some but not all instances of the first cell regions are numbered, i.e., 102(1)-102(8). For simplicity of illustration, some but not all of the second cell regions are numbered, i.e., 104(1)-104(7).

[0028] Each first cell region and each second cell region has a width relative to the X-axis and a height relative to the Y-axis, respectively. The device 100A is arranged in rows RW1-RW6 extending parallel to the X-axis.

[0029] Each first cell region and each second cell region is located in a corresponding row of the rows RW1-RW6. Thus, in some embodiments, each of the first cell regions and each of the second cell regions has a height equal to a single row height, and are described as single row height (or single height) cell regions. Only the first cell regions are located in odd rows, i.e., RW1, RW3, and RW5. The second cell regions are located in even rows, i.e., RW2, RW4, and RW6. The second cell regions are excluded from odd rows. In some embodiments, one or more instances of the even rows include one or more first cell regions in addition to the one or more second cell regions, e.g., Figure 1B-1C The row RW8 of Figure 1A The device 100A is described as having an alternating row arrangement architecture, i.e., alternating rows of corresponding first row architecture and second row architecture. In some embodiments, the alternating row arrangement architecture presents a benefit of facilitating coupling one or more nodes in a given second cell region in an even row to a BM0_PG rail (BM0_PGrail) in an adjacent odd row Figure 3D ).

[0030] The first cell region 102(2) is stacked relative to the Y-axis on the second cell region 104(2) and together comprise a high cell region 106(1). The first cell region 102(7) is stacked relative to the Y-axis on the second cell region 104(6) and together comprise a high cell region 106(2). As such, each of the high cell regions 106(1) and 106(2) has a height equal to two single row heights, i.e., double row height, and are described as double row high (or double height) cell regions. In some embodiments, the high cell regions 106(1)-106(2) are described as high cell regions, while the cell regions 102(1)-102(8) and 104(1)-104(7) are described as short cell regions.

[0031] Each of the first cell regions 102(1) and 102(8) represents an INVD4 cell region. In some embodiments, INVD4 is an alphanumeric text string used as an adjective, designed to indicate that each of the first cell regions 102(1) and 102(8) is an inverter cell region for which the current drive / source current intensity of the cell region is 4D, where D is a unit of driving strength. In some embodiments, the value of the unit driving strength D is determined by, for example, the design rules and dimensions of the corresponding semiconductor process technology node.

[0032] Unit 1, areas 102(3) and 102(5)-102(6) Figures 3A-3B Each of the units in ) and the second unit regions 104(1) and 104(7) Figure 3C-3D Each of the following represents a BUFFD4 cell region. The first cell region 102(4) represents a BUFFD5 cell region. In some embodiments, BUFFDx is an alphanumeric string used as an adjective designed to indicate that the corresponding cell region is a buffer cell region for which the drive strength is DX, where X is a multiple of the unit drive strength D. Each of the first cell regions 102(3) and 102(5)-102(6) has x = 4, such that the drive strength is D4. The first cell region 102(4) has x = 5, such that the drive strength is D5. The BUFFD4 cell region 104(7) is substantially the same as the BUFFD4 cell region 104(1).

[0033] Each of the second cell regions 104(3) and 104(5) represents an AOI22D1 cell region. In some embodiments, AOID22D1 is an alphanumeric string used as an adjective, designed to indicate that the corresponding cell region is an AND-OR-INVERT cell region, wherein the AND gate portion has two inputs, the OR gate has two inputs, and the drive strength of the cell region is a unit drive strength D. AOI22D1 cell region 104(5) is substantially the same as AOI22D1 cell region 104(3).

[0034] Each of the high cell regions 106(1) and 106(2) and the second cell region 104(4) represents an SDFQD1 cell region. In some embodiments, SDFQD1 is an alphanumeric literal used as an adjective designed to indicate that the corresponding cell region is of the type of a D flip-flop (FF), i.e., a scan-insertion D FF (SDFQ) with a drive strength of unit drive strength D. In some embodiments, a SDFQ cell region is used, for example, to implement a design for testing (DFT). An SDFQ is a D flip-flop that includes a multiplexer for controllably selecting between an input D during normal operation and a scan input during scan / test operation. Scan flip-flops, such as SDFQs, are used for device testing.

[0035] The portion 108A of the device 100A includes conductive segments, i.e., instances of M0_PG segments 112 and instances of M0_rte segments 114, that extend parallel to the X axis in the layer MET0. Relative to the Y axis, each instance of the M0_rte segments 114 has a height that is less than a height of each instance of the M0_PG segments 112.

[0036] Relative to the Y axis, each of the top and bottom boundaries of each of the RW1-RW6 rows is crossed by a respective instance of the M0_PG segments 112. Each instance of the M0_PG segments 112 is part of a corresponding track in a power grid (PG) of the device 100A. Thus, each instance of the M0_PG segments 112 is described as an instance of the M0_PG segments 112 and is configured to carry / conduct a respective one of reference voltages of the device 100A, e.g., VDD, VSS, etc. Relative to the Y axis, a top region of each first cell region and each second cell region overlaps with a portion of a respective instance of the M0_PG segments 112. Similarly, a bottom region of each first cell region and each second cell region overlaps with a portion of a respective instance of the M0_PG segments 112.

[0037] In contrast to the M0_PG segments 112, the instances of the M0_rte segments 114 are routing segments that form part of signal paths and are thus configured to carry / conduct respective routing signals for circuits implemented by instances of the first cell regions, instances of the second cell regions, the high cell regions 106(1)-106(2), etc. respectively. Examples of routing signals include input / output (I / O) signals, data signals, control signals, etc. The instances of the M0_rte segments 114 are referred to as M0_rte segments 114. Relative to the Y axis, each instance of the M0_rte segments 114 is narrower / shorter than each instance of the M0_PG segments 112.

[0038] Layer MET0 is organized according to a first grid that includes first reference lines (alpha tracks) that extend parallel to the X-axis (not shown). Instances of M0_rte segments 114 correspond to alignment with the alpha tracks. For a given one of the alpha tracks, one or more instances of M0_rte segments 114 are aligned with the given alpha track and distributed with respect to the X-axis. Whether a given portion of a given alpha track is populated with a given instance of M0_rte segments 114, and the length of the given instance of M0_rte segments 114, with respect to the X-axis, depends on the portion of the corresponding first or second cell region under the given portion.

[0039] Each of the rows RW1-RW6 has four alpha tracks. Thus, each of the corresponding first or second cell regions therein can have (but not necessarily have) one or more instances of M0_rte segments 114 aligned with each of the four alpha tracks of the corresponding row. For simplicity of illustration, with respect to the Y-axis, Figure 1A Adjacent instances of M0_PG segments 112 are shown as being separated by four instances of M0_rte segments 114. In some embodiments, each of the rows RW1-RW4 is described as having an architecture of “four M0_rte segments per row”.

[0040] In Figure 1A , portion 110A represents structures in the backside layer, i.e., structures in the layer under the active region of the transistor Figure 2A-2B Portion 110A includes instances of buried via-to-gate (BVG) contacts 122, instances of buried via-to-MD (BVD) contacts 124, and instances of conductive segments in layer BMET0 that extend parallel to the X-axis, i.e., BM0_PG segments 118 and buried local intra-connect (BM0_LI) structures 120(1)-120(8).

[0041] As intra-connects, each of BM0_LI structures 120(1)-120(8) couples nodes within a given cell region, i.e., on a cell-region-by-cell-region basis. In some embodiments, some of the BM0_LI structures are interconnect structures (not shown) that couple one of the multiple nodes of a first instance of a first cell region to a second instance of the first cell region, i.e., on a cell-region-by-cell-region basis.

[0042] In some embodiments, BVG contacts 122 are contact structures that couple gates Figure 2B to BM0_LI structures. In some embodiments, BVD contacts 124 are contact structures that couple source / drain (S / D) regions Figure 2A ) a contact structure coupled to the BM0 LI structure.

[0043] According to another approach, the BM0 LI structure is not used, which results in a M0 rte segment contention problem, i.e., a M0 routability congestion problem. Another approach is to alleviate the M0 routability congestion problem by making the given cell region wider, i.e., increasing the pitch of the given cell region. However, widening the cell region to reduce the M0 routability congestion has the disadvantage of reducing the cell density of the device including the widened cell region. In contrast, at least some embodiments provide the BM0 LI structure in even rows according to the alternating row arrangement architecture disclosed herein, which has the benefit of reducing the M0 routability congestion compared to other approaches and the benefit of not having to increase the cell pitch.

[0044] With respect to the Y-axis, in each of the first cell regions 102(1)-102(8): the top region overlaps a portion of a respective instance of the BM0 PG segment 118; similarly, the bottom region overlaps a portion of a respective instance of the BM0 PG segment 118. In each of the rows RW1, RW3, and RW5, the respective instance of the BM0 PG segment 118 spans the entire row and is referred to as a BM0 PG track in some embodiments. With respect to the Y-axis, each BM0 PG track 118 has a height of ½ PG.W.

[0045] In the first cell regions 102(1)-102(8), and with respect to the Y-axis: an instance of the BVD contact 124 substantially overlaps a portion of a respective instance of the BM0 PG track 118; an instance of the BVG contact 122 substantially overlaps a portion of a corresponding BM0 LI structure 120(1)-120(8).

[0046] The BM0 LI structures 120(1)-120(8) are correspondingly located in the even rows RW2, RW4, and RW6. Each of the second cell regions 104(1)-104(7) includes at least one BM0 LI structure. As such, the BM0 LI structures 120(1)-120(8) are correspondingly located in the second cell regions 104(1)-104(7). Some second cell regions include at least two BM0 LI structures. Examples of second cell regions that include at least two BM0 LI structures include the second cell regions 104(4), 104(9), and 104(11) that include the BM0 LI structures 120(4) and 120(5), 120(10) and 120(11), and 120(13) and 120(14).

[0047] At least some of the BM0 LI structures 120(1)-120(8) are portions that extend through a central region of the corresponding second unit area. Examples of BM0 LI structures having portions that extend through a central region of the corresponding second unit area include BM0 LI structures 120(1)-120(2), 120(4)-120(5), and 120(7)-120(8) corresponding to second unit areas 104(1)-104(2), 104(4), 104(4), and 104(6)-104(7), etc.

[0048] In some embodiments, each of the BM0 LI structures 120(1)-120(8) is described as an irregular polygon. In some embodiments, an irregular polygon is defined as a polygon that does not have all sides of equal length and does not have all angles equal.

[0049] In some embodiments, each of the BM0 LI structures 120(1), 120(4), 120(5), and 120(8) is described as a concave polygon. In some embodiments, a concave polygon is defined as a polygon having at least one interior angle greater than 180 degrees (180°). With respect to a diagonal line extending between a first vertex and a second vertex of the polygon, in some embodiments, a concave polygon is defined as a polygon having at least one diagonal line outside of the polygon. In some embodiments, each of the BM0 LI structures 120(1), 120(4), and 120(8) is described as a concave polygon having a P-shape. In some embodiments, each of the BM0 LI structures 120(1), 120(4), and 120(8) is described as a concave polygon having an L-shape. In some embodiments, the BM0 LI structure 120(5) is described as a concave polygon having a U-shape.

[0050] In some embodiments, each of the BM0 LI structures 120(2)-120(3) and 120(6)-120(7) is described as a convex polygon. In some embodiments, a convex polygon is defined as a polygon having all interior angles less than 180 degrees (180°). In some embodiments, a convex polygon is defined as a polygon having all diagonal lines inside of the polygon.

[0051] In some embodiments, each of the BM0 LI structures 120(2)-120(3) and 120(6)-120(7) is described as a rectangle.

[0052] Each of the BM0 LI structures 120(3) and 120(6) is shorter than each of the BM0 LI structures 120(2) and 120(7) with respect to the Y-axis. Thus, in some embodiments, each of the BM0 LI structures 120(3) and 120(6) is described as a short rectangular shape, and each of the BM0 LI structures 120(2) and 120(7) is described as a tall rectangular shape.

[0053] In some embodiments, each of the BM0 LI structures 120(3) and 120(6) has a height equal to a minimum height of a conductive segment in layer BMET0 with respect to the Y-axis. In some embodiments, the minimum height of a conductive segment in layer BMET0 is determined by, for example, design rules and dimensions of a corresponding semiconductor process technology node.

[0054] One or more portions of each of the even rows RW2, RW4, and RW6 include instances of the BM0 PG segments 119 with respect to the Y-axis. In each of the even rows RW2, RW4, and RW6, none of the respective instances of the BM0 PG segments 119 substantially spans the entire row, such that the instances of the BM0 PG segments 119 are referred to as BM0 PG stubs in some embodiments.

[0055] Some of the cell regions 104(l)-104(7) include instances of the BM0 PG stubs 119 with respect to the Y-axis, such as the cell regions 104(2), 104(4), and 104(6). In comparison, some of the second cell regions 104(l)-104(7) do not include instances of the BM0 PG stubs 119, such as the second cell regions 104(l), 104(3), 104(5), and 104(7).

[0056] wherein a first instance of the BM0 PG track 118 at a bottom region of a first cell region (e.g., the first cell region 102(2)) abuts a BM0 PG stub 119 at a top region of a second cell region (e.g., the second cell region 104(2)), the first instance of the BM0 PG track 118 and the first instance of the BM0 PG stub 119 have a sum of 2*1 / 2PG.W = PG.W.

[0057] With respect to the X-axis, the second cell region 104(2) includes instances of the BM0 PG stubs 119 to the left and right of the BM0 LI structure 120(2). Also, the BM0 LI structure 120(2) is asymmetrically located within the second cell region 104(2) with respect to the X-axis, i.e., the center of the BM0 LI structure 120(2) is offset to the left of the center of the second cell region 104(2).

[0058] To the right of the second unit region 104(4) with respect to the X axis, there is an instance of the BM0_PG stub 119. In the second unit region 104(4), the U-shaped BM0 LI structure 120(5) is located between the P-shaped BM0 LI structure 120(4) and the instance of the BM0_PG stub 119.

[0059] To the right of the second unit region 104(4) with respect to the X axis, there is an instance of the BM0_PG stub 119. In the second unit region 104(4), the U-shaped BM0 LI structure 120(5) is located between the P-shaped BM0 LI structure 120(4) and the instance of the BM0_PG stub 119.

[0060] With respect to the axis of symmetry parallel to the Y axis, the high unit region 106(2) essentially represents a version of the high unit region 106(1) rotated by 180 degrees (180°). As such, each of the first unit region 102(7) and the second unit region 104(6) essentially represents the first unit region 102(2) and the second unit region 104(2), respectively, and rotated by 180 degrees (180°).

[0061] In Figure 1A-1C , the odd rows have a height h_odd( Figure 2A-2B ); the even rows have a height h_even( Figure 2A-2B ). In Figure 1A-1C , h_odd = h_even. In some embodiments, h_odd ≠ h_even.

[0062] Figure 1B is a layout of a device 100B according to some embodiments.

[0063] Figure 1B The device 100B of Figure 1A is similar to the device 100A of . For brevity, the discussion will focus on the differences of the device 100B compared to the device 100A rather than the similarities.

[0064] In Figure 1B , the layout shows portions 108B and 110B of the device 100B. The portion 108B of the device 100B represents structures in the layer MET0. The portion 110B of the device 100B represents structures in the backside layer, i.e., structures in the layer under the active area of the transistors Figure 2A-2B .

[0065] For simplicity of illustration, some but not all instances of the first cell regions are numbered, namely 102(9)-102(12). For simplicity of illustration, some but not all of the second cell regions are numbered, namely 104(8)-104(11).

[0066] In Figure 1B each first cell region and each second cell region is in a corresponding row in rows RW7-RW10. Only the first cell regions are in odd rows, namely RW7 and RW9. The second cell regions are in even rows, namely RW8 and RW110. The second cell regions are excluded from odd rows. In some embodiments, one or more instances of even rows include one or more first cell regions in addition to one or more second cell regions, for example Figure 1B-1C Row RW8 of Figure 1B device 100B is described as having an alternating row arrangement, namely, alternating rows of corresponding first row architecture and second row architecture.

[0067] The first cell region 102(9) is stacked on the second cell region 104(9) with respect to the Y-axis and together comprise a high cell region 106(3). The first cell region 102(11) is stacked on the second cell region 104(11) with respect to the Y-axis and together comprise a high cell region 106(4).

[0068] Each of the first cell regions 102(10) and 102(12) represents an INVD4 cell region. The INVD4 cell region 102(12) is substantially identical to the INVD4 cell region 102(10). Each of the second cell regions 104(8) and 104(10) represents an AOI22D1 cell region. The AOI22D1 104(10) is substantially identical to the AOI22D1 104(8).

[0069] In Figure 1B each of the high cell regions 106(3) and 106(4) represents an SDFQD1 cell region. The SDFQD1 cell region 106(4) is substantially identical to the SDFQD1 cell region 106(3). As such, the first cell region 102(9) of SDFQD1 106(3) is substantially identical to the first cell region 102(11) of SDFQD1 106(4). Also, the second cell region 104(9) of SDFQD1 106(3) is substantially identical to the second cell region 104(11) of SDFQD1 106(4).

[0070] Port 108B of device 100B includes instances of M0_PG segments, i.e., instances of M0_PG segments 112, and instances of M0_rte segments 115 and 116, that extend parallel to the X axis in layer MET0. Each instance of M0_rte segment 115 has a height, relative to the Y axis, that is less than a height of each instance of M0_PG segment 112. Each instance of M0_PG segment 112 has a height, relative to the Y axis, that is less than a height of each instance of M0_rte segment 116. In some embodiments, each instance of M0_PG segment 112 has a height, relative to the Y axis, that is approximately the same as (but not greater than) a height of each instance of M0_rte segment 116.

[0071] In Figure 1B , layer MET0 is further organized according to a second grid, which includes second reference lines (beta tracks) that extend parallel to the X axis (not shown). The instances of M0_rte segments 115 and 116 are aligned with the beta tracks. One or more instances of M0_rte segment 115 are aligned with a first given one of the beta tracks and distributed relative to the X axis. One or more instances of M0_rte segment 116 are aligned with a second given one of the beta tracks and distributed relative to the X axis. However, no instance of M0_rte segment 115 is aligned with an instance of M0_rte segment 116 to the same beta track.

[0072] Whether a given portion of the first given beta track is filled with a given instance of M0_rte segment 115, and the length of the given instance of M0_rte segment 115, relative to the X axis, depends on a portion of the corresponding second cell region underneath the given portion. Similarly, whether a given portion of the second given beta track is filled with a given instance of M0_rte segment 116, and the length of the given instance of M0_rte segment 116, relative to the X axis, depends on a portion of the corresponding second cell region underneath the given portion.

[0073] In Figure 1B , each of odd rows RW7 and RW9 has the same layer MET0 architecture as odd rows RW1, RW3, and RW5 of Figure 1A . Each of even rows RW8 and RW10 has the same layer MET0 architecture as even rows RW2, RW4, and RW6 of Figure 1AThe even rows RW2, RW4, and RW6 of the layer MET0 architecture are different. Each of the even rows RW8 and RW10 has two MO rte segment 115 specific beta tracks and one MO rte segment 116 specific beta track. Within each of the RW8 and RW10 rows, the MO rte segment 116 specific beta track is between the two MO rte segment 115 specific beta tracks. Thus, each MO rte segment 115 specific beta track of each second unit area can have (but does not necessarily have) one or more instances of the MO rte segment 115 aligned with each of the two beta tracks of the corresponding row. Additionally, the MO rte segment 115 specific beta track of each second unit area can have (but does not necessarily have) one or more instances of the MO rte segment 116 aligned with the beta track of the corresponding row.

[0074] For simplicity of illustration, relative to the Y axis, Figure 1B Adjacent instances of the MO PG segment 112 are shown separated by two instances of the MO rte segment 115 and one instance of the MO rte segment 116. Each instance of the MO rte segment 116 is between the two instances of the MO rte segment 115. In some embodiments, each of the rows RW7 and RW9 is described as having a “four MO rte segments per row” architecture. In some embodiments, each of the rows RW8 and RW10 is described as having a “three MO rte segments per row” architecture.

[0075] In Figure 1B In the portion 110B, the structures in the backside layer are represented. The portion 110B includes: instances of the BVD contacts 124; instances of the BM0_PG tracks 118; instances of the BM0_PG stubs 119; and the BM0 LI structures 120(9)-120(14).

[0076] In the first unit areas 102(9)-102(12), and relative to the Y axis, the instances of the BVD contacts 124 substantially overlap portions of the respective instances of the BM0_PG tracks 118.

[0077] The BM0 LI structures 120(9)-120(14) are located in the even rows RW8 and RW10, respectively. Each of the second unit areas 104(8)-104(11) includes at least one BM0 LI structure. As such, the BM0 LI structures 120(9)-120(14) are located in the second unit areas 104(8)-104(11), respectively. An example of a second unit area having at least two BM0 LI structures is the second unit area 104(9) including the BM0 LI structures 120(10) and 120(11), etc. Another example of a second unit area having at least two BM0 LI structures is the second unit area 104(11) including the BM0 LI structures 120(13) and 120(14), etc.

[0078] In some embodiments, each of the BM0 LI structures 120(9)-120(14) is described as an irregular polygon. Figure 1B

[0079] In some embodiments, each of the BM0 LI structures 120(9) and 120(12) is described as a concave polygon. In some embodiments, each of the BM0 LI structures 120(9) and 120(12) is described as a concave polygon having a Z shape.

[0080] In some embodiments, each of the BM0 LI structures 120(10)-120(11) and 120(13)-120(14) is described as a convex polygon. In some embodiments, each of the BM0 LI structures 120(10)-120(11) and 120(13)-120(14) is described as a convex polygon having a rectangular shape. Thus, in some embodiments, each of the BM0 LI structures 120(10)-120(11) and 120(13)-120(14) is described as a convex polygon having a short rectangular shape.

[0081] With respect to the Y axis, one or more portions of each of the even rows RW8 and RW10 include instances of the BM0 PG stub 119. With respect to the Y axis, some of the unit areas 104(8)-104(11) include instances of the BM0 PG stub 119, such as the unit areas 104(8)-104(11). Conversely, in some embodiments, some of the second unit areas (not shown in FIG. 1) do not include instances of the BM0 PG stub 119. Figure 2B

[0082] ​​Each of the second unit areas 104(8)-104(11) contains, with respect to the X axis, an instance of the BM0_PG stub 119 to the left and right of the corresponding BM0 LI structure 120(9)-120(14). The BM0 LI structures 120(9) and 120(12) are asymmetrically positioned with respect to the X axis within the corresponding second unit areas 104(8) and 104(10), i.e., the centers of the BM0 LI structures 120(8) and 120(12) are shifted right with respect to the centers of the second unit areas 104(8) and 104(10). The second unit area 104(10) is substantially identical to the second unit area 104(8).

[0083] The BM0 LI structures 120(10) and 120(13) are substantially completely overlapped with respect to the X axis by the BM0 LI structures 120(11) and 120(14), respectively.

[0084] The BM0 LI structures 120(10) and 120(13) are asymmetrically positioned with respect to the X axis within the corresponding second unit areas 104(9) and 104(11), i.e., the centers of the BM0 LI structures 120(10) and 120(13) are shifted right with respect to the centers of the second unit areas 104(9) and 104(11).

[0085] The BM0 LI structures 120(11) and 120(14) are substantially symmetrically positioned with respect to the X axis within the corresponding second unit areas 104(9) and 104(11), i.e., the centers of the BM0 LI structures 120(11) and 120(14) are aligned with the centers of the second unit areas 104(9) and 104(11).

[0086] The high unit area 106(4) is substantially identical to the high unit area 106(3). As such, each of the first unit areas 102(9) and the second unit areas 104(11) are substantially identical, and each of the second unit areas 104(9) and 104(11) are substantially identical.

[0087] Figure 1C is a layout of an apparatus 100C in accordance with some embodiments.

[0088] Figure 1C The apparatus 100C is similar to the apparatus 100B of Figure 1B For brevity, the discussion will focus on the differences of the apparatus 100C compared to the apparatus 100B rather than the similarities.

[0089] Figure 1C The apparatus 100C differs from the apparatus 100B of Figure 1B Each of the apparatuses 100B and 100C includes the portion 110B. As such, in Figure 1CThe layout diagram shows parts of 108C and 110B.

[0090] Part 108C of device 100C represents the structure in layer MET0, that is, the layer MET0 architecture. In part 108C, even-numbered rows RW8 and RW10 are... Figure 1B The same as in part 108B. Therefore, Figure 1C The even-numbered rows RW8 and RW10 in part 108C have the same Figure 1B The same layer MET0 architecture is used in rows RW8 and RW10 of part 108B.

[0091] exist Figure 1C In the middle, some odd-numbered rows of 108C have the same characteristics as... Figure 1B The odd-numbered rows in part 108 have a different layer MET0 architecture. In part 108C, the odd-numbered rows RW11 and RW12 have the same layer MET0 architecture as the even-numbered rows (i.e., even-numbered rows RW8 and RW10) in part 108C.

[0092] The paradigmatic orientation of each of the first unit regions 102(1)-102(12) and each of the second unit regions 104(1)-104(11) has been... Figure 1A-1C The corresponding orientations are shown relative to the X-axis and Y-axis. Generally, in some embodiments, one or more of the various first unit regions and / or one or more of the various second unit regions can be inserted into a layout diagram with different orientations relative to the X-axis and / or relative to the Y-axis. For example, having... Figure 3C Front side 342F and Figure 3D The back of the 342R has the BUFFD4 unit area. Figure 1A Examples of the second unit region 104(1) or 104(7), although rotated 180 degrees (180°) around the X-axis.

[0093] Figure 2A-2B These are corresponding cross-sectional views 225A-225B of an apparatus according to some embodiments. Corresponding to... Figure 2A-2B The device with cross-sections 225A-225B is a device containing Figure 1A Example of a device with unit area 104(4).

[0094] Figure 2A The cross section 225A corresponds to Figure 1A The cross section IIA-IIA'. Figure 2B The cross section 225B corresponds to Figure 1A The cross section IIB-IIB'. In Figure 2A-2B In this diagram, we assume an orthogonal Cartesian coordinate system, where the first direction is parallel to the X-axis, the second direction is parallel to the Y-axis, and the third direction is parallel to the Z-axis. For simplicity, corresponding component symbols are not used for labeling. Figure 2A-2B All components in each of the cross-sections 225A-225B. The respective extensions of the cross-sections 225A-225B with respect to the Y-axis are truncated by instances of a break line-pair 237.

[0095] The cross-sections 225A-225B follow a similar numbering scheme as the layout diagram of Figure 1A Although certain components correspond, there are certain components that differ. To help identify those components that correspond but differ, the numbering convention uses a 2-series numbering for the cross-sections 225-225B, while a 1-series numbering is used for Figure 1A For example, Figure 2A-2B The instance of the M0_rte segment 214 in each of the cross-sections 225A-225B corresponds to the instance of the M0_rte segment 114 in Figure 1A For brevity, the discussion will focus more on the differences between Figure 2A-2B and Figure 1A than the similarities.

[0096] In Figure 2A-2B , a reference line 226 extends parallel to the Y-axis. The reference line 226 substantially bisects an active region (AR) layer 227 with respect to the Z-axis. The area above the reference line 226 is referred to as a front side 21 IF. The area below the reference line 226 is referred to as a backside (or rear side) 21 IR. The layer MET0 208 is above the reference line 226 and thus on the front side 21 IF of each of the cross-sections 225A-225B. The layer BMET0 209 is below the reference line 226 and thus on the backside 21 IR of each of the cross-sections 225A-225B. Field effect transistor (FET) components (discussed below) are located in an FET component layer 228. With respect to the Z-axis, the FET component layer 228 is between the layer MET0 208 and the layer BMET0 209.

[0097] In Figure 2A , the AR layer 227 includes source / drain (S / D) regions 229D1(1), 229D1(2), 229D2(1), and 229D2(2) that have been formed in the corresponding active regions Figure 2B). In some embodiments, D1 is an alphanumeric string designed to represent S / D regions 229D1(1) and 229D1(2) formed in respective active regions that have been doped with a first type of dopant (e.g., N-type dopant for negative channel metal-oxide-semiconductor (NMOS) transistor technology). In some embodiments, D2 is an alphanumeric string designed to represent S / D regions 229D2(1) and 229D2(2) formed in respective active regions that have been doped with a second type of dopant (e.g., P-type dopant for positive channel metal-oxide-semiconductor (PMOS) transistor technology). In some embodiments, the first dopant type is N-type dopant and the second dopant type is P-type dopant. In some embodiments, S / D regions 229D1(1) and 229D1(2) are respectively epitaxially grown semiconductors, such as silicon, with N-type dopant. In some embodiments, S / D regions 229D2(1) and 229D2(2) are respectively epitaxially grown semiconductors, such as silicon, with P-type dopant.

[0098] In Figure 2A layer MET0 208 includes an instance of M0_PG segment 212 and an instance of M0_rte segment 214. FET component layer 228 includes metal-to-S / D-region (MD) contacts 230(1) and 230(2) formed partially around corresponding S / D regions 229D2(1) and 229D1(2), respectively, and an instance of via-to-MD (VD) contact 232. MD contact 230(2) is coupled to the instance of M0_PG segment 212 through the instance of VD contact 232.

[0099] At least some embodiments facilitate removal of instances of non-functional and thus unnecessary pseudo MD contacts, which has the beneficial effect of reducing parasitic capacitance. Instances where pseudo MD contacts have been removed are indicated by instances of phantom (dashed) boxes 231. In some embodiments, instances of phantom boxes 231 are referred to as ghost-intersections 231, as the MD contacts would otherwise intersect the active regions at the ghost-intersection locations. In some embodiments, a cell region exhibits an increased ghost-intersection count cnt_GH in the range 2 < cnt_GH < 5 compared to a corresponding cell region according to another approach. In other words, in some embodiments, a cell region exhibits a decreased MD-intersection count cnt_MD in the range 2 < cnt_MD < 5 compared to a corresponding cell region according to another approach.

[0100] In Figure 2AIn the middle, layer BMET0 209 includes BM0_PG tracks 218(1) and 218(2) and BM0_LI structure 220(5). BM0_LI structure 220(5) corresponds to BM0_LI structure 120(5). Each of BM0_PG tracks 218(1) and 218(2) is wider than each instance of M0_PG segment 212. At least a portion of each of BM0_LI structures 120(1)-120(2), 120(4)-120(5), 120(7)-120(9) and 120(12) is wider / higher relative to the Y-axis than each BM0_PG track 218(1) and 218(2).

[0101] The FET component layer 228 also includes instances of BVD contacts 224. The opposite ends / sides of the BM0_LI structure 220(5) are correspondingly coupled to S / D regions 229D1(1) and 229D2(2) through instances of BVD contacts 224. The BM0_PG rail 218(2) is coupled to S / D region 229D1(2) through instances of BVD contacts 224.

[0102] exist Figure 2A In the middle, instances of S / D areas 229D1(1) and 229D2(2), BM0_LI structure 220(5), BVD contact 224, instances of M0_rte segment 214, and a portion of instances of M0_PG segment 212 are in row RW4, and more specifically in the second cell area 204(4), where the latter is the SDFQD1 cell area. Figure 2A In the S / D area 229D1(2), BM0_PG track 218(2), instances of BVD contact 224, MD contact 230(2), instances of VD contact 232, instances of M0_rte segment 214, and a portion of instances of M0_PG segment 212 are in line RW5, and more specifically in the first unit area 202(7). Figure 2A In the middle, the group including instances of S / D area 229D2(1), BM0_PG track 218(1), MD contact 230(1), M0_rte segment 214 and a portion of instances of M0_PG segment 212 is in row RW3; more specifically, relative to the X-axis, in the corresponding Figure 1A Between the first unit area 102(4) and 102(5) in the middle.

[0103] exist Figure 2BIn the middle, layer BMET0 209 includes BM0_PG tracks 218(1) and 218(2) and BM0 LI structure 220(5). AR layer 227 includes active region (AR) structures 235D1(1), 235D1(2), 235D2(1), and 235D2(2). Each of AR structures 235D1(1) and 235D1(2) contains an instance of nanosheet 236D1. Each of AR structures 235D2(1) and 235D2(2) contains an instance of nanosheet 236D2. In some embodiments, 236D1 is an alphanumeric literal string designed to indicate that nanosheet 236D1 is formed from a semiconductor (e.g., silicon) that has been doped with a first type of dopant (e.g., an N-type dopant), and accordingly, AR structures 235D1(1) and 235D1(2) are N-type AR structures. In some embodiments, 236D2 is an alphanumeric literal string designed to indicate that nanosheet 236D2 is formed from a semiconductor (e.g., silicon) that has been doped with a second type of dopant (e.g., a P-type dopant), and accordingly, AR structures 235D2(1) and 235D2(2) are P-type AR structures. In some embodiments, the first dopant type is an N-type dopant and the second dopant type is a P-type dopant.

[0104] In Figure 2B In the middle, FET component layer 228 also includes gates 233(1)-233(3) formed partially around corresponding AR structures 235D2(1), 235D1(1). AR structures 235D1(1) and 235D2(2) are coupled together through gate 233(2). Gate 233(3) is coupled to an instance of M0 rte segment 214 through an instance of VG contact 234.

[0105] FET component layer 228 also contains an instance of BVG contact 222. BM0 LI structure 220(5) is coupled to AR structure 235D1(1) through the instance of BVG contact 222.

[0106] In Figure 2B In the middle, AR structures 235D1(1) and 235D2(2), gate 233(2), BM0 LI structure 220(5), the instance of BVG contact 222, the instance of M0 rte segment 214, and the portion of M0 PG segment 212 are in row RW4, and more specifically, in second cell region 204(4), which is the SDFQD1 cell region.

[0107] In Figure 2BIn particular, the group comprising AR structure 235D1(2), gate 233(3), BM0_PG rail 218(2), an instance of BVG contact 222, an instance of M0_rte segment 214, and a portion of an instance of M0_PG segment 212 is in row RW5, and more particularly, in first cell region 202(7) with respect to the X-axis.

[0108] In Figure 2B In particular, the group comprising AR structure 235D2(1), gate 233(1), BM0_PG rail 218(1), an instance of M0_rte segment 214, and a portion of an instance of M0_PG segment 212 is in row RW3; and, more particularly, with respect to the X-axis, in a region corresponding to Figure 1A between first cell regions 102(4) and 102(5) in

[0109] The following will be discussed in the context of Figure 3E-3F The following will be discussed in the context of Figure 2C .

[0110] Figures 3A-3B are respective layout diagrams 340F and 340R of a BUFFD4 cell region according to some embodiments.

[0111] Layout diagrams 340F and 340R represent the front side and back side, respectively, of a BUFFD4 cell region. The BUFFD4 cell region having front side 340F and back side 340R is an example of a first cell region 102(3), 102(5), or 102(6), etc., of Figure 1A Figures 3A-3B Each of the rows RW33 in Figure 3A Also included are portions of the upper region and lower region corresponding to row RW33, namely, even rows RW32 and RW34.

[0112] Figure 3A includes: an active region; a gate; an MD contact; a VD contact; a VDR contact; an M0_rte segment; an M0_dummy segment; and an M0_PG segment. Figure 3B includes: a BM0_PG stub; a BVD contact; an active region; and a gate. The VDR contact facilitates coupling, e.g., of first and second instances of an MD contact.

[0113] The adjacent gate lines are spaced a uniform distance apart with respect to the X-axis. In some embodiments, the uniform distance is a multiple of a given distance measure unit. In some embodiments, the value of the multiple is one, such that the uniform distance is one instance of the distance-measure given unit. The BUFFD4 cell region having front side 340F and back side 340R has a width of 5 CPPs with respect to the X-axis.

[0114] ​In some embodiments, the unit of distance measurement is 1.0 CPP. In some embodiments, CPP is an abbreviation for contacted poly pitch. The value of CPP is determined, for example, by the design rules and dimensions of the corresponding semiconductor process technology node. Here, the term "poly" in CPP does not necessarily imply a corresponding basis for... Figures 3A-3B The gate lines in semiconductor devices are formed from polysilicon, not because of historical convenience – the gate structures in ICs manufactured according to one or more previous semiconductor process technology nodes were typically formed from polysilicon, which led to the term "polysilicon" being commonly used to refer to "gate lines".

[0115] In some embodiments, the gate lines aligned with the left and right boundaries of the BUFFD4 cell region are replaced by corresponding isolation dummy gates (IDGs) (discussed below). More generally, in other layouts disclosed herein, for example... Figure 3C-3F , Figures 4A-4F , Figures 5B-5C In some embodiments, the gate lines aligned with the left and right boundaries of the corresponding cell regions are replaced by IDGs accordingly.

[0116] In some embodiments, an IDG is a dielectric structure comprising one or more dielectric materials and used as an electrical isolation structure. Therefore, an IDG is not a conductive structure and does not function as an active gate, for example, in a transistor. An IDG comprises one or more dielectric materials and is used as an electrical isolation structure. In some embodiments, an IDG is based on a gate as a precursor. In some embodiments, a method of forming an IDG includes: forming a gate; sacrificing / removing (e.g., etching) the gate to form a trench that at least partially surrounds a corresponding portion of an active region; (optionally) removing part or all of the corresponding active region previously surrounded by the gate portion to deepen the trench, thereby partially or completely separating the corresponding active region so that it does not extend beyond / beyond the corresponding left or right side of the cell region relative to the X-axis; and then filling the trench with one or more dielectric materials such that the physical dimensions of the resulting electrical isolation structure (i.e., the IDG) are similar to the dimensions of the sacrificed gate. In some embodiments, an IDG is a dielectric component comprising one or more dielectric materials (e.g., oxides, nitrides, oxynitrides, or other suitable materials) and used as an isolation component. In some embodiments, IDG is a continuous polysilicon on an oxide diffusion (OD) edge structure and is referred to as a CPODE structure.

[0117] Figure 3C-3D The layout diagrams 342F and 342R of the BUFFD4 cell area are based on some embodiments.

[0118] Layouts 342F and 342R represent the front side and back side, respectively, of the BUFFD4 cell region. The BUFFD4 cell region having front side 342F and back side 342R is an example of the second cell region 104(1) or 104(7) of Figure 1A , albeit with a different orientation, i.e., rotated 180 degrees (180°) about the X-axis, etc. Figure 3C-3D Each of the front side 342F and back side 342R includes: even rows RW36; and portions of odd rows RW35 and RW37 that respectively abut the upper and lower boundaries of the rows RW36. The respective extensions of the front side 342F and back side 342R with respect to the Y-axis are truncated by instances of the broken line pair 237. With respect to the X-axis, the BUFFD4 cell region having front side 342F and back side 342R has a width of 6 CPP.

[0119] In terms of the types of elements / structures included, Figure 3C are similar to Figure 3A , but Figure 3C also include: V0 contacts in the VA0 layer; M1_rte segments in the MET1 layer. In terms of the types of components / structures included, Figure 3D are similar to Figure 3B , however Figure 3D also include instances of the BM0_LI structure 320(1) and the BM0_PG stub 319. With respect to the Y-axis, the bottom region of the rows RW35 and the top region of the rows RW37 include the BM0_PG tracks 318.

[0120] The upper region of the back side 342R includes the BM0_PG stubs that extend from about the middle of the back side 342R to the right side boundary of the back side 342R. The BM0_PG stubs in the back side 342R are coupled to the BM0_PG tracks in the rows RW35. The ability to couple the BM0_PG stubs in the back side 342R of the even rows RW36 to the BM0_PG tracks in the odd rows RW35 is Figure 3C-3D an advantage of the arrangement of , i.e., is an advantage of the architecture of the alternating row arrangement disclosed herein.

[0121] Figure 3C In Figure 3C , the M0_rte segments are aligned with two of the four alpha tracks. In Figure 3C , two of the alpha tracks do not have M0_rte segments aligned therewith.

[0122] Generally, in some embodiments, alpha track usage cnt_a in the second unit area is reduced compared to the unit area according to the other approach of the respective counterpart of the BUFFD4 unit area. In some embodiments, alpha track usage in the second unit area is reduced in the range of 1 < cnt_a < 2 compared to the respective counterpart unit area.

[0123] As a counterpart of the BUFFD4 unit area having a front side 342F and a back side 342R, a BUFFD4 unit area according to another approach (A) (not shown) does not include a BM0 LI structure, and (B) each of its four alpha tracks has one or more M0 rte segments aligned therewith. Thus, the counterpart BUFFD4 unit area according to the other approach encounters increased M0 routing congestion and increased parasitic capacitance. In contrast, by using the BM0 LI structure 320(1) to reduce M0 routable linear congestion, the BUFFD4 unit area having a front side 342F and a back side 342R reduces alpha track usage by 50% compared to the counterpart BUFFD4 unit area according to the other approach, which reduces the parasitic capacitance situation compared to the counterpart BUFFD4 unit area according to the other approach.

[0124] Figure 3E-3F are a counterpart layout 344F and 344R of a BUFFD4 unit area according to some embodiments.

[0125] In Figure 3E-3F , the cross-hatching IIC-IIC' extends parallel to the Y axis. The cross-hatching IIC-IIC' corresponds to a cross-sectional view 225C of Figure 2C .

[0126] The layout 344F and 344R represent the front side and the back side of a BUFFD4 unit area, respectively. The BUFFD4 unit area having a front side 344F and a back side 344R is an example of a second unit area of Figure 1A . Figure 3E-3F Each of the

[0127] In terms of the types of components / structures contained, Figure 3E are similar to Figure 3C . In terms of the types of components / structures contained, Figure 3F are similar to Figure 3D , however Figure 3FAlso included are BVD rail (BVDR) contacts 323. Relative to the Y axis, the bottom region of row RW39 and the top region of row RW41 include BM0_PG rails 318. The BVDR contacts 323 facilitate coupling between, for example, a first instance and a second instance of an S / D region Figure 2B

[0128] In Figure 3E , the M0_rte segments are organized according to four Alvarez tracks (not shown). However, in Figure 3E , the M0_rte segments are aligned with three of the four Alvarez tracks. In Figure 3E , one of the Alvarez tracks does not have an M0_rte segment aligned therewith.

[0129] As a counterpart to the BUFFD4 cell region having a front side 344F and a back side 344R, a BUFFD4 cell region (not shown) according to another approach (A) does not include BVD rail (BVDR) contacts, and (B) each of its four Alvarez tracks has one or more M0_rte segments aligned therewith. Accordingly, the counterpart BUFFD4 cell region according to the other approach encounters increased M0 routability congestion and increased parasitic capacitance. By using the BVD rail (BVDR) contacts 323 to reduce M0 routable linear congestion, the BUFFD4 cell region having a front side 344F and a back side 344R uses 25% fewer Alvarez tracks than the counterpart BUFFD4 cell region according to the other approach, which reduces the parasitic capacitance situation compared to the counterpart BUFFD4 cell region according to the other approach.

[0130] Before discussing Figures 4A-4C , the discussion will return to Figure 2C , corresponding to Figure 3E-3F .

[0131] Figure 2C is a cross-sectional view 225C of an apparatus according to some embodiments. The apparatus of the cross-sectional view 225C corresponds to Figure 2C the front side 344F and the back side 344R of the counterpart Figure 3E-3F apparatus.

[0132] Figure 2C The cross-sectional view 225C of Figure 3E-3F corresponds to the cross-section IIC-IIC' of Figure 2C . In , an orthogonal Cartesian coordinate system is assumed, with a first direction parallel to the X axis, a second direction parallel to the Y axis and a third direction parallel to the Z axis. The respective extension of the cross-sectional view 225C relative to the Y axis is truncated by instances of the broken line pair 237.

[0133] Figure 2Cincludes: BM0_PG tracks 218(3) and 218(4); BM0 LI structure 220(2); BDVR contact 223; SD regions 229D1(3) and 229D2(3); an instance of M0 PG segment 212; and an instance of M0 rte segment 214.

[0134] Figures 4A-4C Layout diagrams 440A M, 428B, and 440C BM are respective layout diagrams of AOI 22D1 cell region according to some embodiments.

[0135] Layout diagram 440A M represents layer MET0, layer VIAO, and layer MET1 of the corresponding AOI 22D1 cell region. Layout diagram 428B represents FET component layers of the corresponding AOI 22D1 cell region. Layout diagram 440C BM represents layer BMET0 of the corresponding AOI 22D1 cell region.

[0136] The AOI 22D1 cell region with layout diagrams 440A M, 428B, and 44C BM is an example of a second cell region 104(3) or 104(5) of Figure 1A Figures 4A-4C Each of the layout diagrams 440A M, 428B, and 44C BM includes even rows RW44. Figure 4A Layout diagram 440A M also includes portions of odd rows RW43 and RW45 that correspond to upper and lower boundaries of adjacent rows RW44. The corresponding extension of layout diagram 440A M with respect to the Y-axis is truncated by instances of break line pair 237. The AOI 22D1 cell region with layout diagrams 440A M, 428B, and 44C BM has a width of 5 CPP.

[0137] Figure 4A includes: VD contact; M0 rte segment; M0 dummy segment; M0 PG segment; gate; V0 contact; M1 rte segment; and MD contact (although only portions under the M0 PG segment are shown (for simplicity of illustration)). Figure 4B includes: active region; gate; MD contact; and dummy intersection 431. Figure 4C includes: BVD contact; gate; BM0 PG stub 419; and BM0 LI structure 420(1).

[0138] BM0 PG stub 419 is coupled to a BM0 PG track (not shown) in row RW45. The ability to couple BM0 PG stubs 419 of even rows RW44 to BM0 PG tracks (not shown) in odd rows RW45 is Figures 4A-4C an advantage of the arrangement of

[0139] ​According to another approach, the corresponding AOI22D1 cell region (not shown) has two virtual intersections, otherwise the MD contacts would be located over the lower active region with respect to the Y axis. By comparison, the AOI22D1 cell region with layout diagrams 440A_M, 428B and 440C_BM has an additional three virtual intersections 431, otherwise the MD contacts would be located over the upper active region with respect to the Y axis, i.e., an improvement of about 37.5% in the number of virtual intersections.

[0140] In Figure 4B , virtual intersections 431 are a result of at least some embodiments that help remove MD contacts that are non-functional and thus not necessary. Accordingly, virtual intersections 431 represent the benefit of reducing parasitic capacitance by correspondingly removing MD contacts that do not function and are thus not necessary.

[0141] In Figure 4A , M0_rte segments are organized according to four Al tracks (not shown). However, in Figure 4A , M0_rte segments are aligned with three of the four Al tracks. In Figure 4A , one of the Al tracks does not have an M0_rte segment aligned with it. According to another approach (A) the corresponding AOI22D1 cell region (not shown) does not include BM0_LI structures, and (B) each of its four Al tracks has one or more M0_rte segments aligned with it. Accordingly, the corresponding AOI22D1 cell region according to another approach suffers from increased M0 routing congestion and increased parasitic capacitance. By comparison, the AOI22D1 cell region with layout diagrams 440A_M, 428B and 440C_BM reduces Al track usage by 25% using BM0_LI structures 420(1) compared to the corresponding AOI22D1 cell region according to another approach, which reduces the situation of parasitic capacitance compared to the corresponding AOI22D1 cell region according to another approach.

[0142] Figure 4D-4F are corresponding layout diagrams 440D_M, 428E and 440F_BM of a BUFFD4 cell region according to some embodiments.

[0143] Layout diagram 440D_M represents layer MET0, layer VIA0 and layer MET1 of the corresponding BUFFD4 cell region. Layout diagram 428E represents FET component layers of the corresponding BUFFD4 cell region. Layout diagram 440F_BM represents layer BMET0 of the corresponding BUFFD4 cell region.

[0144] The BUFFD4 cell region with layout diagrams 440D_M, 428E and 440F_BM is Figure 1AExamples of the second unit area 104(1) or 104(7). Figure 4D-4F Each of them contains an even number of rows RW48. Figure 4D Additionally, it includes portions of odd-numbered rows RW47 and RW479 corresponding to the upper and lower boundaries of adjacent row RW48. The corresponding extension of layout diagram 440D_M relative to the Y-axis is truncated by the break line of instance 237. The BUFFD4 cell region with layout diagrams 440D_M, 428E, and 44F_BM has a width of 6 CPP.

[0145] Figure 4D This includes: VD contact; M0_rte segment; M0_virtual segment; M0_PG segment; gate; V0 contact; M1_rte segment; and MD contact (although only the portion under the M0_PG segment is shown (for simplicity)). Figure 4E Includes: active region; gate; MD contact; and virtual intersection 431. Figure 4F Includes: BVD contact; gate; BM0_PG stub 419; and BM0_LI structure 420(2).

[0146] BM0_PG stub 419 is coupled to the BM0_PG track (not shown) in row RW49. The ability to couple BM0_PG stub 419 of even-numbered row RW48 to the BM0_PG track (not shown) of odd-numbered row RW49 is... Figure 4D-4F The advantages of this arrangement are, in other words, the advantages of the alternating row arrangement architecture revealed in this paper.

[0147] exist Figure 4D In the M0_rte segment, the sequence is organized according to four alpha tracks (not shown). However, in Figure 4D In the M0_rte segment, the alignment is with two of the four alpha tracks. That is, in Figure 4D In the middle, the two alpha tracks do not have an M0_rte segment aligned with them.

[0148] According to another approach, the corresponding BUFFD4 cell region (not shown) does not include the BMO_LI structure, such that each of the four alpha tracks of the corresponding BUFFD4 cell region has one or more M0_rte segments aligned with it. Therefore, the corresponding BUFFD4 cell region according to the other approach suffers from increased M0 wiring congestion and an increase in the generation of parasitic capacitance. In contrast, by using the BMO_LI structure 420(2) to reduce M0 wiring congestion, the BUFFD4 cell region with layout diagrams 440D_M, 428E, and 440F_BM also reduces the number of parasitic capacitances generated compared to the corresponding BUFFD4 cell region according to the other approach.

[0149] According to another approach, the corresponding BUFFD4 cell region (not shown) has zero virtual intersections, otherwise the MD contacts would be located above the upper or lower active region with respect to the Y-axis. Conversely, the BUFFD4 cell regions with layout diagrams 440D_M, 428E and 440F_BM have an additional two virtual intersections 431, otherwise the MD contacts would be located above the upper active region with respect to the Y-axis, i.e., an improvement of approximately 16.7% in the number of virtual intersections.

[0150] In Figure 4E , virtual intersections 431 are a result of at least some embodiments that help remove MD contacts that are non-functional and thus not necessary. Accordingly, virtual intersections 431 accordingly represent the benefit of reducing parasitic capacitance by accordingly removing MD contacts that do not function and thus are not necessary.

[0151] In Figure 4D , M0_rte segments are organized according to four alpha tracks (not shown). However, in Figure 4D , M0_rte segments are aligned with two of the four alpha tracks. In Figure 4D , two of the alpha tracks do not have M0_rte segments aligned therewith. According to another approach (A) the corresponding BUFFD4 cell region (not shown) does not include BM0_LI structures and (B) each of the four alpha tracks thereof has one or more M0_rte segments aligned therewith. Accordingly, the corresponding BUFFD4 cell region according to another approach suffers from increased M0 routing congestion and parasitic capacitance increase. In contrast, by using BM0_LI structures 420(2) to reduce M0 routable linear congestion, the BUFFD4 cell regions with layout diagrams 440D_M, 428E and 440F_BM have a 50% reduction in alpha track usage compared to the corresponding BUFFD4 cell region according to another approach, which reduces the parasitic capacitance situation compared to the corresponding BUFFD4 cell region according to another approach.

[0152] Figure 5A is a schematic circuit diagram of SDFQ 546 according to some embodiments.

[0153] Examples of SDFQ cell regions include Figure 1A SDFQ D1 cell regions 106(1) and 106(2) of Figure 1B-1C SDFQ D1 cell regions 106(3) and 106(4) of and the like, SDFQ 546 is a representative schematic circuit diagram of an example of a SDFQ cell region.

[0154] SDFQ 546 is a pass-transistor-based design (described below). SDFQ 546 is an edge-triggered arrangement, triggered on the rising edge (positive edge) of a clock signal. Variants of SDFQ 546 are triggered on the falling edge (negative edge) of a clock signal. Other variants of SDFQ 546 are double-edge triggered, i.e., triggered by both the rising edge (positive edge) and the falling edge (negative edge) of a clock signal.

[0155] SDFQ 546 includes data selectors, D flip-flops, scan buffers, and clock buffers. SDFQ 546 includes field effect transistors (FETs), and more specifically, positive channel metal oxide semiconductor (PMOS) FETs (PFETs) and negative channel metal oxide semiconductor

[0156] (NMOS) FETs (NFETs). Some of the FETs of SDFQ 546 are arranged to work together as a sleep inverter (described below). Some of the FETs of SDFQ 546 are configured to work together as a non-sleep (NS) inverter (discussed below).

[0157] In Figure 5A , a clock buffer includes first and second NS inverters coupled in series. An input node of the first NS inverter is set to receive a clock signal CP. An output node of the first NS inverter has a clock signal CPB representative of an inversion of the clock signal CP. The output node of the first NS inverter is an input node of the second NS inverter. An input node of the second NS inverter is set to receive the clock signal CPB. An output node of the second NS inverter has a clock signal CPBB representative of an inversion of the clock signal CPB.

[0158] Various nodes in SDFQ 546 are configured to receive the clock signal CP; these nodes together represent a clock network for CP (CLK-net-CP). Various nodes in SDFQ 546 are configured to receive the clock signal CPB; these nodes together represent a clock network for CPB (CLK-net-CPB). Various nodes in SDFQ 546 are configured to receive the clock signal CPBB; these nodes together represent a clock network for CPBB (CLK-net-CPBB).

[0159] In Figure 5A , a scan buffer receives a scan / test enable (SE) signal that selects between normal (i.e., non-scan / test) operation with respect to a data signal or scan / test operation with respect to a scan input (SI) signal. The scan buffer includes a non-sleep (NS) inverter. The NS inverter is the counterpart of a sleep inverter (described below).

[0160] In Figure 5A , the data selector includes a set of pass transistors GRPDAT (pass set GRPDAT), a set of scan transistors GRPSC (scan set GRPSC), and a set of delay transistors GRPDEL (delay set GRPDEL). The pass set GRPDAT is used to select a pass input signal D. The scan set GRPSC is used to select a scan input signal SI. The delay set GRPDEL is used to delay the propagation of the selected input (i.e., SI or D) through the data selector. An output node of the data selector has a signal mq_x.

[0161] In Figure 5A , the D flip-flop includes a primary latch, an internal buffer, a secondary latch, and an output buffer. The primary latch includes an NS inverter and a sleep inverter. An input node of the primary latch is configured to receive a signal mq_x from the data selector, and an output node has a signal mq. The signal mq represents an inversion of the signal mq_x. The sleep inverter can be placed in a sleep mode of operation due to including a PFET configured to receive a clock signal CPB and a NFET configured to receive a clock signal CPBB. In contrast, the NS inverter lacks a PFET configured to receive a clock signal CPB and a NFET configured to receive a clock signal CPBB, such that the NS inverter lacks a sleep mode of operation; thus, the NS inverter is described as a non-sleep (NS) inverter. The sleep inverter feeds back an inverted version of the signal mq to an input of the NS inverter, and thus to an input of the primary latch.

[0162] In Figure 5A , the internal buffer includes a pass gate. The SDFQ 546 can be described as a pass-gate-based design due to including the pass gate in the SDFQ 546. An input node of the internal buffer (i.e., the pass gate) is configured to receive the signal mq from the primary latch. An output node of the internal buffer (i.e., the pass gate) has a signal qf.

[0163] In the D flip-flop, the secondary latch includes an NS inverter and a sleep inverter. An input node of the secondary latch is configured to receive the signal qf from the internal buffer, and an output node has a signal qf_x. The signal qf_x represents an inversion of the signal qf.

[0164] In the D flip-flop, the output buffer includes an NS inverter. An input node of the output buffer is configured to receive the signal qf_x, and an output node has a signal Q. The output node of the output buffer represents an output node of the D flip-flop, and thus also represents an output node of the SDFQ 546. The signal Q represents an inversion of the signal qf_x.

[0165] In Figure 5AIn this design, the D flip-flop is based on a transmission gate design because its internal buffer contains a transmission gate. In some embodiments, the D flip-flop is based on a stacked gate design (not shown). More specifically, although Figure 5A The internal buffer includes a transmission gate, but the stacked-gate version of the D flip-flop includes a stacked-gate version of the internal buffer. In some embodiments, the stacked-gate version of the internal buffer includes a sleep inverter (not shown) instead of a transmission gate, where the sleep inverter is an example of a stacked-gate device. Similar to the transmission gate, the output of the sleep inverter is coupled to the input of the secondary latch. Unlike the transmission gate, the input of the sleep inverter in the stacked-gate device is not connected to the output node of the primary latch, but rather to the output node of the data selector.

[0166] Figures 5B-5C The corresponding layout diagrams 548F and 548R of the SDFQD1 cell area are based on some embodiments.

[0167] Layout diagrams 548F and 548R respectively represent the front and back sides of the SDFQD1 cell region. The SDFQD1 cell region having a front side 548F and a back side 548R is... Figure 1A Examples of SDFQD1 cell regions 106(1) or 106(2). Figures 5B-5C Each of these includes: a portion of even-numbered row RW50, odd-numbered row RW51, even-numbered row RW52, and a portion of odd-numbered row RW53. The SDFQD1 cell region with front side 548F and back side 548R has a width of 11 CPP relative to the X-axis. The corresponding extensions of each layout diagram 548F and 548R relative to the Y-axis are truncated by break lines in instance 237.

[0168] Figure 5B This includes: VD contact; M0_rte segment; M0_virtual segment; M0_PG segment; gate; V0 contact; and M1_rte segment. Figure 5C Includes: BVD contact; BVG contact; gate; BM0_PG rail 518; BM0_PG stub 519(1)-519(4); and BM0_LI structure 520(1).

[0169] BM0_PG stubs 519(1) and 519(2) are coupled to BM0_PG rail 518 in the upper region of row RW51. BM0_PG stubs 519(3) and 519(4) are coupled to BM0_PG rail 518 in the lower region of row RW53. The ability to couple BM0_PG stubs 519(1)-519(4) to the corresponding rails in BM0_PG rail 518 is... Figures 5B-5C The advantages of this arrangement are, in other words, the advantages of the alternating row arrangement architecture revealed in this paper.

[0170] In Figure 5A , CLK-net-CP and CLK-net-CPB are routed using M0_rte segments and M1_rte segments. In Figure 5B , CLK-net-CPBB is routed using BM0_LI structure 520(1). The corresponding SDFQ cell region according to the other approach (not shown) does not include a BM0_LI structure, and (B) routes each of CLK-net-CP, CLK-net-CPB, and CLK-net-CPBB using M0_rte segments and M1_rte segments. According to the other approach, all three clock networks exist on the front side of the corresponding SDFQ cell region, which increases M0 routing congestion, which increases parasitic capacitance, which results in slower operating speed and increased power consumption. In contrast, SDFQ D1 cell region having front side 548F and back side 548R reduces M0 routing congestion compared to the corresponding SDFQ cell region according to the other approach, and thus reduces parasitic capacitance by moving CLK-net-CPBB to back side 548R using BM0_LI structure 520(1). Thus, SDFQ D1 cell region having front side 548F and back side 548R advantageously exhibits faster operating speed and reduced power consumption compared to the corresponding SDFQ cell region according to the other approach.

[0171] Figure 6 is a flowchart 600 of a method of fabricating a memory device according to some embodiments.

[0172] According to some embodiments, the method of flowchart (flowchart) 600 may, for example, be implemented using EDA system 800 Figure 8 , discussed below, and IC fabrication system 900 Figure 9 , discussed below. Examples of devices that can be fabricated according to the method of flowchart 600 include devices based on the layout diagrams disclosed herein, among others.

[0173] In Figure 6 , the method of flowchart 600 includes blocks 602-604. At block 602, a layout diagram is generated, including one or more of the layout diagrams disclosed herein, a layout diagram corresponding to one or more of the devices disclosed herein, among others. According to some embodiments, block 602 may, for example, be implemented using EDA system 800 Figure 8 , discussed below. Flow proceeds from block 602 to block 604.

[0174] At block 604, according to the layout diagram, at least one of the following is performed: (A) one or more lithography exposures are performed, or (B) one or more lithography masks are fabricated, or (C) one or more components in a layer of a device, e.g., a semiconductor element, are fabricated. See the discussion below of Figure 9 the IC fabrication system 900 of FIG. 1.

[0175] Figure 7A is a flowchart 710A of a method of fabricating a device according to some embodiments.

[0176] The flowchart 710A is an example of the block 604 of Figure 6 The flowchart 710A includes blocks 712-716. The flowchart 710A shows the following order: block 712→ block 714→ block 716. In some embodiments, other orders of blocks 712-720 are provided Figure 7B The examples provided in the context of the flowchart 710A assume that the first, second, and third orthogonal directions are parallel to the X-axis, Y-axis, and Z-axis, respectively. The method of the flowchart 710A may, for example, be implemented using the IC fabrication system 900 Figure 9 discussed below, according to some embodiments. Examples of devices that can be fabricated according to the method of the flowchart 710A include devices based on the layout maps disclosed herein, etc.

[0177] At block 712, active regions are formed in alternating first and second rows, where the first and second rows include first and second cell regions, respectively, and where each of the first and second cell regions includes active regions, respectively. Examples of active regions include the AR structures 235D1(1), 235D1(2), 235D2(1), and 235D2(2) of FIG. 2, etc. Examples of the first rows are the odd rows RW1, RW3, and RW5 of FIG. 1, Figure 2B Figure 1A the odd rows RW1, RW3, and RW5 of FIG. 1, Figure 1B-1C the RW7 and RW9 of FIG. 1, etc. Examples of the second rows are the even rows RW2, RW4, and RW6 of FIG. 1, Figure 1A the RW8 and RW10 of FIG. 1, etc. Examples of the first cell regions include the first cell regions 102(1)-102(8) of FIG. 2, Figure 1B-1C the first cell regions 102(9)-102(12) of FIG. 2, etc. Examples of the second cell regions include the 104(1)-104(7) of FIG. 2, Figure 1A the 104(8)-104(11) of FIG. 2, etc. Flow proceeds from block 712 to block 714. Figure 1B-1C Figure 1A At block 714, first conductors are formed in a first metallization layer over the active regions, the first conductors including first and second power grid (PG) segments and one or more routing (RTE) segments in each of the first and second cell regions. Examples of the first metallization layer are the MET0 layer 108 of FIG. 1, Figure 1B-1C the MET0 layer 108 of FIG. 1,

[0178] At block 714, first conductors are formed in a first metallization layer over the active regions, the first conductors including first and second power grid (PG) segments and one or more routing (RTE) segments in each of the first and second cell regions. Examples of the first metallization layer are the MET0 layer 108 of FIG. 1, Figure 1A-1C the MET0 layer 108 of FIG. 1, Figure 2A-2B ​​of the MET0 layer 208, etc. Examples of first PG segments include Figure 1A of the M0_PG segment 112 in the upper region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the upper region of the odd rows RW1-RW5 of the memory array 100, Figure 1A of the M0_PG segment 112 in the upper region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the upper region of the odd rows RW1-RW5 of the memory array 100, Figure 1B of the M0_PG segment 112 in the upper region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the upper region of the odd rows RW1-RW5 of the memory array 100, Figure 1B of the M0_PG segment 112 in the upper region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the upper region of the odd rows RW1-RW5 of the memory array 100, Figure 2A-2B of the M0_PG segment 112 in the upper region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the upper region of the odd rows RW1-RW5 of the memory array 100. Examples of second PG segments include Figure 1A of the M0_PG segment 112 in the lower region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the lower region of the odd rows RW1-RW5 of the memory array 100, Figure 1A of the M0_PG segment 112 in the lower region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the lower region of the odd rows RW1-RW5 of the memory array 100, Figure 1B of the M0_PG segment 112 in the lower region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the lower region of the odd rows RW1-RW5 of the memory array 100, Figure 1B of the M0_PG segment 112 in the lower region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the lower region of the odd rows RW1-RW5 of the memory array 100, Figure 2A-2B of the M0_PG segment 112 in the lower region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the lower region of the odd rows RW1-RW5 of the memory array 100. Examples of M0_rte segments include Figure 1A-1C the M0_rte segment 114 in the first cell regions 102(1)-102(8) of the memory array 100, Figure 1B-1C the M0_rte segment 115 in the first cell regions 102(1)-102(8) of the memory array 100, Figure 1C the M0_rte segment 116 in the first cell regions 102(1)-102(8) of the memory array 100, Figure 2A-2B the M0_rte segment 214 in the first cell regions 102(1)-102(8) of the memory array 100, etc. Flow proceeds from block 714 to block 716.

[0179] At block 716, a first buried conductor is formed in a first buried metallization layer beneath the active region, the first buried conductor including: first and second buried power grid (BPG) segments in each first cell region; and one or more buried local interconnect (BLI) structures in each second cell region, each first cell region not including a BLI structure. Examples of first buried metallization layers are Figure 2A-2B of the layer BMET0 209 of the memory array 100, etc. Examples of first BPG segments include the BM0_PG tracks 118 in the upper region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the upper region of the odd rows RW1-RW5 of the memory array 100, Figure 1A of the BM0_PG tracks 118 in the upper region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the upper region of the odd rows RW1-RW5 of the memory array 100, Figure 1A of the BM0_PG tracks 118 in the upper region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the upper region of the odd rows RW1-RW5 of the memory array 100, Figure 1B of the BM0_PG tracks 118 in the upper region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the upper region of the odd rows RW1-RW5 of the memory array 100, Figure 1B of the BM0_PG tracks 118 in the upper region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the upper region of the odd rows RW1-RW5 of the memory array 100, Figure 2A-2B of the BM0_PG tracks 118 in the upper region of the first cell regions 102(1)-102(8) of the memory array 100, and more generally in the upper region of the odd rows RW1-RW5 of the memory array 100. Examples of second BPG segments include Figure 1ABM0_PG tracks 118 in the lower regions of the first cell regions 102(1)-102(8) of the Figure 1A in the lower regions of the odd rows RW1-RW5 of the Figure 1B in the lower regions of the first cell regions 102(9)-102(12) of the Figure 1B in the lower regions of the odd rows RW7-RW9 of the Figure 2A-2B the portion of the BM0_PG track 218(1) in the row RW3 of the

[0180] Examples of BLI structures include Figure 1A the BM0_LI structures 120(1)-120(8) in the Figure 1B-1C 120(9)-120(14) in the Figure 2A-2B 220(1) in the Examples of first cell regions that do not include BLI structures include Figure 1A the first cell regions 102(1)-102(8) of the Figure 1B-1C 102(9)-102(12) of the

[0181] In some embodiments, the forming the first conductors of block 714 positions the first and second PG segments to be adjacent to the first (e.g., top) and second (e.g., bottom) sides, respectively, of the first and second cell regions, respectively, with respect to a given first cell region and a given second cell region. The direction, for example, is parallel to the Y-axis.

[0182] In some embodiments, the forming the first buried conductors of block 716 positions each of the first and second BPG segments of each second cell region to be adjacent to the first (e.g., top) side and the second (e.g., bottom) side, respectively, with respect to a given direction (e.g., parallel to the Y-axis) of the cell region.

[0183] In some embodiments, the forming the first conductors of block 714 forms each of the first BPG segment and the second BPG segment to be wider than each of the first PG segment and the second PG segment with respect to a given direction (e.g., parallel to the Y-axis). Examples of each of the first and second BPG segments being wider than each of the first and second PG segments include Figure 2A-2B each of the BM0_PG tracks 218(1) and 218(2) in the

[0184] In some embodiments, the forming the first conductors of block 714 forms at least a portion of at least one of the one or more BLI structures to be wider than each of the first and second BPG segments. Examples of BLI structures having at least a portion that is wider than each of the first and second BPG segments include the BLI structures Figure 1Athe portion of each of the BM0 LI structures 120(1)-120(2), 120(4)-120(5), 120(7)-120(8) of the BM0 LI structure 120(3) and the BLI structure Figure 1B-1C the portion of each of the BM0 LI structures 120(9) and 120(12) of the BM0 LI structure 120(10), and the BLI structure Figure 1A-1C each BM0 PG track 118 of the BM0 PG structure 116, Figure 2A-2B the BM0 LI structure 220(1) of the BM0 LI structure 220, Figure 2A-2B each of the BM0 PG tracks 218(1)-218(2) of the BM0 PG structure 216, or the like.

[0185] In some embodiments, the forming of the first conductors of block 714 also forms at least one of the one or more BLI structures to include a portion that extends through a central region of a corresponding second cell region. Examples of such BLI structures include the BM0 LI structures 120(1)-120(2), 120(4)-120(5), 120(7)-120(9), and 120(12) of the corresponding second cell regions 104(1)-104(2), 104(4), 104(4), 104(6)-104(8), and 104(10), and the like.

[0186] In some embodiments, the forming of the active regions of block 712 forms at least one of the second cell regions to include two or more BLI structures. Examples of such second cell regions include Figure 1A the second cell region 104(4) of the BM0 LI structure 120(3) and the BLI structure Figures 1 B-1 C the second cell regions 104(9) and 104(11) of the BM0 LI structure 120(10) and the BLI structure Figure 1 A the BM0 LI structures 120(4) and 120(5) of the BM0 LI structure 120(3) and the BLI structure Figures 1 B-1 C the BM0 LI structures 120(10)-120(11) and 120(13)-120(14) of the BM0 LI structure 120(10) and the BLI structure.

[0187] In some embodiments, the forming of the active regions of block 712 forms a first one of the first cell regions and a first one of the second cell regions, and further forms the first first cell region and the first second cell region to have substantially the same width and to be aligned with each other, and wherein the first first cell region and the first second cell region include a larger cell region. Examples of the first first cell region and the first second cell region include the following pairs: Figure 1 A the first cell region 102(1) and the second cell region 104(2) of the BM0 LI structure 120(3) and the BLI structure Figure 1 A the first first cell region 102(7) and the first second cell region 104(6) of the BM0 LI structure 120(3) and the BLI structure Figures 1 B-1 C the first first cell region 102(9) and the first second cell region 104(9) of the BM0 LI structure 120(10) and the BLI structure Figures 1 B-1 Cthe first first cell region 102(11) and the first second cell region 104(11) of the first row RW1. The indicated pairings respectively include Figure 1 A the high cell regions 106(1)-106(2) of the second row RW2, and Figures 1 B-1 C the high cell regions 106(3)-106(4) of the third row RW3.

[0188] In some embodiments, the forming the active regions of block 712 forms at least one of a second row to further include one or more of the first cell regions. Examples of such a second row include Figures 1 B-1 C the even rows RW8 and RW10 of the first row RW1, additionally including the corresponding first cell regions 102(10) and 102(12).

[0189] In some embodiments, the forming the active regions of block 712 forms at least one of a second cell region such that one or more of the BLI structures has a concave polygonal shape. Examples of such a second cell region include Figure 1 A the second cell regions 104(1), 104(4), and 104(7) of the first row RW1, and Figures 1 B-1 C the second cell regions 104(8) and 104(10) of the second row RW2, which respectively include Figure 1 A the concave polygonal BM0 LI structures 120(1), 120(4)-120(5), and 120(8) of the first row RW1, and Figures 1 B-1 C the concave polygonal BM0 LI structures 120(9) and 120(12) of the second row RW2.

[0190] In some embodiments, the concave polygonal shape of at least one of the one or more BLI structures is P-shaped, Z-shaped, or U-shaped. Examples of P-shaped BLI structures include Figure 1 A the P-shaped BM0 LI structures 120(1), 120(4), and 120(8) of the first row RW1, and the like. Examples of Z-shaped BLI structures include Figures 1 B-1 C the Z-shaped BM0 LI structures 120(9) and 120(12) of the second row RW2, and the like. Examples of U-shaped BLI structures include Figure 1 A the U-shaped BM0 LI structure 120(5) of the first row RW1, and the like.

[0191] In some embodiments, the forming the active regions of block 712 forms at least one of a second cell region such that one or more of the BLI structures has a convex polygonal shape. Examples of such a second cell region include Figure 1 A the second cell regions 104(2), 104(3), and 104(5) of the first row RW1, and Figures 1 B-1 C the second cell regions 104(9) and 104(11) of the second row RW2, which respectively include Figure 1 A the convex polygonal BM0 LI structures 120(2), 120(3), and 120(6)-120(7) of the first row RW1, and Figures 1 B-1 CThe convex polygonal BMO_LI structures 120(10)-120(11) and 120(13)-120(14). In some embodiments, at least one of the convex polygonal shapes of one or more BLI structures in at least one second unit region has a high rectangular shape, wherein the high rectangular shape is higher than the minimum width of the conductive segment in the first buried metallization layer relative to a given direction (e.g., parallel to the Y-axis). Examples of high rectangular BLI structures include BMO_LI structures 120(2) and 120(7) in the corresponding second unit regions 104(2) and 104(6).

[0192] In some embodiments, the flow sequence in flowchart 710A is described as forming the front layer before the back layer. An example of the front layer is... Figures 2A-2B Examples include the front side 211F, etc. The reverse side example is... Figures 2A-2B The back side of the 211R, etc.

[0193] Figure 7B This is a flowchart 710B of a method for manufacturing an apparatus according to some embodiments.

[0194] Similar to flowchart 710B Figure 7A The flowchart 710A is different from the flowchart 710A, because, for example, flowchart 710B contains the same boxes as flowchart 710, namely boxes 712-716. The difference between flowchart 710B and flowchart 710A is that flowchart 710B shows a different flow sequence through boxes 712-716 compared to the sequence shown in flowchart 710A.

[0195] exist Figure 7B In flowchart 710B, the following sequence is shown: box 712 → box 716 → box 714. In some embodiments, the sequence of flowchart 710B is described as forming the back layer before the front layer.

[0196] Figure 8 This is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0197] In some embodiments, the EDA system 800 includes an automatic placement and routing (APR) system. In some embodiments, the EDA system 800 is a general purpose computing device that includes a hardware processor 802 and a non-transitory computer-readable storage medium 804. The storage medium 804 has encoded therein (i.e., stored) computer program code 806 (i.e., a set of executable instructions). Execution of the instructions 806 by the hardware processor 802 represents, at least in part, an EDA tool that implements, for example, part or all of a method such as the method of generating a layout disclosed herein, a method of generating a layout (e.g., a layout disclosed herein or a layout corresponding to a device disclosed herein), etc., in accordance with one or more embodiments (hereinafter, the referenced processes and / or methods).

[0198] The storage medium 804 stores, among other things, a layout 811, such as a layout disclosed herein, etc.

[0199] The processor 802 is electrically coupled to the computer-readable storage medium 804 via a bus 808. The processor 802 is also electrically coupled to an I / O interface 810 via the bus 808. A network interface 812 is also electrically connected to the processor 802 via the bus 808. The network interface 812 is connected to a network 814, enabling the processor 802 and the computer-readable storage medium 804 to connect to external elements via the network 814. The processor 802 is configured to execute the computer program code 806 encoded in the computer-readable storage medium 804, to enable the system 800 to be used to perform part or all of the referenced processes and / or methods. In one or more embodiments, the processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0200] In one or more embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 804 includes semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a hard disk, and / or an optical disk. In one or more embodiments using an optical disk, the computer-readable storage medium 804 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0201] In one or more embodiments, storage medium 804 stores computer code 806 configured to cause system 800 (where such execution represents, at least in part, an EDA tool) to perform some or all of the processes and / or methods mentioned. In one or more embodiments, storage medium 804 also stores information that facilitates performance of some or all of the processes and / or methods mentioned. In one or more embodiments, storage medium 804 stores a library of standard cells 807 including such standard cells disclosed herein. In some embodiments, storage medium 804 stores one or more layout maps 811.

[0202] EDA system 800 includes input / output (I / O) interface 810. I / O interface 810 is coupled to external circuits. In one or more embodiments, I / O interface 810 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor direction keys for communicating information and instructions to processor 802.

[0203] EDA system 800 also includes network interface 812 coupled to processor 802. Network interface 812 allows system 800 to communicate with network 814 to which one or more other computer systems are connected. Network interface 812 includes a wireless network interface, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as ETHERNET, USB, or IEEE- 1364. In one or more embodiments, some or all of the processes and / or methods mentioned are implemented in two or more systems 800.

[0204] System 800 is configured to receive information through I / O interface 810. Information received through I / O interface 810 includes one or more of instructions, data, design rules, a library of standard cells, and / or other parameters for processing by processor 802. This information is communicated to processor 802 via bus 808. EDA system 800 is configured to receive information related to a user interface (UI) through I / O interface 810. This information is stored in computer-readable medium 804 as UI 842.

[0205] In some embodiments, part or all of the mentioned processes and / or methods are implemented as a standalone software application program executed by a processor. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application program that is part of an additional software application program. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a plug-in of a software application program. In some embodiments, at least one of the mentioned processes and / or methods is implemented as a software application program that is part of an EDA tool. In some embodiments, part or all of the mentioned processes and / or methods are implemented as a software application program used by EDA system 800. In some embodiments, the mentioned processes and / or methods are implemented using a tool such as tools available from CADENCE DESIGN SYSTEMS, Inc. (e.g., ) or another suitable layout generation tool to generate a layout including standard cells.

[0206] In some embodiments, the processes are implemented as functions of programs stored in a non-transitory computer-readable recording medium. Examples of the non-transitory computer-readable recording medium include, but are not limited to, one or more of external / removable and / or internal / built-in storage or memory units, such as one or more of optical discs (e.g., DVD, DVD), magnetic discs, such as a hard disc; semiconductor memory, such as ROM, RAM, memory card, etc.

[0207] Figure 9 is a block diagram of an integrated circuit (IC) manufacturing system 900 and an IC manufacturing flow associated therewith, according to some embodiments.

[0208] In some embodiments, based on the layout map generated by block 602 of Figure 6 , IC manufacturing system 900 implements block 604 of Figure 6 , where at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a preliminary semiconductor integrated circuit is manufactured using manufacturing system 900. In some embodiments, IC manufacturing system 900 implements the flow of Figures 7A-7B

[0209] In some embodiments, IC manufacturing system 900 implements block 606 of Figure 9 ​In particular embodiments, IC fabrication system 900 includes entities that interact with each other in the design, development, and fabrication cycle and / or services related to fabricating IC elements 960, such as design company 920, mask company 930, and IC foundry ("fab") 950. The entities in system 900 are connected through a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is various different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design company 920, mask company 930, and IC foundry 950 are owned by a single larger company. In some embodiments, two or more of design company 920, mask company 930, and IC foundry 950 coexist in a common facility and use common resources.

[0210] Design company (or design team) 920 generates IC design layout 922. IC design layout 922 includes various geometric patterns designed for IC elements 960. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that make up various components of IC elements 960 to be fabricated. The layers combine to form various IC functions. For example, a portion of IC design layout 922 includes various IC features to be formed in a semiconductor substrate, such as active regions, gate terminals, source and drain regions, metal lines or vias for interlayer interconnections, and openings for bond pads (e.g., a silicon wafer), as well as various material layers disposed on the semiconductor substrate. Source / drain regions can refer to either source or drain individually or collectively, depending on the context. Design company 920 implements appropriate design procedures to form IC design layout 922. The design process includes one or more of logic design, physical design, or layout routing. IC design layout 922 is represented in one or more data files with geometric pattern information. For example, IC design layout 922 is expressed in a GDSII file format or a DFII file format.

[0211] Mask shop 930 includes data preparation 932 and mask manufacturing 934. Mask shop 930 uses IC design layout 922 to manufacture one or more masks 935 used to manufacture layers of IC device 960 according to IC design layout 922. Mask shop 930 performs mask data preparation 932 in which IC design layout 922 is converted into representative data files ("RDFs"). Mask data preparation 932 provides the RDFs to mask manufacturing 934. Mask manufacturing 934 includes a mask writer. The mask writer converts the RDFs into an image on a substrate (e.g., a reticle (reticle version) or a semiconductor wafer). The design layout is manipulated by mask data preparation 932 to conform to the particular characteristics of the mask writer and / or the requirements of IC fab 950. In Figure 9 In some embodiments, mask data preparation 932 and mask manufacturing 934 are collectively referred to as mask data preparation.

[0212] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC) that uses lithography enhancement techniques to compensate for image errors, e.g., that can be caused by diffraction, interference, other process effects, etc. OPC adjusts IC design layout 922. In some embodiments, mask data preparation 932 includes further resolution enhancement techniques (RET), e.g., off-axis illumination, sub-resolution assist features, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0213] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that checks the IC design layout that has been processed in OPC against a set of mask creation rules that include certain geometric and / or connectivity restrictions to ensure sufficient margins to account for variability of semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout to compensate for restrictions during mask manufacturing 934, which can undo some of the modifications performed by OPC in order to satisfy the mask creation rules.

[0214] In some embodiments, mask preparation 932 includes lithography process check (LPC), which simulates the processing to be performed by IC foundry 950 to manufacture IC device 960. LPC simulates this processing based on IC design layout 922 to manufacture a simulated manufactured device, such as IC device 960. The processing parameters in the LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and / or other aspects of the manufacturing flow. The LPC takes into account various factors, such as, for example, aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and / or combinations thereof. In some embodiments, after the simulated manufactured device is manufactured through LPC, if the shapes of the simulated device are not close enough to meet design rules, then OPC and / or MRC are repeated to further refine IC design layout 922.

[0215] The above description of mask preparation 932 has been simplified for clarity. In some embodiments, mask preparation 932 includes additional features, such as logic operations (LOP), to modify the IC design layout according to manufacturing rules. Additionally, the processing applied to IC design layout 922 during preparation 932 can be performed in various different orders.

[0216] After mask preparation 932 and during mask manufacturing 934, a mask 935 or a set of masks 935 is manufactured based on the modified IC design layout. In some embodiments, an e-beam or multiple e-beam mechanism is used to form a pattern on a mask (reticle or pellicle) based on the modified IC design layout. The mask is formed in a variety of techniques. In some embodiments, the mask is formed using binary technology. In some embodiments, the mask pattern includes opaque regions and transparent regions. A beam of radiation, such as an ultraviolet (UV) beam, used to expose a layer of image-sensitive material (e.g., photoresist) that has been coated on a wafer, is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the mask. In another example, the mask is formed using phase-shift technology. In a phase-shift mask (PSM), various features in the pattern formed on the mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shift mask is an attenuated PSM or an alternating PSM. The mask resulting from mask manufacturing 934 is used in a variety of processes. For example, such a mask is used in an ion implantation process to form various doped regions in a semiconductor wafer, in an etching process to form various etched regions in a semiconductor wafer, and / or in other suitable processes.

[0217] IC fab 950 is an IC manufacturing enterprise that includes one or more fabrication facilities for manufacturing a variety of different IC products. In some embodiments, IC wafer foundry 950 is a semiconductor foundry. For example, there can be one fabrication facility for front-end manufacturing of multiple IC products (front-end-of-line (FEOL) manufacturing), while a second fabrication facility can provide back-end manufacturing of IC products for interconnection and packaging (back-end-of-line (BEOL) manufacturing), and a third fabrication facility can provide other services for foundry business.

[0218] IC wafer foundry 950 uses the mask (or masks) 935 manufactured by mask house 930 to manufacture IC elements 960 using manufacturing tools 952. Thus, IC wafer foundry 950 uses IC design layout 922, at least indirectly, to manufacture IC elements 960. In some embodiments, semiconductor wafer 953 is manufactured by IC wafer foundry 950 using mask (or masks) 935 to form IC elements 960. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer also includes one or more of various doped regions, dielectric properties, multilayer interconnects, etc. (formed in subsequent manufacturing steps).

[0219] In some embodiments, an apparatus comprises: a plurality of first rows and a plurality of second rows in alternation, comprising a plurality of first cell regions and a plurality of second cell regions, respectively; each first cell region and second cell region comprising a plurality of active regions, respectively; in a first metallization layer over the active regions: each of the first cell regions and the second cell regions comprises: first and second power grid (PG) segments and one or more routing (RTE) segments; in a first buried metallization layer under the active regions: each first cell region comprises: first and second buried power grid (BPG) segments; each second cell region comprises: one or more buried local interconnect (BLI) structures; each first cell region does not comprise a BLI structure.

[0220] In some embodiments, the first and second rows extend along a first direction; at least a portion of each of the first and second PG segments, the one or more RTE segments, the first and second BPG segments, and the one or more BLI structures extend along the first direction; relative to a second direction perpendicular to the first direction, the first and second PG segments are adjacent to respective first and second sides of the first and second cell regions, respectively.

[0221] In some embodiments, relative to the first direction, each of the first and second BPG segments of each second cell region is adjacent to respective first and second sides of the first cell region, respectively.

[0222] In some embodiments, relative to the second direction perpendicular to the first direction, each of the first and second BPG segments is wider than each of the first and second PG segments.

[0223] In some embodiments, at least one of the one or more BLI structures has at least one portion that is wider than each of the first and second BPG segments with respect to a second direction perpendicular to the first direction.

[0224] In some embodiments, the at least one second unit region includes two or more BLI structures.

[0225] In some embodiments, the first and second rows extend along a first direction; at least a portion of each of the first and second PG segments, the one or more RTE segments, the first and second BPG segments, and the one or more BLI structures extend along the first direction; and with respect to a second direction perpendicular to the first direction, at least one of the one or more BLI structures includes a portion that extends through a central zone of a corresponding second unit region.

[0226] In some embodiments, the first and second rows extend along a first direction; with respect to a second direction perpendicular to the first direction, the first unit regions and the second unit regions are adjacent to each other. With respect to the first direction, a first first unit region and a first second unit region have substantially the same width and are aligned with each other. The first first unit region and the first second unit region comprise larger unit regions.

[0227] In some embodiments, the first second unit region further includes: third and fourth BPG segments.

[0228] In some embodiments, at least one of the second rows further includes: one or more first unit regions.

[0229] In some embodiments, in the at least one second unit region, at least one of the one or more BLI structures has a concave polygonal shape.

[0230] In some embodiments, the concave polygonal shape of at least one of the one or more BLI structures of the at least one second unit region has: a P-shape, a Z-shape, or a U-shape.

[0231] In some embodiments, in the at least one second unit region, at least one of the one or more BLI structures has a convex polygonal shape.

[0232] In some embodiments, the convex polygonal shape of at least one of the one or more BLI structures of the at least one second unit region has a high rectangular shape; and with respect to a second direction perpendicular to the first direction, the high rectangular shape is higher than a minimum width of the conductive segments in the first buried metallization layer.

[0233] In some embodiments, a method (of forming a device) includes: forming a plurality of active regions in an alternating plurality of first rows and a plurality of second rows, the first rows and the second rows respectively comprising a plurality of first cell regions and a plurality of second cell regions, each of the first cell regions and the second cell regions respectively comprising a plurality of active regions; forming a plurality of first conductors in a first metallization layer over the active regions, the plurality of first conductors comprising: first and second power grid (PG) segments and one or more routing (RTE) segments in each of the first cell regions and the second cell regions; forming a plurality of first buried conductors in a first buried metallization layer under the active regions, the plurality of first buried conductors comprising: in each first cell region, first and second buried power grid (BPG) segments; in each second cell region, one or more buried local interconnect (BLI) structures; and forming the first buried conductors further comprises: configuring each first cell region to not include a BLI structure.

[0234] In some embodiments, the first rows and the second rows extend along a first direction; forming the first conductors comprises forming each of the first and second PG segments and the one or more RTE segments to extend in the first direction; forming the first buried conductors comprises forming at least a portion of each of the first and second BPG segments and the one or more BLI structures to extend in the first direction; and relative to a second direction perpendicular to the first direction, forming the first conductors comprises positioning the first and second PG segments respectively adjacent respective first and second sides of the first cell regions and the second cell regions.

[0235] In some embodiments, relative to the first direction, forming the first buried conductors comprises positioning each of the first and second BPG segments of each second cell region respectively adjacent respective first and second sides of the plurality of first cell regions.

[0236] In some embodiments, relative to the second direction perpendicular to the first direction, forming the first buried conductors comprises forming each of the first and second BPG segments to be wider than each of the first and second PG segments.

[0237] In some embodiments, relative to the second direction perpendicular to the first direction, forming the first buried conductors comprises forming at least a portion of at least one of the one or more BLI structures to be wider than each of the first and second BPG segments.

[0238] In some embodiments, an apparatus comprises: a plurality of first rows and a plurality of second rows in alternation, comprising a plurality of first cell regions and a plurality of second cell regions, respectively; each first cell region and second cell region comprises a plurality of active regions, respectively; in a first metallization layer above the active regions: each of the first cell regions and the second cell regions comprises: first and second power grid (PG) segments and one or more routing (RTE) segments; in a first buried metallization layer below the active regions: each first cell region comprises: first and second buried power grid (BPG) segments; each second cell region comprises: one or more buried local interconnect (BLI) structures; each first cell region does not comprise a BLI structure; and in at least one second cell region, a shape of at least one of the one or more buried BLI structures is different from a smallest rectangular shape of instances of the one or more buried BLI structures, the smallest rectangular shape having a smallest width of a conductive segment in the first buried metallization layer.

[0239] In some embodiments, in at least one second cell region, at least one of the one or more BLI structures has a concave polygonal shape.

[0240] In some embodiments, the concave polygonal shape of at least one of the one or more BLI structures of the at least one second cell region has: a P-shape; a Z-shape; or a U-shape.

[0241] In some embodiments, in at least one second cell region, at least one of the one or more BLI structures has a convex polygonal shape.

[0242] In some embodiments, the convex polygonal shape of at least one of the one or more BLI structures of the at least one second cell region has a high rectangular shape; and the high rectangular shape is taller than a smallest width of a conductive segment in the first buried metallization layer with respect to a second direction perpendicular to the first direction.

[0243] One of ordinary skill in the art will readily see from the disclosure herein that one or more of the disclosed embodiments realize one or more of the advantages listed above. Many of those advantages are applicable in various combinations. One of ordinary skill in the art will readily see from the disclosure herein how various changes and modifications can be made to the specific embodiments described above without departing from the scope of the disclosure. Accordingly, the protection sought herein is as set forth in the claims below, along with their equivalents.

Claims

1. An apparatus, comprising: comprise a plurality of first and second unit areas, respectively; each of the plurality of first and second unit areas correspondingly comprises a plurality of active areas; in a first metallization layer over the plurality of active areas: each of the plurality of first and second unit areas comprises: first and second power grid segments; and one or more wiring segments; and in a first buried metallization layer under the plurality of active areas: each of the first unit areas comprises: first and second buried power grid segments; and each of the second unit areas comprises: one or more buried local interconnect structures; and each of the first unit areas does not comprise a buried local interconnect structure.

2. The apparatus of claim 1, wherein: the plurality of first and second rows extend along a first direction; at least a portion of each of the first and second power grid segments, the one or more wiring segments, the first and second buried power grid segments, and the one or more buried local interconnect structures extend in the first direction; and with respect to a second direction perpendicular to the first direction, the first and second power grid segments are respectively adjacent to respective first and second sides of the plurality of first and second unit areas.

3. The apparatus of claim 1, wherein: with respect to a second direction perpendicular to the first direction, each of the first and second buried power grid segments is wider than each of the first and second power grid segments.

4. The apparatus of claim 1, wherein: with respect to a second direction perpendicular to the first direction, at least a portion of at least one of the one or more buried local interconnect structures is wider than each of the first and second buried power grid segments.

5. The apparatus of claim 1, wherein: the plurality of first and second rows extend along a first direction; at least a portion of each of the first and second power grid segments, the one or more wiring segments, the first and second buried power grid segments, and the one or more buried local interconnect structures extend in the first direction; and with respect to a second direction perpendicular to the first direction, at least one of the one or more buried local interconnect structures comprises a portion that extends through a center region of the corresponding second unit area.

6. The apparatus of claim 1, wherein: at least one of the plurality of second rows further comprises: one or more of the first unit areas. comprise a plurality of first and second unit areas, respectively; 7. An apparatus, comprising: each of the plurality of first and second unit areas correspondingly comprises a plurality of active areas; in a first metallization layer over the plurality of active areas: each of the plurality of first and second unit areas comprises: first and second power grid segments; and one or more wiring segments; and in a first buried metallization layer under the plurality of active areas: each of the first unit areas comprises: first and second buried power grid segments; and each of the second unit areas comprises: one or more buried local interconnect structures; and each of the first unit areas does not comprise a buried local interconnect structure. each of the second unit areas comprises: one or more buried local interconnect structures; each of the first unit areas does not comprise a buried local interconnect structure; and in at least one of the second unit areas, at least one of the one or more buried local interconnect structures has a shape that is different from a minimum rectangular shape of instances of the one or more buried local interconnect structures, the minimum rectangular shape has a minimum width of a conductive segment in the first buried metallization layer.

8. The apparatus of claim 7, wherein, in at least one of the second unit areas, at least one of the one or more buried local interconnect structures has a concave polygonal shape.

9. The apparatus of claim 8, wherein, the concave polygonal shape of at least one of the one or more buried local interconnect structures of at least one of the second unit areas has: a P-shape; a Z-shape; or a U-shape.

10. The apparatus of claim 7, wherein, in at least one of the second unit areas, at least one of the one or more buried local interconnect structures has a convex polygonal shape.

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