Data acquisition unit circuit for seismograph

Abstract

The utility model discloses a data acquisition unit circuit used for a seismograph, an output positive terminal US + of a detector is electrically connected with UO + through a resistor R14, a resistor R16 and a resistor R18 which are connected in series, an output negative terminal US-of the detector is electrically connected with UO-through a resistor R15, a resistor R17 and a resistor R19 which are connected in series, a connection point of a resistor R12 and a resistor R13 is grounded, one end of the resistor R12 far away from the connection point is electrically connected with the output positive terminal US + of the detector, and the other end of the resistor R12 far away from the connection point is electrically connected with the output negative terminal US-of the detector. The end, away from the connecting point, of the resistor R13 is electrically connected with the output negative end US-of the detector, the connecting point of the capacitor C45 and the capacitor C46 is grounded, the end, away from the connecting point, of the capacitor C45 is electrically connected with the resistor R14 and the resistor R16, the end, away from the connecting point, of the capacitor C46 is electrically connected with the resistor R15 and the resistor R17, one end of the capacitor C47 is electrically connected with the resistor R16 and the resistor R18, and the other end of the capacitor C47 is electrically connected with the resistor R16 and the resistor R18. And one end of the capacitor C48 is electrically connected with the UO +, and the other end of the capacitor C48 is electrically connected with the UO-. The circuit provided by the utility model has the advantages of simple circuit, good interference elimination and suppression effects and the like.

Description

Technical Field

[0001] This utility model relates to the field of data acquisition technology, specifically a data acquisition unit circuit for a seismograph. Background Technology

[0002] The amplitude of the original signal output by the existing seismograph detector is uncertain, and the interference frequency components are complex. Noise or interference sources include interference caused by electromagnetic fields generated by natural phenomena or electrical appliances, thermal noise generated by internal components of the instrument, and interference from the internal power supply of the system. Noise or interference sources act on circuits and devices that are sensitive to noise and interference sources through the coupling channel, affecting the acquired data. Therefore, it is necessary to eliminate and suppress interference. Utility Model Content

[0003] The purpose of this invention is to provide a simple circuit for a data acquisition unit of a seismograph that effectively eliminates and suppresses interference.

[0004] The technical solution adopted by this utility model to solve its technical problem is:

[0005] A data acquisition unit circuit for a seismograph, characterized in that it includes a detector and a signal preprocessing differential circuit, wherein the signal preprocessing differential circuit includes resistors R12, R13, R14, R15, R16, R17, R18, and R19, and capacitors C45, C46, ​​C47, and C48, and the detector outputs a positive terminal U. S+ Through resistors R14, R16, and R18 connected in series, and U O+ Electrical connection, the detector output negative terminal U S- Through resistors R15, R17, and R19 connected in series, and U O- Electrical connection;

[0006] Resistors R12 and R13 are connected in series, with the connection point between them grounded. The end of resistor R12 furthest from the connection point is connected to the positive output terminal U of the detector. S+ Electrical connection: The end of resistor R13 furthest from the connection point is connected to the negative output terminal U of the detector. S- Electrical connection;

[0007] Capacitors C45 and C46 are connected in series. The connection point of capacitors C45 and C46 is grounded. The end of capacitor C45 furthest from the connection point is electrically connected to resistors R14 and R16. The end of capacitor C46 furthest from the connection point is electrically connected to resistors R15 and R17.

[0008] One end of the capacitor C47 is electrically connected between the resistor R16 and the resistor R18, and the other end is electrically connected between the resistor R17 and the resistor R19;

[0009] One end of the capacitor C48 is electrically connected between the resistor R16 and the resistor R18, and the other end is electrically connected between the resistor R17 and the resistor R19; O+ One end of the capacitor C48 is electrically connected between the resistor R16 and the resistor R18, and the other end is electrically connected between the resistor R17 and the resistor R19; O- One end of the capacitor C48 is electrically connected between the resistor R16 and the resistor R18, and the other end is electrically connected between the resistor R17 and the resistor R19;

[0010] The two output ends of the detector are connected with the differential input end of the pre-processing circuit, the resistor R12 and the resistor R13 serve as the input signal bias to the ground, the resistor R14 and the capacitor C45, the resistor R15 and the capacitor C46 form a low-pass filter circuit, filter out the high-frequency interference components in the low-frequency signal, realize filtering, the resistor R16, the resistor R17 and the resistor R18, the resistor R19 form the differential single-end isolation resistance of the anti-aliasing filter, the capacitor C47 and the capacitor C48 form the differential capacitor of the anti-aliasing filter, and a first-order anti-aliasing filter and a second-order anti-aliasing filter are formed, and the frequency suppression effect is good after the second-order anti-aliasing filter, and the filtering performance is high.

[0011] The signal pre-processing differential circuit further comprises a bidirectional transient suppression diode D1, the bidirectional transient suppression diode D1 is connected between U S+ and U S- The overvoltage and overcurrent protection circuit is composed, the amplitude of the input signal is limited, and the subsequent digital circuit is prevented from being damaged due to the fault of the detector or other reasons.

[0012] The signal pre-processing differential circuit further comprises a clamping protection circuit D2 and D3, the clamping protection circuit D2 is arranged at U O+ , the clamping protection circuit D3 is arranged at U O- , the clamping protection circuit D2 comprises a voltage VS25, a voltage VD25, a diode D21 and a diode D22, the voltage VS25 is electrically connected with the voltage VD25 in series through the diode D21 and the diode D22, and a junction point between the diode D21 and the diode D22 is electrically connected with U O+ .

[0013] The clamping protection circuit D3 comprises a voltage VS25, a voltage VD25, a diode D31 and a diode D32, the voltage VS25 is electrically connected with the voltage VD25 in series through the diode D31 and the diode D32, and a junction point between the diode D31 and the diode D32 is electrically connected with U O- .

[0014] When the input voltage is in the reference voltage range of the analog-digital converter, the two series-connected diodes work in the off state, and the capacitance is generally small, and the influence on the collected signal can be ignored, when the input voltage appears a peak signal and is out of limit, the corresponding diode is turned on, and the input voltage can be clamped to the full bias voltage value of the analog-digital converter.

[0015] The utility model also has analog switch chip U8, two single pole double throw switches S1 and S2 are built in analog switch chip U8, single pole double throw switch S1 includes D1 pin, S1A pin and S1B pin, single pole double throw switch S2 includes D2 pin, S2A pin and S2B pin, D1 pin is connected with the positive end OUT of detector output + Electric connection, S1A pin is connected with the positive end U of detector output S+ Electric connection, S1B pin is connected with the PA5 pin of singlechip detection voltage value, and S1B pin is connected with voltage VDD3 through resistance R6;

[0016] D2 pin is connected with the negative end OUT of detector output - Electric connection, S2A pin is connected with the negative end U of detector output S- Electric connection, S2B pin is grounded;

[0017] The EN pin of analog switch chip U8 is connected with the PC0 pin of singlechip, and the low level output of singlechip PC0 pin enables analog switch chip U8, and the EN pin is connected with voltage VDD3 through resistance R5;

[0018] The IN1 pin, IN2 pin and IN3 pin of analog switch chip U8 are connected with the PA3 pin of singlechip, and the switch state of two single pole double throw switches S1 and S2 is switched by the logic input pin IN1, IN2 and IN3 of singlechip control analog switch chip U8;

[0019] The D1 pin and S1B pin of analog switch chip U8 are closed and the D2 pin and S2B pin are closed by the low level output of PA3 pin, and the circuit works in the state of measuring the resistance of detector, and the D1 pin and S1A pin of analog switch chip U8 are closed and the D2 pin and S2A pin are closed by the high level output of PA3 pin, and the circuit works in the state of data acquisition and processing;

[0020] In the process of transporting and laying the seismometer in the field, the problem of detector falling off exists, which leads to the failure of collection work, and the static resistance of the detector needs to be checked to determine whether the connection is normal, two working states are designed in the circuit, which can measure the resistance of the detector to determine whether the detector is connected normally, and can also perform data acquisition and processing work.

[0021] The VCC pin of the analog switch chip U8 is electrically connected with external VDD3, the VSS pin is electrically connected with external VS25, and the GND pin is grounded.

[0022] Capacitors C40 and C41 are connected in series between VDD3 and VS25, and the connecting point of the capacitors C40 and C41 is grounded.

[0023] The capacitors C40 and C41 are used to realize power filtering.

[0024] The resistance calculation formula of the detector is as follows:

[0025]

[0026] In the formula, R d is the static resistance (kΩ) of the detector, V d is the detection point analog voltage (V) calculated by the internal ADC of the single-chip microcomputer through the PA5 pin sampling, 3 is the power voltage (V) of the voltage dividing circuit.

[0027] The resistance R14 and the capacitor C45, the resistance R15 and the capacitor C46 constitute a low-pass filter circuit, and the upper limit cutoff frequency formula of the low-pass filter circuit is as follows:

[0028]

[0029] In the formula, f H is the upper limit frequency (Hz) of the low-pass filter, ω H is the angular frequency (rad / s) of the input signal, and τ is the time constant (s).

[0030] The setting of the low-pass filter circuit can filter out the high-frequency interference components in the low-frequency signal, the low-pass filter circuit has the characteristics that the higher the frequency is, the greater the amplitude attenuation is, the value of the resistance and the capacitor of the low-pass filter circuit can be adjusted to flexibly adjust the upper limit cutoff frequency, and the targeted filtering effect is realized.

[0031] The model of the analog switch chip U8 is ADG1633.

[0032] The utility model also is equipped with simulation circuit, simulation circuit includes baud rate tester XBP1, baud rate tester XBP2, simulation signal preprocessing differential circuit, power V1 and power V2, power V1 and power V2 voltage and frequency are same, the structure of simulation signal preprocessing differential circuit is same with signal preprocessing differential circuit, and the input of simulation signal preprocessing differential circuit is equipped with power V1 and power V2, the anode of power V1 is connected with the input anode of simulation signal preprocessing differential circuit, the cathode of power V1 is connected with the anode of power V2, the cathode of power V2 is connected with the input cathode of simulation signal preprocessing differential circuit, and the junction of power V1 and power V2 is grounded;

[0033] The IN of baud rate tester XBP1 and baud rate tester XBP2 + The IN is connected with the anode of power V1, and the IN - The OUT of baud rate tester XBP1 is connected with the cathode of power V2, and the OUT + The OUT is connected with one end of capacitor C47, and the OUT - The OUT is connected with the other end of capacitor C47.

[0034] The OUT of baud rate tester XBP2 + The OUT is connected with one end of capacitor C48, and the OUT - The OUT is connected with the other end of capacitor C48.

[0035] Baud rate tester XBP1 shows first-order anti-aliasing filter effect, and baud rate tester XBP2 shows second-order anti-aliasing filter effect, and through simulation circuit, the filter performance of signal preprocessing differential circuit can be measured.

[0036] The utility model discloses a signal preprocessing differential circuit uses the circuit board to adopt four layer board structure, the circuit board includes the signal layer in top layer, the power layer and ground layer in middle layer and the signal layer in bottom layer;

[0037] The ground layer is physically divided into two copper skins that do not affect each other and serves as analog ground and digital ground respectively, and the analog circuit device and the digital circuit device are placed in different regions and connected by a 0Ω resistor.

[0038] The four layer board structure isolates the signal layer, the ground layer and the power layer from each other, effectively reduces the influence of power noise on the circuit, one-point grounding effectively isolates the analog circuit device and the digital circuit device, ensures the effective isolation of analog ground and digital ground, reduces the ground end coupling of the analog circuit and the digital circuit, and simultaneously weakens the influence of digital signal switching noise on the analog circuit.

[0039] The utility model discloses beneficial effect is: the two output ends of detector are connected with the differential input of pre -processing circuit, resistance R12 and resistance R13 play the role of input signal bias to ground, resistance R14 and capacitor C45, resistance R15 and capacitor C46 constitute low pass filter circuit, filter the high -frequency interference component in low -frequency signal, realize filtering, resistance R16, resistance R17 and resistance R18, resistance R19 constitute the differential single -end isolation resistance of anti -aliasing filter, capacitor C47 and capacitor C48 constitute the differential capacitor of anti -aliasing filter, respectively form first order anti -aliasing filter and second order anti -aliasing filter, after second order anti -aliasing filter frequency suppression effect is good, and the filtering performance is high, in the process of field transportation, the layout seismograph, there is the problem of detector drop, lead to unable to carry out the collection work, need to check the static resistance of detector to judge whether the connection is normal, this circuit designs two kinds of working conditions, can measure detector resistance to judge whether the detector is connected normally, also can carry out the processing work of data acquisition, baud rate tester XBP1 shows first order anti -aliasing filter effect, baud rate tester XBP2 shows second order anti -aliasing filter effect, through simulation circuit, the filtering performance of signal preprocessing differential circuit can be measured. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 It is the signal preprocessing differential circuit diagram of the utility model.

[0041] Figure 2 It is the simulation circuit diagram of the utility model. DETAILED DESCRIPTION

[0042] The utility model will be explained below in connection with the drawings and examples.

[0043] As shown in the attached Figure 1 , a kind of data acquisition unit circuit for seismograph is provided with detector and signal preprocessing differential circuit, the signal preprocessing differential circuit includes resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, capacitor C45, capacitor C46, capacitor C47, capacitor C48, bidirectional transient suppression diode D1 and clamping protection circuit D2 and D3, the detector output positive terminal U S+ It is connected with U O+ In sequence, resistance R15, resistance R17, resistance R19 are connected in series with U S- It is connected with U O- Electrically connected;

[0044] Resistance R12 and resistance R13 are connected in series, the joint of resistance R12 and resistance R13 is grounded, the end of resistance R12 away from joint is connected with detector output positive terminal US+ an electrical connection is made between one end of the resistor R13, which is away from the junction, and the negative terminal of the detector output U S- an electrical connection is made between the other end of the resistor R13, which is away from the junction, and the positive terminal of the detector output U

[0045] a bidirectional transient suppression diode D1 is connected between U S+ and U S- ;

[0046] a capacitor C45 and a capacitor C46 are connected in series, one end of the capacitor C45, which is away from the junction, is electrically connected between the resistor R14 and the resistor R16, one end of the capacitor C46, which is away from the junction, is electrically connected between the resistor R15 and the resistor R17, and the junction of the capacitor C45 and the capacitor C46 is grounded;

[0047] one end of the capacitor C47 is electrically connected between the resistor R16 and the resistor R18, and the other end of the capacitor C47 is electrically connected between the resistor R17 and the resistor R19;

[0048] one end of the capacitor C48 is electrically connected to U O+ , and the other end of the capacitor C48 is electrically connected to U O- ;

[0049] a clamping protection circuit D2 is arranged at U O+ , and a clamping protection circuit D3 is arranged at U O- , the clamping protection circuit D2 comprises a voltage VS25, a voltage VD25, a diode D21 and a diode D22, the voltage VS25 is electrically connected to the voltage VD25 through the diode D21 and the diode D22 connected in series, and the junction between the diode D21 and the diode D22 is electrically connected to U O+ ;

[0050] the clamping protection circuit D3 comprises a voltage VS25, a voltage VD25, a diode D31 and a diode D32, the voltage VS25 is electrically connected to the voltage VD25 through the diode D31 and the diode D32 connected in series, and the junction between the diode D31 and the diode D32 is electrically connected to U O- ;

[0051] The two output ends of the detector are connected with the differential input ends of the pre-processing circuit, the resistance R12 and the resistance R13 play a role of biasing the input signal to the ground, the bidirectional transient suppression diode D1 constitutes an overvoltage and overcurrent protection circuit, the amplitude of the input signal is limited, the input signal amplitude is prevented from being too large to damage the subsequent digital circuit due to the fault of the detector or other reasons, the resistance R14 and the capacitor C45, the resistance R15 and the capacitor C46 constitute a low-pass filter circuit, high-frequency interference components in the low-frequency signal are filtered out, filtering is realized, the resistance R16, the resistance R17 and the resistance R18, the resistance R19 constitute differential single-end isolation resistors of the anti-aliasing filter, the capacitor C47 and the capacitor C48 constitute differential capacitors of the anti-aliasing filter, a first-order anti-aliasing filter and a second-order anti-aliasing filter are formed respectively, the frequency suppression effect is good after the second-order anti-aliasing filter, and the filtering performance is high.

[0052] The clamping protection circuit is arranged, when the input voltage is in the reference voltage range of the analog-to-digital converter, the two series-connected diodes work in the cutoff state, and the capacitance is generally small, the influence on the collected signal can be ignored, when a sharp signal appears in the input voltage and is out of limit, the corresponding diode is turned on, and the input voltage can be clamped to the full-bias voltage value of the analog-to-digital converter.

[0053] The effective signal output by the detector is a low-frequency signal, which is input in a differential form into the signal pre-processing differential circuit, the nominal values of the two differential single-end components in the signal pre-processing differential circuit need to be kept strictly symmetrical and consistent, the resistances used in the signal pre-processing differential circuit adopt resistances with an accuracy of 1%, in this embodiment, the resistance value of the resistance R12 is the same as that of the resistance R13, the resistance value of the resistance R14 is the same as that of the resistance R15, the resistance value of the resistance R16 is the same as that of the resistance R17, the resistance value of the resistance R18 is the same as that of the resistance R19, the capacity of the capacitor C45 is the same as that of the capacitor C46, and the capacity of the capacitor C47 is the same as that of the capacitor C48.

[0054] In this embodiment, the model of the bidirectional transient suppression diode D1 is SMAJ5.0CA.

[0055] The resistance R14 and the capacitor C45, the resistance R15 and the capacitor C46 constitute a low-pass filter circuit, and the upper limit cutoff frequency formula of the low-pass filter circuit is:

[0056]

[0057] In the formula, f H is the upper limit frequency (Hz) of the low-pass filter, ω H is the angular frequency (rad / s) of the input signal, and τ is the time constant (s);

[0058] The low-pass filter circuit can filter out high-frequency interference components in low-frequency signals. The low-pass filter circuit has the characteristic that the higher the frequency, the greater the amplitude attenuation. By adjusting the resistance and capacitance values of the low-pass filter circuit, the upper cut-off frequency can be flexibly adjusted to achieve targeted filtering effect.

[0059] This embodiment is also provided with an analog switch chip U8, which is internally provided with two single-pole double-throw switches S1 and S2. The single-pole double-throw switch S1 includes a D1 pin, an S1A pin and an S1B pin. The single-pole double-throw switch S2 includes a D2 pin, an S2A pin and an S2B pin. The D1 pin is electrically connected to the positive output end OUT + of the detector. The S1A pin is electrically connected to the positive output end U S+ of the detector. The S1B pin is electrically connected to the PA5 pin of the single-chip microcomputer for detecting voltage value. The S1B pin is electrically connected to the voltage VDD3 through the resistance R6.

[0060] The D2 pin is electrically connected to the negative output end OUT - of the detector. The S2A pin is electrically connected to the negative output end U S- of the detector. The S2B pin is grounded.

[0061] The EN pin of the analog switch chip U8 is electrically connected to the PC0 pin of the single-chip microcomputer. The PC0 pin of the single-chip microcomputer outputs a low level to enable the analog switch chip U8. The EN pin is electrically connected to the voltage VDD3 through the resistance R5.

[0062] The IN1 pin, the IN2 pin and the IN3 pin of the analog switch chip U8 are electrically connected to the PA3 pin of the single-chip microcomputer. The switching states of the two single-pole double-throw switches S1 and S2 are switched by the logic input pins IN1, IN2 and IN3 of the analog switch chip U8 controlled by the single-chip microcomputer.

[0063] The PA3 pin outputs a low level to control the D1 pin and the S1B pin of the analog switch chip U8 to be closed and the D2 pin and the S2B pin to be closed. The circuit works in the state of measuring the resistance value of the detector. The PA3 pin outputs a high level to control the D1 pin and the S1A pin of the analog switch chip U8 to be closed and the D2 pin and the S2A pin to be closed. The circuit works in the state of data acquisition and processing.

[0064] The VCC pin of the analog switch chip U8 is electrically connected to the external VDD3. The VSS pin is electrically connected to the external VS25. The GND pin is grounded.

[0065] The capacitor C40 and the capacitor C41 are connected in series between the VDD3 and the VS25. The connection point of the capacitor C40 and the capacitor C41 is grounded. The capacitor C40 and the capacitor C41 are used for power filtering.

[0066] In the process of field transportation and seismic instrument layout, there is a problem of geophone falling off, which leads to the failure of acquisition work. The static resistance of the geophone needs to be checked to determine whether the connection is normal. This circuit is designed to have two working states, which can measure the resistance value of the geophone to determine whether the connection is normal, and can also process data acquisition.

[0067] In this embodiment, the geophone resistance calculation formula is:

[0068]

[0069] In the formula, R d is the static resistance of the geophone (kΩ), V d is the detection point analog voltage (V) calculated by the single-chip microcomputer internal ADC through the PA5 pin sampling, 3 is the power supply voltage (V) of the voltage dividing circuit, and the resistance R6 is 4.7kΩ.

[0070] In this embodiment, the analog switch chip U8 uses ADG1633 chip with a conduction resistance of 4.5Ω and low power consumption. In this embodiment, only two switches S1 and S2 of the ADC1633 chip are used.

[0071] This embodiment also has a simulation circuit for simulating the signal preprocessing differential circuit using Multisim tool, which includes a baud rate tester XBP1, a baud rate tester XBP2, a simulation signal preprocessing differential circuit, a power supply V1 and a power supply V2. The voltage and frequency of the power supply V1 and the power supply V2 are the same, the structure of the simulation signal preprocessing differential circuit is the same as that of the signal preprocessing differential circuit, the input end of the simulation signal preprocessing differential circuit is provided with the power supply V1 and the power supply V2, the positive electrode of the power supply V1 is electrically connected with the positive electrode of the input end of the simulation signal preprocessing differential circuit, the negative electrode of the power supply V1 is electrically connected with the positive electrode of the power supply V2, the negative electrode of the power supply V2 is electrically connected with the negative electrode of the input end of the simulation signal preprocessing differential circuit, and the junction of the power supply V1 and the power supply V2 is grounded.

[0072] The IN + pin of the baud rate tester XBP1 and the baud rate tester XBP2 is electrically connected with the positive electrode of the power supply V1, the IN - pin is electrically connected with the negative electrode of the power supply V2, the OUT + pin of the baud rate tester XBP1 is electrically connected with one end of the capacitor C47, and the OUT - pin is electrically connected with the other end of the capacitor C47.

[0073] The OUT + pin of the baud rate tester XBP2 is electrically connected with one end of the capacitor C48, and the OUT - pin is electrically connected with the other end of the capacitor C48.

[0074] The baud rate tester XBP1 shows the first-order anti-aliasing filter effect, and the baud rate tester XBP2 shows the second-order anti-aliasing filter effect, and the filter performance of the signal preprocessing differential circuit can be measured through the simulation circuit. In this embodiment, the second-order anti-aliasing filter effect has a faster overall frequency roll-off speed than the first-order anti-aliasing filter effect, and has a better frequency suppression effect near 1.024 MHz.

[0075] In this embodiment, the frequency of the power supply V1 and the power supply V2 is 31.25 Hz, the peak voltage is V1, the resistance of the resistor R12 and the resistor R13 is 10kΩ, the resistance of the resistor R14 and the resistor R15 is 100Ω, the resistance of the resistor R16 and the resistor R17 is 120Ω, the resistance of the resistor R18 and the resistor R19 is 120Ω, and the capacity of the capacitor C45 and the capacitor C46 is 22nF. ， The capacity of the capacitor C47 and the capacity of the capacitor C48 is 33nF.

[0076] The circuit board used by the signal preprocessing differential circuit adopts a four-layer board structure, and the circuit board includes a signal layer located on the top layer, a power supply layer and a ground layer located on the middle layer, and a signal layer located on the bottom layer.

[0077] The ground layer covers the entire board surface, and each device in the internal circuit of the same level is connected to the ground through punching, which shortens the circuit backflow path and reduces the interference of environmental noise. The ground layer is physically divided into two copper skins that do not affect each other, which are used as an analog ground and a digital ground, respectively. The analog circuit devices and the digital circuit devices are placed in different regions and connected by a 0Ω resistor.

[0078] The four-layer board structure isolates the signal layer, the ground layer and the power supply layer from each other, which can effectively reduce the influence of power supply noise on the circuit. One-point grounding effectively isolates the analog circuit devices and the digital circuit devices, ensures the effective isolation of the analog ground and the digital ground, ensures the potential balance of the analog ground and the digital ground, reduces the ground end coupling of the analog circuit and the digital circuit, and at the same time weakens the influence of digital signal switching noise on the analog circuit.

[0079] In the wiring process of the multilayer circuit board in this embodiment, the front and back traces are arranged in a cross form as much as possible to reduce parasitic capacitance.

[0080] After the analog signal is preprocessed, the analog-to-digital converter will generate quantization noise. The analog sine wave signal is converted into a digital signal using the analog-to-digital converter, and the signal-to-noise ratio calculation formula of the quantization noise is:

[0081] SNR=6.02N+1.76;

[0082] Wherein SNR is the signal-to-noise ratio (dB) of quantization noise, N is the sampling bit number of the analog-to-digital converter;

[0083] The signal-to-noise ratio is improved with the increase of the sampling bit number of the analog-to-digital converter, and the selection of the sampling bit number of the analog-to-digital converter is related to the effective number of bits (ENOB), which is a parameter for measuring the conversion quality of the analog-to-digital converter to the input signal, and the calculation formula of ENOB is:

[0084]

[0085] Wherein ENOB is the effective number of bits (bit), l V uF is the full-scale voltage value (V), V In is the input voltage value (V);

[0086] The reference voltage amplitude of the analog-to-digital converter commonly used in the seismograph is mostly 2.5V, and the effective number of bits of the analog-to-digital converter can be obtained,

[0087]

[0088] When the amplitude of the minimum effective signal that can be collected by the seismograph is required to be 5 microvolts, the effective number of bits of the analog-to-digital converter should be at least 18.93 to meet the requirement, and the signal-to-noise ratio of the analog-to-digital converter can be calculated to be at least 115.72 decibels.

[0089] The utility model uses when:

[0090] 1, the singlechip PC0 pin output low level enables ADG1633, and the PA3 pin outputs low level to control ADG1633 D1 and S1B close, D2 and S2B close, at this time, the circuit works in the state of measuring the resistance value of the detector, and the voltage value of the detection point is measured by the internal ADC detection IO port PA5 of the singlechip, and the static resistance value of the detector can be calculated;

[0091] 2, according to the static resistance value of the detector, it is judged whether the detector connection is normal, after judging that the detector connection is normal, the singlechip PC0 pin output low level enables ADG1633, and the PA3 pin outputs high level to control ADG1633 D1 and S1A close, D2 and S2A close, at this time, the circuit works in the state of collecting data, and the two output ends of the detector are connected with the input end of the signal preprocessing differential circuit, and the effective signal output by the detector is a low-frequency signal, and the noise and interference in the low-frequency signal are filtered out by the signal preprocessing differential circuit, and filtering is realized;

[0092] 3、The preprocessed analog signal is input to an analog-digital converter, the analog sinusoidal wave signal is converted into a digital signal by using the analog-digital converter, the sampling bit number of the analog-digital converter is improved, the signal-to-noise ratio of quantization noise is improved, and noise is reduced.

Claims

1. A data acquisition unit circuit for a seismic instrument, characterized by: There are a detector and a signal pre-processing differential circuit, the signal pre-processing differential circuit includes resistance R12, resistance R13, resistance R14, resistance R15, resistance R16, resistance R17, resistance R18, resistance R19, capacitor C45, capacitor C46, capacitor C47 and capacitor C48, the detector output positive end U S+ Connected in series with resistance R14, resistance R16, resistance R18 and U O+ Connected in series with resistance R15, resistance R17, resistance R19 and U S- Connected in series with resistance R15, resistance R17, resistance R19 and U O- Connected in series with resistance R15, resistance R17, resistance R19 and U The resistor R12 is connected in series with the resistor R13, the joint of the resistor R12 and the resistor R13 is grounded, and the end of the resistor R12 away from the joint is connected with the positive terminal U of the detector output S+ The resistor R13 is connected in series with the resistor R12, the joint of the resistor R13 and the resistor R12 is grounded, and the end of the resistor R13 away from the joint is connected with the negative terminal U of the detector output S- The resistor R13 is connected in series with the resistor R12, the joint of the resistor R13 and the resistor R12 is grounded, and the end of the resistor R13 away from the joint is connected with the negative terminal U of the detector output Capacitor C45 and capacitor C46 are connected in series, the joint of capacitor C45 and capacitor C46 is grounded, one end of capacitor C45 away from the joint is electrically connected between resistor R14 and resistor R16, and one end of capacitor C46 away from the joint is electrically connected between resistor R15 and resistor R17; One end of capacitor C47 is electrically connected between resistor R16 and resistor R18, and the other end is electrically connected between resistor R17 and resistor R19; One end of the capacitor C48 is connected to U O+ An electrical connection, the other end of which is connected to U O- An electrical connection.

2. A data acquisition unit circuit for a seismic instrument according to claim 1, wherein: The signal pre-processing differential circuit further comprises a bidirectional transient suppression diode D1 connected between U S+ and U S- .

3. A data acquisition unit circuit for a seismic instrument according to claim 1 or 2, characterized in that: The signal pre-processing differential circuit further comprises clamping protection circuits D2 and D3, the clamping protection circuit D2 is arranged at U O+ , and the clamping protection circuit D3 is arranged at U O- , the clamping protection circuit D2 comprises a voltage VS25, a voltage VD25, a diode D21 and a diode D22, the voltage VS25 is electrically connected with the voltage VD25 through the series connection of the diode D21 and the diode D22, and a junction between the diode D21 and the diode D22 is electrically connected with U O+ . The clamping protection circuit D3 comprises a voltage VS25, a voltage VD25, a diode D31 and a diode D32, the voltage VS25 is electrically connected with the voltage VD25 through the series connection of the diode D31 and the diode D32, and the junction between the diode D31 and the diode D32 is electrically connected with U O- is electrically connected.

4. A data acquisition unit circuit for a seismic instrument according to claim 1 or 2, characterized in that: Also provided is an analog switch chip U8, the analog switch chip U8 is built-in two single-pole double-throw switches S1 and S2, the single-pole double-throw switch S1 includes a D1 pin, an S1A pin and an S1B pin, the single-pole double-throw switch S2 includes a D2 pin, an S2A pin and an S2B pin, the D1 pin is electrically connected with the positive end OUT of the detector output + Electrically connected, the S1A pin is electrically connected with the positive end U of the detector output S+ Electrically connected, the S1B pin is electrically connected with the PA5 pin of the single-chip microcomputer detection voltage value, and the S1B pin is electrically connected with the voltage VDD3 through the resistor R6. D2 pin and the negative end of the detector output OUT - electrical connection, S2A pin and the negative end of the detector output U S- electrical connection, S2B pin to ground; The EN pin of analog switch chip U8 is electrically connected with the PC0 pin of the single-chip microcomputer, and the single-chip microcomputer PC0 pin outputs low level to enable the analog switch chip U8, and the EN pin is electrically connected with the voltage VDD3 through the resistor R5; The IN1 pin, IN2 pin and IN3 pin of the analog switch chip U8 are electrically connected with the PA3 pin of the single-chip microcomputer, and the switching state of the two single-pole double-throw switches S1 and S2 is controlled by the single-chip microcomputer to switch the logic input pin IN1, IN2 and IN3 of the analog switch chip U8; The PA3 pin outputs low level to control the D1 pin and S1B pin of the analog switch chip U8 to be closed and the D2 pin and S2B pin to be closed, and the circuit works in the state of measuring the resistance value of the detector, and the PA3 pin outputs high level to control the D1 pin and S1A pin of the analog switch chip U8 to be closed and the D2 pin and S2A pin to be closed, and the circuit works in the state of data acquisition and processing.

5. A data acquisition unit circuit for a seismic instrument according to claim 4, wherein: The VCC pin of the analog switch chip U8 is electrically connected with the external VDD3, the VSS pin is electrically connected with the external VS25, and the GND pin is grounded; Capacitors C40 and C41 are connected in series between VDD3 and VS25, and the joint of capacitors C40 and C41 is grounded.

6. A data acquisition unit circuit for a seismic instrument according to claim 4, wherein: The resistance value calculation formula of the detector is: In the formula, R d is the static resistance value (kΩ) of the detector, V d is the detection point analog voltage (V) calculated by the single-chip microcomputer internal ADC through the PA5 pin sampling, and VDD3 is the power supply voltage (V) of the voltage dividing circuit.

7. A data acquisition unit circuit for a seismic instrument as claimed in claim 1 or 2 or 5 or 6, characterized in that: The resistor R14 and capacitor C45, resistor R15 and capacitor C46 constitute a low-pass filter circuit, and the upper limit cutoff frequency formula of the low-pass filter circuit is: where f H is the upper frequency of the low pass filter (Hz), ω H is the angular frequency of the input signal (rad / s), and τ is the time constant (s).

8. A data acquisition unit circuit for a seismic instrument according to claim 4, wherein: The model of the analog switch chip U8 is ADG1633.

9. A data acquisition unit circuit for a seismic instrument as claimed in claim 1 or 2 or 5 or 6, characterized in that: An emulation circuit is further provided, the emulation circuit comprises a baud rate tester XBP1, a baud rate tester XBP2, an emulation signal pre-processing differential circuit, a power supply V1 and a power supply V2, the power supply V1 and the power supply V2 have the same voltage and frequency, the structure of the emulation signal pre-processing differential circuit is the same as that of the signal pre-processing differential circuit, the input end of the emulation signal pre-processing differential circuit is provided with the power supply V1 and the power supply V2, the positive electrode of the power supply V1 is electrically connected with the positive electrode of the input end of the emulation signal pre-processing differential circuit, the negative electrode of the power supply V1 is electrically connected with the positive electrode of the power supply V2, the negative electrode of the power supply V2 is electrically connected with the negative electrode of the input end of the emulation signal pre-processing differential circuit, and the joint of the power supply V1 and the power supply V2 is grounded; IN of the baud rate tester XBP1, baud rate tester XBP2 + The pin is electrically connected with the positive pole of the power supply V1, IN - The pin is electrically connected with the negative pole of the power supply V2, OUT of the baud rate tester XBP1 + The pin is electrically connected with one end of the capacitor C47, OUT - The pin is electrically connected with the other end of the capacitor C47 The OUT of the baud rate tester XBP2 + The pin is electrically connected with one end of the capacitor C48. - The pin is electrically connected with the other end of the capacitor C48.

10. A data acquisition unit circuit for a seismic instrument as claimed in claim 1 or 2 or 5 or 6, characterized in that: The circuit board used by the signal pre-processing differential circuit adopts a four-layer board structure, and the circuit board comprises a signal layer located at the top layer, a power supply layer and a ground layer located at the middle layer, and a signal layer located at the bottom layer; The ground layer is physically divided into two copper skins which are not affected by each other and are respectively used as an analog ground and a digital ground, and analog circuit devices and digital circuit devices are placed in different regions and are connected by a 0Ω resistor.

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