FeFET-based complete nonvolatile full adder circuit

Abstract

The utility model discloses a fully non-volatile full adder circuit based on a FeFET. The fully non-volatile full adder circuit comprises a standard sum solving module and a carry module, wherein the standard sum solving module consists of a pre-charging module I, a pull-down module I and an operation module I; the carry module consists of a pre-charging module II, a pull-down module II and an operation module II; the pre-charging module I and the pre-charging module II are used for preparing for standard sum calculation and carry calculation; the pull-down module I and the pull-down module II are used for forming an earth passage in an evaluation stage; the first operation module and the second operation module respectively comprise a plurality of FeFETs, the FeFETs receive and store input signals in a pre-charging stage as a non-volatile switch state, a conduction path formed by connecting part of the FeFETs in series is obtained according to the switch state in an evaluation stage, logic operation is executed on related input signals on the conduction path, and a non-volatile operation result is generated; the method has the advantages that frequent access to operands is avoided, data in the operation process can be correctly recovered after power failure, and the operation accuracy and the calculation efficiency in an unstable power supply environment are improved.

Description

Technical Field

[0001] This utility model belongs to the field of digital circuits and relates to an in-memory adder circuit, and more particularly to a fully non-volatile full adder circuit based on FeFET (Ferroelectric Field-Effect Transistor). Background Technology

[0002] In IoT edge chips powered by ambient energy harvesting technology, computing processes are susceptible to power intermittentity. During power outages, data cannot be saved promptly, affecting computational continuity and data security. To overcome the impact of power outages, building fully non-volatile chips that support field backup and data recovery using emerging non-volatile memory (NVM) devices is considered a promising solution. Among numerous non-volatile memory devices, ferroelectric field-effect transistors (FeFETs) have attracted particular attention due to their low power consumption, high on / off ratio, and compatibility with existing CMOS processes.

[0003] Addition is one of the most fundamental operations, whether performing simple arithmetic or complex data processing tasks. Currently, researchers have proposed several 1-bit full adder designs based on novel non-volatile memory devices. However, these designs only use non-volatile memory to store one of their operands, failing to store all operands and the output. This necessitates frequent operand access during computation, and the calculated result requires additional static latch storage. Furthermore, data cannot be effectively retained and recovered in power-down environments, thus failing to achieve truly non-volatile functionality.

[0004] How to design a fully non-volatile full adder circuit using FeFET to not only reduce the energy consumption caused by frequent access to operands during operation, but also to achieve on-site data backup and efficient recovery after power failure is an important problem that urgently needs to be solved. Summary of the Invention

[0005] This invention addresses the technical problem in existing IoT edge chip technologies where operands are frequently accessed during computation and computation results cannot be effectively recovered in the event of power failure. It provides a fully non-volatile full adder circuit based on FeFET, which can back up operands in FeFET to reduce the energy consumption associated with operand access. Furthermore, it utilizes non-volatile interconnects to store computation results and enable power-loss recovery, thereby completing a fully non-volatile full adder operation. This provides a new approach for designing circuit unit libraries for IoT edge chips.

[0006] The technical solution adopted by this utility model to solve the above-mentioned technical problems is as follows: a fully non-volatile full adder circuit based on FeFET, characterized in that it includes a sum-finding module and a carry-finding module. The sum-finding module is composed of a pre-charge module one, a pull-down module one, and an arithmetic module one working together. The carry-finding module is composed of a pre-charge module two, a pull-down module two, and an arithmetic module two working together.

[0007] The precharge module one and the precharge module two are used to receive high power signals from their respective first precharge input terminal and second precharge input terminal during the precharge phase, thereby charging their respective first precharge output terminal and second precharge output terminal to a high level, so as to prepare for summation operation and carry operation respectively.

[0008] The first and second pull-down modules are used to receive a low power signal from their respective ground input terminals during the evaluation phase, thereby ensuring that their respective ground output terminals reach a low level.

[0009] The arithmetic input, inverted logic output, and logic output of the first arithmetic module are connected to the ground output of the first pull-down module and the first and second precharge outputs of the first precharge module. The first arithmetic module includes multiple first FeFETs. These first FeFETs receive and store input signals as non-volatile switching states during the precharge phase. During the evaluation phase, a conduction path is obtained based on the pre-stored switching states, consisting of a portion of the first FeFETs connected in series, leading from the arithmetic input of the first arithmetic module to the logic output or inverted logic output. Evaluation logic operations are performed on the relevant input signals along this conduction path to generate a non-volatile operation result, which is then output to the logic output or inverted logic output. The operation result output by the logic output is the sum of its bits. The arithmetic input, inverted logic output, and logic output of the second arithmetic module are also connected. The output terminal is connected to the ground output terminal of the pull-down module two, the first precharge output terminal and the second precharge output terminal of the precharge module two. The arithmetic module two includes multiple second FeFETs. These second FeFETs receive and store input signals as non-volatile switching states during the precharge phase. During the evaluation phase, a conduction path is obtained based on the pre-stored switching states. This path is formed by connecting some of the second FeFETs in series and extends from the arithmetic input terminal of the arithmetic module two to the logic output terminal or the inverse logic output terminal. Evaluation logic operations are performed on the relevant input signals along this conduction path to generate a non-volatile operation result. The operation result is then output to the logic output terminal or the inverse logic output terminal. The operation result output by the logic output terminal is the carry. The input signals include two local input signals, two inverse local input signals, one carry input signal, and one inverse carry input signal.

[0010] The full adder circuit retains the calculation result after power failure and automatically resumes the calculation state after power is restored.

[0011] Further defined, the full adder circuit has a high power input terminal, a low power input terminal, a clock control input terminal, and a first signal write terminal, a second signal write terminal, a third signal write terminal, a first inverted signal write terminal, a second inverted signal write terminal, and a third inverted signal write terminal; the high power input terminal is connected to a high power signal, i.e., power supply VDD, and is respectively connected to the first precharge input terminal and the second precharge input terminal of precharge module one and precharge module two to provide operating voltage; the low power input terminal is connected to a low power signal, i.e., ground GND, and is respectively connected to the ground input terminal of pull-down module one and pull-down module two; the clock control input terminal is connected to a low level or a high level. This circuit controls the operating phases of the full adder. When the clock control input is low, the full adder is in the pre-charge phase; when the clock control input is high, the full adder is in the evaluation phase. The first signal write terminal and the second signal write terminal each receive one local input signal, the first inverted signal write terminal and the second inverted signal write terminal each receive one inverted local input signal, the third signal write terminal receives the carry input signal, and the third inverted signal write terminal receives the inverted carry input signal. The inverted local input signal is obtained by logically inverting the corresponding local input signal, and the inverted carry input signal is obtained by logically inverting the carry input signal. This defines the external ports of the full adder circuit and the signals that should be connected to each port, facilitating the integration of the full adder circuit.

[0012] Preferably, the first arithmetic module includes 10 first FeFETs. The drains of the first and third first FeFETs are connected and connected to the inverted logic output terminal of the first arithmetic module. The drains of the second and fourth first FeFETs are connected and connected to the logic output terminal of the first arithmetic module. The gates of the first and fourth first FeFETs are both connected to the first signal writing terminal. The gates of the second and third first FeFETs are both connected to the first inverted signal writing terminal. The sources of the first and second first FeFETs are connected and connected to the drains of the fifth and seventh first FeFETs, respectively. The sources of the third and fourth first FeFETs are connected and connected to the drains of the sixth and seventh first FeFETs, respectively. The drain of the first FeFET and the drain of the eighth first FeFET are connected. The gates of the fifth and eighth first FeFETs are both connected to the third signal write terminal. The gates of the sixth and seventh first FeFETs are both connected to the third inverse signal write terminal. The sources of the fifth and sixth first FeFETs are respectively connected to the drain of the ninth first FeFET. The sources of the seventh and eighth first FeFETs are respectively connected to the drain of the tenth first FeFET. The gate of the ninth first FeFET is connected to the second signal write terminal. The gate of the tenth first FeFET is connected to the second inverse signal write terminal. The sources of the ninth and tenth first FeFETs are both connected to the operation input terminal of the operation module one. Here, a specific structure of the operation module one is defined. This structure can realize the bit sum operation in full addition, and the switching state and operation result can be stored non-volatilely.

[0013] Preferably, the second arithmetic module includes eight second FeFETs. The drains of the first and third second FeFETs are connected and connected to the inverted logic output of the second arithmetic module. The drains of the second and sixth second FeFETs are connected and connected to the logic output of the second arithmetic module. The gate of the first second FeFET is connected to the third signal writing terminal. The gate of the second second FeFET is connected to the third inverted signal writing terminal. The sources of the first and second second FeFETs are connected and connected to the drains of the fourth and fifth second FeFETs, respectively. The gate of the third second FeFET is connected to the drain of the fifth second FeFET. The gates of both FeFETs are connected to the first signal write terminal. The gates of the fourth and sixth second FeFETs are both connected to the first inverted signal write terminal. The sources of the third and fourth second FeFETs are respectively connected to the drain of the seventh second FeFET. The sources of the fifth and sixth second FeFETs are respectively connected to the drain of the eighth second FeFET. The gate of the seventh second FeFET is connected to the second signal write terminal. The gate of the eighth second FeFET is connected to the second inverted signal write terminal. The sources of the seventh and eighth second FeFETs are both connected to the operation input terminal of the second operation module. Here, a specific structure of the second operation module is defined. This structure enables the carry operation in full addition, and both the switching state and the operation result can be stored non-volatilely.

[0014] Preferably, the pre-charge module one and the pre-charge module two have the same structure, each including four PMOS transistors. The source of the first PMOS transistor and the source of the second PMOS transistor are connected and connected to the first pre-charge input terminal. The source of the third PMOS transistor and the source of the fourth PMOS transistor are connected and connected to the second pre-charge input terminal. The gate of the first PMOS transistor and the gate of the fourth PMOS transistor are both connected to the clock control input terminal. The drain of the first PMOS transistor, the drain of the second PMOS transistor, and the gate of the third PMOS transistor are connected and connected to the first pre-charge output terminal. The drain of the third PMOS transistor, the drain of the fourth PMOS transistor, and the gate of the second PMOS transistor are connected and connected to the first pre-charge output terminal. The gates of the transistors are connected to and to the second precharge output terminal. When the clock control input terminal is low, the first and fourth PMOS transistors are turned on, the high level of the first precharge input terminal is transmitted to the first precharge output terminal, while the third PMOS transistor remains off. The high level of the second precharge input terminal is transmitted to the second precharge output terminal, while the second PMOS transistor remains off, completing the precharge process. When the clock control input terminal is high, the first and fourth PMOS transistors are turned off, entering the evaluation stage. In the evaluation stage, the third PMOS transistor will be turned on according to the low level received at the first precharge output terminal, or the second PMOS transistor will be turned on according to the low level received at the second precharge output terminal. Here, a specific structure for precharge module one and precharge module two is defined, through which the respective first and second precharge output terminals can be charged to a high level to prepare for summation operations and carry operations, respectively.

[0015] Preferably, the first and second pull-down modules have the same structure, each including one NMOS transistor. The source of the NMOS transistor is connected to the ground input terminal, the gate of the NMOS transistor is connected to the clock control input terminal, and the drain of the NMOS transistor is connected to the ground output terminal. When the clock control input terminal is low, the NMOS transistor is turned off; when the clock control input terminal is high, the NMOS transistor is turned on, and the ground output terminal reaches a low level. Here, a specific structure for the first and second pull-down modules is defined, which ensures that their respective ground output terminals reach a low level during the evaluation phase.

[0016] Compared with the prior art, the advantages of this utility model are:

[0017] This invention fully utilizes the non-volatile storage characteristics of FeFETs to achieve effective backup of input signals; it also leverages the non-volatile switching characteristics of FeFETs to effectively preserve the interconnection relationships of circuit units, realizing fully non-volatile full addition operations that are recoverable even after power loss. Furthermore, it employs a dynamic current-mode circuit design, simultaneously obtaining the output signal and its inverse signal, saving dedicated hardware resources for inversion and avoiding logic errors caused by race conditions.

[0018] Compared to designs that store only a portion of the input signals or volatile full adder circuits, this invention stores all input signals as the switching states of FeFETs and then performs specific operations based on the series-parallel relationship of FeFETs. This not only avoids frequent access to operands and reduces computational energy consumption, but also correctly recovers the data from the computation process after a power outage, improving the accuracy and efficiency of computation in scenarios with unstable power supply. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of an N-type FeFET;

[0020] Figure 2 This is a schematic diagram of an NMOS transistor;

[0021] Figure 3 This is a schematic diagram of a PMOS transistor;

[0022] Figure 4 This is a schematic diagram of the FeFET-based fully non-volatile full adder circuit of this invention;

[0023] Figure 5 for Figure 4 The diagram shows the timing simulation results of the FeFET-based fully non-volatile full adder circuit. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings.

[0025] This invention proposes a fully non-volatile full adder circuit based on FeFET, which utilizes N-type FeFET, NMOS transistor and PMOS transistor to realize a fully non-volatile full adder circuit, which can simultaneously output the local sum and carry output of the full adder operation, and the local sum operation result and the carry operation result are non-volatile.

[0026] Figure 1A schematic diagram of an N-type FeFET is given, where the g-terminal is the gate, the s-terminal is the source, and the d-terminal is the drain. When a forward bias voltage is applied to the g-terminal of the N-type FeFET, and this forward bias voltage is greater than a threshold voltage V... TH When a reverse bias voltage is applied to the g-terminal of an N-type FeFET, a conductive channel is formed between the source and drain, putting the N-type FeFET in a "conducting" state, which remains even after the g-terminal voltage is removed. When a reverse bias voltage is applied to the g-terminal of the N-type FeFET, and this reverse bias voltage is greater than the threshold voltage V... TL When the voltage is removed, the conductive channel between the source and drain of the N-type FeFET will disappear, causing the N-type FeFET to be in an "off" state, and this state will remain even after the voltage at the g terminal is removed.

[0027] Figure 2 A schematic diagram of an NMOS transistor is given, where g N The terminal is the gate of an NMOS transistor, s N The terminal is the source of the NMOS transistor, d N The terminal is the drain of the NMOS transistor, and the source of the NMOS transistor is s. N Connect to a low power supply. The on / off state of the NMOS transistor depends on the gate g. N The applied voltage condition. When g N Apply a voltage greater than its threshold voltage V to the terminal thn At that time, s N end and d N A conductive channel is formed between the terminals, and the NMOS transistor is in the "on" state; when g N The voltage applied to the terminal is less than its threshold voltage V thn At that time, s N end and d N When the conductive channel between the terminals disappears, the NMOS transistor is in an "off" state.

[0028] Figure 3 A schematic diagram of a PMOS transistor is given, in which g P The terminal is the gate of the PMOS transistor, s P The terminal is the source of the PMOS transistor, d P The terminal is the drain of the PMOS transistor, and the source of the PMOS transistor is s. P Connect to a high-voltage power supply. The on / off state of the PMOS transistor depends on the gate g. P The applied voltage condition. When g P end and s P The applied voltage between the terminals is less than its threshold voltage V. thp At that time, s P end and d PA conductive channel is formed between the terminals, and the PMOS transistor is in the "on" state; when g P end and s P The applied voltage between the terminals is greater than its threshold voltage V. thp At that time, s P end and d P When the conductive channel between the terminals disappears, the PMOS transistor is in an "off" state.

[0029] This invention proposes a fully non-volatile full adder circuit based on FeFET, such as... Figure 4As shown, it includes a sum-of-the-parts module and a carry-of-the-parts module. The sum-of-the-parts module consists of a precharge module 11, a pull-down module 12, and an operation module 13 working together. The carry-of-the-parts module consists of a precharge module 21, a pull-down module 22, and an operation module 23 working together. Precharge modules 11 and 21 receive high power signals from their respective first and second precharge inputs during the precharge phase, thereby charging their respective first and second precharge outputs to a high level to prepare for summation and carry-of operations, respectively. Pull-down modules 12 and 22 receive low power signals from their respective ground inputs during the evaluation phase, thereby ensuring their respective ground outputs reach a low level. The arithmetic input, inverted logic output !S, and logic output S of arithmetic module 13 are connected to the ground output of pull-down module 12 and the first and second precharge outputs of precharge module 11, respectively. Arithmetic module 13 includes multiple first FeFETs. These first FeFETs receive and store input signals as non-volatile switching states during the precharge phase. During the evaluation phase, a conduction path is obtained based on the pre-stored switching states, consisting of a portion of the first FeFETs connected in series, from the arithmetic input of arithmetic module 13 to the logic output S or the inverted logic output !S. Evaluation logic operations are performed on the relevant input signals along this conduction path to generate a non-volatile operation result, which is then output to the logic output S or the inverted logic output !S. The operation result output by logic output S is the sum of its bits. The arithmetic input, inverted logic output !Cout, and logic output Co of arithmetic module 23 are also connected. `ut` corresponds to the ground output terminal of pull-down module 22, and the first and second precharge output terminals of precharge module 21. Operation module 23 includes multiple second FeFETs. These second FeFETs receive and store input signals as non-volatile switching states during the precharge phase. During the evaluation phase, a conduction path is obtained based on the pre-stored switching states, formed by a series connection of some second FeFETs, from the operation input terminal of operation module 23 to the logic output terminal `Cout` or the inverted logic output terminal `!Cout`. Evaluation logic operations are performed on the relevant input signals along this conduction path to generate a non-volatile operation result, which is then output to the logic output terminal `Cout` or the inverted logic output terminal `!Cout`. The operation result output by the logic output terminal `Cout` is the carry. The input signals include two local input signals, two inverted local input signals, one carry input signal, and one inverted carry input signal. This full adder circuit retains the operation result after power failure and automatically restores the operation state after power is restored.

[0030] Further defined, the full adder circuit has a high power input terminal, a low power input terminal, a clock control input terminal CLK, and a first signal write terminal A, a second signal write terminal B, a third signal write terminal C, a first inverted signal write terminal A, a second inverted signal write terminal B, and a third inverted signal write terminal C; the high power input terminal is connected to a high power signal, i.e., power supply VDD, and is connected to the first and second precharge input terminals of precharge module 11 and precharge module 21 respectively to provide operating voltage; the low power input terminal is connected to a low power signal, i.e., ground GND, and is connected to the ground input terminals of pull-down module 12 and pull-down module 22 respectively; the clock control input terminal CLK... The K input is connected to a low or high level to control the operating phase of the full adder circuit. When the clock control input CLK is connected to a low level, the full adder circuit is in the pre-charge phase; when the clock control input CLK is connected to a high level, the full adder circuit is in the evaluation phase. The first signal writing terminal A and the second signal writing terminal B each receive a local input signal. The first inverted signal writing terminal A and the second inverted signal writing terminal B each receive an inverted local input signal. The third signal writing terminal C receives the carry input signal, and the third inverted signal writing terminal C receives the inverted carry input signal. The inverted local input signal is obtained by logically inverting the corresponding local input signal, and the inverted carry input signal is obtained by logically inverting the carry input signal.

[0031] Preferably, the precharge module 11 and the precharge module 21 have the same structure, both including 4 PMOS transistors.

[0032] In precharge module 11, the source of the first PMOS transistor P1-1 and the source of the second PMOS transistor P1-2 are connected and connected to the first precharge input terminal. The source of the third PMOS transistor P1-3 and the source of the fourth PMOS transistor P1-4 are connected and connected to the second precharge input terminal. The gate of the first PMOS transistor P1-1 and the gate of the fourth PMOS transistor P1-4 are both connected to the clock control input terminal CLK. The drain of the first PMOS transistor P1-1, the drain of the second PMOS transistor P1-2, and the gate of the third PMOS transistor P1-3 are connected and connected to the first precharge output terminal. The drain of the third PMOS transistor P1-3, the drain of the fourth PMOS transistor P1-4, and the gate of the second PMOS transistor P1-2 are connected and connected to the second precharge output terminal. When the clock control input terminal CLK is low, the first PMOS transistor P1-1 and the fourth PMOS transistor P1-4 are connected to the clock control input terminal CLK. When P1-4 is turned on, the high level of the first precharge input terminal is transmitted to the first precharge output terminal, while the third PMOS transistor P1-3 remains off. The high level of the second precharge input terminal is transmitted to the second precharge output terminal, while the second PMOS transistor P1-2 remains off. That is, during the precharge phase, a conduction path is formed from the first precharge input terminal to the first precharge output terminal, and a conduction path is also formed from the second precharge input terminal to the second precharge output terminal, completing the precharge process. When the clock control input terminal CLK is connected to a high level, the first PMOS transistor P1-1 and the fourth PMOS transistor P1-4 are turned off, and the evaluation phase begins. During the evaluation phase, the third PMOS transistor P1-3 will turn on according to the low level received at the first precharge output terminal, or the second PMOS transistor P1-2 will turn on according to the low level received at the second precharge output terminal, thereby forming a conduction path from the second precharge input terminal to the second precharge output terminal, or from the first precharge input terminal to the first precharge output terminal.

[0033] In precharge module 21, the source of the first PMOS transistor P2-1 and the source of the second PMOS transistor P2-2 are connected and connected to the first precharge input terminal. The source of the third PMOS transistor P2-3 and the source of the fourth PMOS transistor P2-4 are connected and connected to the second precharge input terminal. The gate of the first PMOS transistor P2-1 and the gate of the fourth PMOS transistor P2-4 are both connected to the clock control input terminal CLK. The drain of the first PMOS transistor P2-1, the drain of the second PMOS transistor P2-2, and the gate of the third PMOS transistor P2-3 are connected and connected to the first precharge output terminal. The drain of the third PMOS transistor P2-3, the drain of the fourth PMOS transistor P2-4, and the gate of the second PMOS transistor P2-2 are connected and connected to the second precharge output terminal. When the clock control input terminal CLK is low, the first PMOS transistor P2-1 and the fourth PMOS transistor P2-4 are connected to the clock control input terminal CLK. When P2-4 is turned on, the high level of the first precharge input terminal is transmitted to the first precharge output terminal, while keeping the third PMOS transistor P2-3 off. The high level of the second precharge input terminal is transmitted to the second precharge output terminal, while keeping the second PMOS transistor P2-2 off. That is, during the precharge phase, a conduction path is formed from the first precharge input terminal to the first precharge output terminal, and a conduction path is also formed from the second precharge input terminal to the second precharge output terminal, completing the precharge process. When the clock control input terminal CLK is connected to a high level, the first PMOS transistor P2-1 and the fourth PMOS transistor P2-4 are turned off, and the evaluation phase begins. During the evaluation phase, the third PMOS transistor P2-3 will turn on according to the low level received at the first precharge output terminal, or the second PMOS transistor P2-2 will turn on according to the low level received at the second precharge output terminal, thereby forming a conduction path from the second precharge input terminal to the second precharge output terminal, or from the first precharge input terminal to the first precharge output terminal.

[0034] Preferably, pull-down module 12 and pull-down module 22 have the same structure, each including one NMOS transistor.

[0035] In pull-down module 12, the source of NMOS transistor N1 is connected to the input terminal to ground, the gate of NMOS transistor N1 is connected to the clock control input terminal CLK, and the drain of NMOS transistor N1 is connected to the output terminal to ground. When the clock control input terminal CLK is low, NMOS transistor N1 is turned off; when the clock control input terminal CLK is high, NMOS transistor N1 is turned on, and the output terminal to ground reaches a low level, that is, a conduction path from the input terminal to the output terminal to ground is formed during the evaluation stage.

[0036] In pull-down module 22, the source of NMOS transistor N2 is connected to the input terminal to ground, the gate of NMOS transistor N2 is connected to the clock control input terminal CLK, and the drain of NMOS transistor N2 is connected to the output terminal to ground. When the clock control input terminal CLK is low, NMOS transistor N2 is turned off; when the clock control input terminal CLK is high, NMOS transistor N2 is turned on, and the output terminal to ground reaches a low level, that is, a conduction path from the input terminal to the output terminal to ground is formed during the evaluation stage.

[0037] Preferably, the arithmetic module 13 includes 10 first FeFETs. The drains of the first first FeFET 1-1 and the third first FeFET 1-3 are connected and connected to the inverted logic output terminal S of the arithmetic module 13. The drains of the second first FeFET 1-2 and the fourth first FeFET 1-4 are connected and connected to the logic output terminal S of the arithmetic module 13. The gates of the first first FeFET 1-1 and the fourth first FeFET 1-4 are both connected to the first signal write terminal A. The gates of the second first FeFET 1-2 and the third first FeFET 1-3 are both connected to the first inverted signal write terminal A. The sources of the first first FeFET 1-1 and the second first FeFET 1-2 are connected and connected to the drains of the fifth first FeFET 1-5 and the seventh first FeFET 1-7, respectively. The third first FeFET... The sources of FeFETs 1-3 and 4 are connected to the source of FeFET 1-4, and are respectively connected to the drains of FeFETs 6-6 and 8-8. The gates of FeFETs 5-5 and 8-8 are both connected to the third signal write terminal C. The gates of FeFETs 6-6 and 7-7 are both connected to the third inverse signal write terminal C. The sources of FeFETs 5-5 and 6-6 are respectively connected to the drains of FeFETs 9-9. The sources of FeFETs 7-7 and 8-8 are respectively connected to the drains of FeFETs 1-10. The gates of FeFETs 1-9 are connected to the second signal writing terminal B, the gate of the 10th FeFET1-10 is connected to the second inverse signal writing terminal B, and the sources of the 9th FeFET1-9 and the 10th FeFET1-10 are both connected to the operation input terminal of the operation module 13.

[0038] Preferably, the second operational module 23 includes eight second FeFETs. The drains of the first second FeFET 2-1 and the third second FeFET 2-3 are connected and connected to the inverted logic output terminal Cout of the second operational module 23. The drains of the second second FeFET 2-2 and the sixth second FeFET 2-6 are connected and connected to the logic output terminal Cout of the second operational module 23. The gate of the first second FeFET 2-1 is connected to the third signal write terminal C. The gate of the second second FeFET 2-2 is connected to the third inverted signal write terminal C. The sources of the first second FeFET 2-1 and the second second FeFET 2-2 are connected and connected to the drains of the fourth second FeFET 2-4 and the fifth second FeFET 2-5, respectively. The gates of the third second FeFET 2-3 and the fifth second FeFET 2-5 are both connected to the first signal write terminal A. The fourth second FeFET... The gates of FeFETs 2-4 and 6 are connected to the first inverted signal write terminal A. The sources of FeFETs 3-3 and 4-4 are connected to the drain of FeFET 7-7. The sources of FeFETs 5-5 and 6-6 are connected to the drain of FeFET 8-8. The gate of FeFET 7-7 is connected to the second signal write terminal B. The gate of FeFET 8-8 is connected to the second inverted signal write terminal B. The sources of FeFETs 7-7 and 8-8 are connected to the operation input terminal of operation module 23.

[0039] For arithmetic module 13, since there is only one conduction path, which is either from the arithmetic input terminal of arithmetic module 13 to the logic output terminal S or from the arithmetic input terminal of arithmetic module 13 to the inverted logic output terminal S, when the conduction path is from the arithmetic input terminal of arithmetic module 13 to the logic output terminal S, the result of the operation output terminal S is the sum of its bits (low level), and is transmitted to the second precharge output terminal of precharge module 11. This connection is made with the gate of the second PMOS transistor P1-2 in precharge module 11, turning on the second PMOS transistor P1-2, forming a connection from the first precharge input terminal to the second precharge output terminal. A precharge output path causes the inverted logic output !S to output a high level. When the conduction path is from the operation input of operation module 13 to the inverted logic output !S, the operation result output by the inverted logic output !S is the inverted sum (low level), which is transmitted to the first precharge output of precharge module 11. This connection is made with the gate of the third PMOS transistor P1-3 in precharge module 11, turning on the third PMOS transistor P1-3 and forming a path from the second precharge input to the second precharge output, causing the logic output S to output a high level as the sum. Similarly, for operation module 23... Since there is only one conduction path, which is either from the arithmetic input terminal of arithmetic module 23 to the logic output terminal Cout or from the arithmetic input terminal of arithmetic module 23 to the inverted logic output terminal !Cout, when the conduction path is from the arithmetic input terminal of arithmetic module 23 to the logic output terminal Cout, the arithmetic result output by the logic output terminal Cout is a carry (low level), which is transmitted to the second precharge output terminal of precharge module 21. This connection is made with the gate of the second PMOS transistor P2-2 in precharge module 21, turning on the second PMOS transistor P2-2 and forming a carry from the first precharge input terminal. The path to the first precharge output terminal causes the inverted logic output terminal !Cout to output a high level. When the conduction path is from the operation input terminal of the operation module 23 to the inverted logic output terminal !Cout, the operation result output by the inverted logic output terminal !Cout is the inverted carry (low level), which is transmitted to the first precharge output terminal of the precharge module 21. It is connected to the gate of the third PMOS transistor P2-3 in the precharge module 21, so that the third PMOS transistor P2-3 is turned on, forming a path from the second precharge input terminal to the second precharge output terminal, so that the logic output terminal Cout outputs a high level as a carry.

[0040] Based on the transistor connections in precharge module 11, pull-down module 12, and arithmetic module 13, the output levels of the logic output terminal S and the inverted logic output terminal !S of arithmetic module 13 can be pulled high during the precharge phase. During the evaluation phase, they jointly perform the summation operation in the full addition operation. Furthermore, the result, based on the series-parallel relationship of the transistors and the non-volatile switching state of the FeFET, remains non-volatile. Similarly, based on the transistor connections in precharge module 21, pull-down module 22, and arithmetic module 23, the output levels of the logic output terminal Cout and the inverted logic output terminal !Cout of arithmetic module 23 can be pulled high during the precharge phase. During the evaluation phase, they jointly perform the carry operation in the full addition operation. Again, the result, based on the series-parallel relationship of the transistors and the non-volatile switching state of the FeFET, is non-volatile.

[0041] To further illustrate the feasibility of the fully non-volatile full adder circuit of this invention, Figure 4 The fully non-volatile full adder circuit shown was simulated.

[0042] In the simulation experiment, "0" represents the input reverse bias voltage signal and "1" represents the input forward bias voltage signal. Figure 5 Yes Figure 4 The simulation results of the fully non-volatile full adder circuit shown are as follows: the local input signal received sequentially at the first signal writing terminal A is {0, 0, 0, 0, 1, 1, 1, 1}, and the inverted local input signal received sequentially at the first inverted signal writing terminal A is {1, 1, 1, 1, 0, 0, 0, 0}; the local input signal received sequentially at the second signal writing terminal B is {0, 0, 1, 1, 0, 0, 1, 1}, and the inverted local input signal received sequentially at the second inverted signal writing terminal B is {1, 1, 0, 0, 1, 1, 0, 0}; the carry input signal received sequentially at the third signal writing terminal C is {0, 1, 0, 1, 0, 1, 0, 1}, and the inverted carry input signal received sequentially at the third inverted signal writing terminal C is {1, 0, 1, 0, 1, 0, 1, 0}.

[0043] Figure 5In the first cycle L1, at time T1, the clock control input terminal CLK receives a logic low-level voltage signal. At this time, the gates of the first PMOS transistor P1-1 and the fourth PMOS transistor P1-4 in the precharge module 11 are connected to the logic low-level voltage signal, and the first PMOS transistor P1-1 and the fourth PMOS transistor P1-4 are turned on, forming a conduction path from the first precharge input terminal to the first precharge output terminal and a conduction path from the second precharge input terminal to the second precharge output terminal, so that the first precharge output terminal and the second precharge output terminal output logic high-level voltage signals; the NMOS transistor N1 in the pull-down module 12 is turned off, disconnecting from the low power input terminal. Similarly, in the precharge module 21, the gates of the first PMOS transistor P2-1 and the fourth PMOS transistor P2-4 are connected to a logic low-level voltage signal, and the first PMOS transistor P2-1 and the fourth PMOS transistor P2-4 are turned on, forming a conduction path from the first precharge input terminal to the first precharge output terminal and a conduction path from the second precharge input terminal to the second precharge output terminal, so that the first precharge output terminal and the second precharge output terminal output logic high-level voltage signals; the NMOS transistor N2 in the pull-down module 22 is turned off, disconnecting the connection with the low power input terminal. In the arithmetic module 13, the local input signal {0} received by the first signal writing terminal A is transmitted to the gates of the first first FeFET 1-1 and the fourth first FeFET 1-4 of the arithmetic module 13, causing the first first FeFET 1-1 and the fourth first FeFET 1-4 to turn off; the inverse local input signal {1} ​​received by the first inverse signal writing terminal A is transmitted to the gates of the second first FeFET 1-2 and the third first FeFET 1-3 of the arithmetic module 13, causing the second first FeFET 1-2 and the third first FeFET 1-3 to turn on; the local input signal {0} received by the second signal writing terminal B is transmitted to the gate of the ninth first FeFET 1-9 of the arithmetic module 13, causing the ninth first FeFET 1-9 to turn off; the inverse local input signal {1} ​​received by the second inverse signal writing terminal B is transmitted to the tenth first FeFET of the arithmetic module 13. The gates of 1-10 are turned on, making the 10th first FeFET 1-10 turn on; the carry input signal {0} received by the third signal writing terminal C is transmitted to the gates of the 5th first FeFET 1-5 and the 8th first FeFET 1-8 of the operation module 13, making the 5th first FeFET 1-5 and the 8th first FeFET 1-8 turn off; the inverse carry input signal {1} ​​received by the third inverse signal writing terminal C is transmitted to the gates of the 6th first FeFET 1-6 and the 7th first FeFET 1-7 of the operation module 13, making the 6th first FeFET 1-6 and the 7th first FeFET 1-7 turn on.In the second operation module 23, the local input signal {0} received by the first signal writing terminal A is transmitted to the gates of the third and fifth second FeFETs 2-3 and 2-5 of the second operation module 23, causing the third and fifth second FeFETs 2-3 to turn off; the inverted local input signal {1} ​​received by the first inverted signal writing terminal A is transmitted to the gates of the fourth and sixth second FeFETs 2-4 and 2-6 of the second operation module 23, causing the fourth and sixth second FeFETs 2-4 to turn on; the local input signal {0} received by the second signal writing terminal B is transmitted to the gate of the seventh second FeFET 2-7 of the second operation module 23, causing the seventh second FeFET 2-7 to turn off; the inverted local input signal {1} ​​received by the second inverted signal writing terminal B is transmitted to the eighth second FeFET of the second operation module 23. The gate of 2-8 turns on the 8th second FeFET 2-8; the carry input signal {0} received by the third signal writing terminal C is transmitted to the gate of the first second FeFET 2-1 of the second operation module 23, turning off the first second FeFET 2-1; the inverse carry input signal {1} ​​received by the third inverse signal writing terminal C is transmitted to the gate of the second second FeFET 2-2 of the second operation module 23, turning on the second second FeFET 2-2.

[0044] Figure 5In the first cycle L1, at time T2, the clock control input CLK receives a logic high-level voltage signal. At this time, the gates of the first PMOS transistor P1-1 and the fourth PMOS transistor P1-4 in precharge module 11 are connected to a logic high-level voltage signal, and the first PMOS transistor P1-1 and the fourth PMOS transistor P1-4 are turned off. The NMOS transistor N1 in pull-down module 12 is turned on, forming a connection with the low power input terminal. Similarly, the gates of the first PMOS transistor P2-1 and the fourth PMOS transistor P2-4 in precharge module 21 are connected to a logic high-level voltage signal, and the first PMOS transistor P2-1 and the fourth PMOS transistor P2-4 are turned off. The NMOS transistor N2 in pull-down module 22 is turned on, forming a connection with the low power input terminal. At this time, since the first FeFET 1-1, the fourth FeFET 1-4, the fifth FeFET 1-5, the eighth FeFET 1-8, and the ninth FeFET 1-9 in the arithmetic module 13 are in the off state, a path cannot be formed from the inverted logic output terminal !S of the arithmetic module 13 to the arithmetic input terminal; since the second FeFET 1-2, the third FeFET 1-3, the sixth FeFET 1-6, the seventh FeFET 1-7, and the tenth FeFET 1-10 in the arithmetic module 13 are in the on state, the second FeFET 1-2 and the seventh FeFET 1-9 are in the off state. 1-7. The tenth first FeFET1-10 is connected in series to form a conduction path, creating a path from the logic output terminal S of the arithmetic module 13 to the arithmetic input terminal. Therefore, the logic output terminal S of the arithmetic module 13 outputs a logic low-level voltage signal. Since the logic output terminal S of the arithmetic module 13 is connected to the gate of the second PMOS transistor P1-2 in the precharge module 11, the second PMOS transistor P1-2 is driven to conduct with a logic low-level voltage signal, forming a path from the first precharge input terminal to the first precharge output terminal of the precharge module 11. Therefore, the inverted logic output terminal S of the arithmetic module 13 outputs a logic high-level voltage signal.In operation module 23, since the first second FeFET 2-1, the third second FeFET 2-3, the fifth second FeFET 2-5, and the seventh second FeFET 2-7 are in the off state, a path cannot be formed from the inverted logic output terminal !Cout of operation module 23 to the operation input terminal; since the second second FeFET 2-2, the fourth second FeFET 2-4, the sixth second FeFET 2-6, and the eighth second FeFET 2-8 are in the on state, the sixth second FeFET 2-6 and the eighth second FeFET 2-7 are in the off state. 2-8 are connected in series to form a conduction path, creating a path from the logic output terminal Cout of the second arithmetic module 23 to the arithmetic input terminal. Therefore, the logic output terminal Cout of the second arithmetic module 23 outputs a logic low-level voltage signal. Since the logic output terminal Cout of the second arithmetic module 23 is connected to the gate of the second PMOS transistor P2-2 in the precharge module 21, the second PMOS transistor P2-2 is driven to conduct with a logic low-level voltage signal, forming a path from the first precharge input terminal to the first precharge output terminal of the precharge module 21. Therefore, the inverted logic output terminal Cout of the second arithmetic module 23 outputs a logic high-level voltage signal.

[0045] Figure 5In the fourth cycle L4, at time T1, the clock control input CLK receives a logic low-level voltage signal. At this time, the gates of the first PMOS transistor P1-1 and the fourth PMOS transistor P1-4 in the precharge module 11 are connected to the logic low-level voltage signal, and the first PMOS transistor P1-1 and the fourth PMOS transistor P1-4 are turned on, forming a conduction path from the first precharge input terminal to the first precharge output terminal and a conduction path from the second precharge input terminal to the second precharge output terminal, so that the first precharge output terminal and the second precharge output terminal output logic high-level voltage signals; the NMOS transistor N1 in the pull-down module 12 is turned off, disconnecting from the low power input terminal. Similarly, in the precharge module 21, the gates of the first PMOS transistor P2-1 and the fourth PMOS transistor P2-4 are connected to a logic low-level voltage signal, and the first PMOS transistor P2-1 and the fourth PMOS transistor P2-4 are turned on, forming a conduction path from the first precharge input terminal to the first precharge output terminal and a conduction path from the second precharge input terminal to the second precharge output terminal, so that the first precharge output terminal and the second precharge output terminal output logic high-level voltage signals; the NMOS transistor N2 in the pull-down module 22 is turned off, disconnecting the connection with the low power input terminal. In the arithmetic module 13, the local input signal {0} received by the first signal writing terminal A is transmitted to the gates of the first first FeFET 1-1 and the fourth first FeFET 1-4 of the arithmetic module 13, causing the first first FeFET 1-1 and the fourth first FeFET 1-4 to turn off; the inverse local input signal {1} ​​received by the first inverse signal writing terminal A is transmitted to the gates of the second first FeFET 1-2 and the third first FeFET 1-3 of the arithmetic module 13, causing the second first FeFET 1-2 and the third first FeFET 1-3 to turn on; the local input signal {1} ​​received by the second signal writing terminal B is transmitted to the gate of the ninth first FeFET 1-9 of the arithmetic module 13, causing the ninth first FeFET 1-9 to turn on; the inverse local input signal {0} received by the second inverse signal writing terminal B is transmitted to the tenth first FeFET of the arithmetic module 13. The gates of FeFETs 1-10 are turned off, causing the 10th FeFET 1-10 to turn off; the carry input signal {1} ​​received by the third signal writing terminal C is transmitted to the gates of the 5th FeFET 1-5 and the 8th FeFET 1-8 of the arithmetic module 13, causing the 5th FeFET 1-5 and the 8th FeFET 1-8 to turn on; the inverse carry input signal {0} received by the third inverse signal writing terminal C is transmitted to the gates of the 6th FeFET 1-6 and the 7th FeFET 1-7 of the arithmetic module 13, causing the 6th FeFET 1-6 and the 7th FeFET 1-7 to turn off.In the second operation module 23, the local input signal {0} received by the first signal writing terminal A is transmitted to the gates of the third and fifth second FeFETs 2-3 and 2-5 of the second operation module 23, causing the third and fifth second FeFETs 2-3 to turn off; the inverse local input signal {1} ​​received by the first inverse signal writing terminal A is transmitted to the gates of the fourth and sixth second FeFETs 2-6 of the second operation module 23, causing the fourth and sixth second FeFETs 2-4 to turn on; the local input signal {1} ​​received by the second signal writing terminal B is transmitted to the gate of the seventh second FeFET 2-7 of the second operation module 23, causing the seventh second FeFET 2-7 to turn on; the inverse local input signal {0} received by the second inverse signal writing terminal B is transmitted to the eighth second FeFET of the second operation module 23. The gate of 2-8 turns off the 8th second FeFET 2-8; the carry input signal {1} ​​received by the third signal writing terminal C is transmitted to the gate of the first second FeFET 2-1 of the second operation module 23, turning on the first second FeFET 2-1; the inverse carry input signal {0} received by the third inverse signal writing terminal C is transmitted to the gate of the second second FeFET 2-2 of the second operation module 23, turning off the second second FeFET 2-2.

[0046] Figure 5In the process, at time T2 of the fourth cycle L4, the clock control input CLK receives a logic high-level voltage signal. At this time, the gates of the first PMOS transistor P1-1 and the fourth PMOS transistor P1-4 in precharge module 11 are connected to a logic high-level voltage signal, and the first PMOS transistor P1-1 and the fourth PMOS transistor P1-4 are turned off; the NMOS transistor N1 in pull-down module 12 is turned on, forming a connection with the low power input terminal. Similarly, the gates of the first PMOS transistor P2-1 and the fourth PMOS transistor P2-4 in precharge module 21 are connected to a logic high-level voltage signal, and the first PMOS transistor P2-1 and the fourth PMOS transistor P2-4 are turned off; the NMOS transistor N2 in pull-down module 22 is turned on, forming a connection with the low power input terminal. At this time, because the first FeFET 1-1, the fourth FeFET 1-4, the sixth FeFET 1-6, the seventh FeFET 1-7, and the tenth FeFET 1-10 in the arithmetic module 13 are in the off state, a path cannot be formed from the inverted logic output terminal !S of the arithmetic module 13 to the arithmetic input terminal; because the second FeFET 1-2, the third FeFET 1-3, the fifth FeFET 1-5, the eighth FeFET 1-8, and the ninth FeFET 1-9 in the arithmetic module 13 are in the on state, and the second FeFET 1-2, the fifth FeFET 1-5, and the ninth FeFET 1-10 are in the off state, a path cannot be formed from the inverted logic output terminal !S of the arithmetic module 13 to the arithmetic input terminal. Lines 1-9 are connected in series to form a conduction path, creating a path from the logic output terminal S of the arithmetic module 13 to the arithmetic input terminal. Therefore, the logic output terminal S of the arithmetic module 13 outputs a logic low-level voltage signal. Since the logic output terminal S of the arithmetic module 13 is connected to the gate of the second PMOS transistor P1-2 in the precharge module 11, the logic low-level voltage signal drives the second PMOS transistor P1-2 to conduct, forming a path from the first precharge input terminal to the first precharge output terminal of the precharge module 11. Therefore, the inverted logic output terminal S of the arithmetic module 13 outputs a logic high-level voltage signal.In operation module 23, since the second FeFET 2-2, the third FeFET 2-3, the fifth FeFET 2-5, and the eighth FeFET 2-8 are in the off state, a path cannot be formed from the logic output terminal Cout of operation module 23 to the operation input terminal; since the first FeFET 2-1, the fourth FeFET 2-4, the sixth FeFET 2-6, and the seventh FeFET 2-7 are in the on state, the first FeFET 2-1, the fourth FeFET 2-4, and the seventh FeFET 2-8 are in the off state. 2-7 are connected in series to form a conduction path, creating a path from the inverted logic output terminal !Cout of the second arithmetic module 23 to the arithmetic input terminal. Therefore, the inverted logic output terminal !Cout of the second arithmetic module 23 outputs a logic low-level voltage signal. Since the inverted logic output terminal !Cout of the second arithmetic module 23 is connected to the gate of the third PMOS transistor P2-3 in the precharge module 21, the third PMOS transistor P2-3 is driven to conduct with a logic low-level voltage signal, forming a path from the second precharge input terminal to the second precharge output terminal of the precharge module 21. Therefore, the logic output terminal Cout of the second arithmetic module 23 outputs a logic high-level voltage signal.

Claims

1. A fully non-volatile full adder circuit based on FeFET, characterized in that: It includes a module for calculating the sum of the base digits and a module for calculating the carry digits. The module for calculating the sum of the base digits consists of a pre-filling module 1, a drop-down module 1, and a calculation module 1 working together. The module for calculating the carry digits consists of a pre-filling module 2, a drop-down module 2, and a calculation module 2 working together. The precharge module one and the precharge module two are used to receive high power signals from their respective first precharge input terminal and second precharge input terminal during the precharge phase, thereby charging their respective first precharge output terminal and second precharge output terminal to a high level, so as to prepare for summation operation and carry operation respectively. The first and second pull-down modules are used to receive a low power signal from their respective ground input terminals during the evaluation phase, thereby ensuring that their respective ground output terminals reach a low level. The arithmetic input, inverted logic output, and logic output of the first arithmetic module are connected to the ground output of the first pull-down module and the first and second precharge outputs of the first precharge module. The first arithmetic module includes multiple first FeFETs. These first FeFETs receive and store input signals as non-volatile switching states during the precharge phase. During the evaluation phase, a conduction path is obtained based on the pre-stored switching states, consisting of a portion of the first FeFETs connected in series, leading from the arithmetic input of the first arithmetic module to the logic output or inverted logic output. Evaluation logic operations are performed on the relevant input signals along this conduction path to generate a non-volatile operation result, which is then output to the logic output or inverted logic output. The operation result output by the logic output is the sum of its bits. The arithmetic input, inverted logic output, and logic output of the second arithmetic module are also connected. The output terminal is connected to the ground output terminal of the pull-down module two, the first precharge output terminal and the second precharge output terminal of the precharge module two. The arithmetic module two includes multiple second FeFETs. These second FeFETs receive and store input signals as non-volatile switching states during the precharge phase. During the evaluation phase, a conduction path is obtained based on the pre-stored switching states. This path is formed by connecting some of the second FeFETs in series and extends from the arithmetic input terminal of the arithmetic module two to the logic output terminal or the inverse logic output terminal. Evaluation logic operations are performed on the relevant input signals along this conduction path to generate a non-volatile operation result. The operation result is then output to the logic output terminal or the inverse logic output terminal. The operation result output by the logic output terminal is the carry. The input signals include two local input signals, two inverse local input signals, one carry input signal, and one inverse carry input signal. The full adder circuit retains the calculation result after power failure and automatically resumes the calculation state after power is restored.

2. The fully non-volatile full adder circuit based on FeFET according to claim 1, characterized in that: The full adder circuit has a high power input terminal, a low power input terminal, a clock control input terminal, and a first signal write terminal, a second signal write terminal, a third signal write terminal, a first inverted signal write terminal, a second inverted signal write terminal, and a third inverted signal write terminal. The high power input terminal is connected to a high power signal, i.e., power supply VDD, and is connected to the first and second pre-charge input terminals of both pre-charge module one and pre-charge module two to provide the operating voltage. The low power input terminal is connected to a low power signal, i.e., ground GND, and is connected to the ground input terminals of both pull-down module one and pull-down module two. The clock control input terminal is connected to a low or high level for control. The operation phases of the full adder circuit are as follows: when the clock control input is low, the full adder circuit is in the pre-charge phase; when the clock control input is high, the full adder circuit is in the evaluation phase. The first signal writing terminal and the second signal writing terminal each receive one local input signal; the first inverted signal writing terminal and the second inverted signal writing terminal each receive one inverted local input signal; the third signal writing terminal receives the carry input signal; and the third inverted signal writing terminal receives the inverted carry input signal. The inverted local input signal is obtained by logically inverting the corresponding local input signal, and the inverted carry input signal is obtained by logically inverting the carry input signal.

3. The fully non-volatile full adder circuit based on FeFET according to claim 2, characterized in that: The first arithmetic module includes 10 first FeFETs. The drains of the first and third first FeFETs are connected and connected to the inverted logic output terminal of the first arithmetic module. The drains of the second and fourth first FeFETs are connected and connected to the logic output terminal of the first arithmetic module. The gates of the first and fourth first FeFETs are both connected to the first signal write terminal. The gates of the second and third first FeFETs are both connected to the first inverted signal write terminal. The sources of the first and second first FeFETs are connected and connected to the drains of the fifth and seventh first FeFETs, respectively. The sources of the third and fourth first FeFETs are connected and connected to the drains of the sixth first FeFET, respectively. The drain of the FeFET is connected to the drain of the 8th first FeFET. The gates of the 5th and 8th first FeFETs are both connected to the third signal write terminal. The gates of the 6th and 7th first FeFETs are both connected to the third inverse signal write terminal. The sources of the 5th and 6th first FeFETs are respectively connected to the drain of the 9th first FeFET. The sources of the 7th and 8th first FeFETs are respectively connected to the drain of the 10th first FeFET. The gate of the 9th first FeFET is connected to the second signal write terminal. The gate of the 10th first FeFET is connected to the second inverse signal write terminal. The sources of the 9th and 10th first FeFETs are both connected to the operation input terminal of the operation module one.

4. The fully non-volatile full adder circuit based on FeFET according to claim 3, characterized in that: The second arithmetic module includes eight second FeFETs. The drains of the first and third second FeFETs are connected and connected to the inverted logic output of the second arithmetic module. The drains of the second and sixth second FeFETs are connected and connected to the logic output of the second arithmetic module. The gate of the first second FeFET is connected to the third signal writing terminal. The gate of the second second FeFET is connected to the third inverted signal writing terminal. The sources of the first and second second FeFETs are connected and connected to the drains of the fourth and fifth second FeFETs, respectively. The gate of the third second FeFET is connected to the drain of the fifth second FeFET. The gates of all eFETs are connected to the first signal write terminal. The gates of the fourth and sixth second FeFETs are both connected to the first inverted signal write terminal. The sources of the third and fourth second FeFETs are respectively connected to the drain of the seventh second FeFET. The sources of the fifth and sixth second FeFETs are respectively connected to the drain of the eighth second FeFET. The gate of the seventh second FeFET is connected to the second signal write terminal. The gate of the eighth second FeFET is connected to the second inverted signal write terminal. The sources of the seventh and eighth second FeFETs are both connected to the operation input terminal of the second operation module.

5. A fully non-volatile full adder circuit based on FeFET according to any one of claims 2 to 4, characterized in that: The precharge module one and the precharge module two have the same structure, each including four PMOS transistors. The source of the first PMOS transistor and the source of the second PMOS transistor are connected and connected to the first precharge input terminal. The source of the third PMOS transistor and the source of the fourth PMOS transistor are connected and connected to the second precharge input terminal. The gate of the first PMOS transistor and the gate of the fourth PMOS transistor are both connected to the clock control input terminal. The drain of the first PMOS transistor, the drain of the second PMOS transistor, and the gate of the third PMOS transistor are connected and connected to the first precharge output terminal. The drain of the third PMOS transistor, the drain of the fourth PMOS transistor, and the gate of the second PMOS transistor are connected to the first PMOS output terminal. The gate of the transistor is connected to and connected to the second precharge output terminal; when the clock control input terminal is low, the first PMOS transistor and the fourth PMOS transistor are turned on, the high level of the first precharge input terminal is transmitted to the first precharge output terminal, while the third PMOS transistor is kept off, the high level of the second precharge input terminal is transmitted to the second precharge output terminal, while the second PMOS transistor is kept off, completing the precharge process; when the clock control input terminal is high, the first PMOS transistor and the fourth PMOS transistor are turned off, entering the evaluation stage; in the evaluation stage, the third PMOS transistor will be turned on according to the low level received by the first precharge output terminal, or the second PMOS transistor will be turned on according to the low level received by the second precharge output terminal.

6. A fully non-volatile full adder circuit based on FeFET according to claim 5, characterized in that: The pull-down module one and the pull-down module two have the same structure, each including one NMOS transistor. The source of the NMOS transistor is connected to the ground input terminal, the gate of the NMOS transistor is connected to the clock control input terminal, and the drain of the NMOS transistor is connected to the ground output terminal. When the clock control input terminal is low, the NMOS transistor is turned off; when the clock control input terminal is high, the NMOS transistor is turned on, and the ground output terminal reaches a low level.

Images