Multifunctional debugging device
By designing a multifunctional debugging device, non-destructive testing of CSSD is achieved using connectors and power protection circuits, solving the problems of faults and damage introduced by traditional destructive operations, reducing costs and improving testing efficiency and accuracy.
Patent Information
- Application Number
- CN202423139536.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-18
- Publication Date
- 2025-12-09
- Estimated Expiration
- 2034-12-18
AI Technical Summary
Traditional CSSD testing involves complex destructive operations that can easily introduce new points of failure and cause physical damage, increasing maintenance costs.
Design a multifunctional debugging device that transfers the signal of the device under test to the host and external testing equipment through a connector to achieve non-destructive testing. It includes a power protection circuit and a display circuit to ensure power stability and signal transmission, and reserves test points for non-destructive testing.
It enables non-destructive operation in the CSSD testing process, reduces sample consumption and labor costs, improves the comprehensiveness and accuracy of testing, and reduces operating costs.
Smart Images
Figure CN223650995U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of hard disk testing technology, and in particular to a multifunctional debugging device. Background Technology
[0002] In the traditional testing, analysis, and debugging of CSSD (Customized Solid State Drive), engineers typically need to perform the following destructive operations: extending the board's serial port wires to view board logs, cutting and resoldering wires to test power consumption, and resoldering wires on board components to test signals. These destructive operations are not only complex and prone to introducing new fault points, but they also cause physical damage, resulting in irreversible effects on the sample and increasing maintenance costs. Utility Model Content
[0003] The purpose of this invention is to provide a multifunctional debugging device that addresses the technical problem that existing destructive operations are not only complex and prone to introducing new fault points, but also cause physical damage, resulting in irreversible effects on samples and increasing maintenance costs.
[0004] To solve the above-mentioned technical problems, the objective of this utility model is achieved through the following technical solution:
[0005] A specific embodiment of this application provides a multifunctional debugging device, including a test board. The test board is provided with a first connector and a test board interface. The first connector is provided with a connector slot, which is inserted into the device under test. The test board interface is located on one side of the first connector. One end of the test board interface is connected to the first connector, and the other end is connected to the host. A second connector is also provided between the first connector and the test board interface. One end of the second connector is connected to the first connector, and the other end is connected to an external testing device.
[0006] In one possible implementation, the first connector includes a plurality of pins, and the first connector converts the signal of the device under test (DUT) through the plurality of pins. The signal of the DUT includes a high-speed signal and a low-speed signal. The test board interface transmits the high-speed signal to the host, and the second connector transmits the low-speed signal to the external test equipment.
[0007] In one possible implementation, the second connector is a header that connects to the pin wires so that the external test equipment can perform debugging on the header.
[0008] In one possible implementation, the test board further includes a power protection circuit located between the first connector and the test board interface, and electrically connected to both the first connector and the test board interface.
[0009] In one possible implementation, the power protection circuit includes: a TVS diode D7, a first resistor R52, a first capacitor C8, a second capacitor C10, and a third capacitor C11.
[0010] The positive terminal of the TVS diode D7 is connected to the input power supply;
[0011] The negative terminal of the TVS diode D7 is grounded;
[0012] One end of the first resistor R52 is connected to the input power supply, and the other end is connected to one end of the first capacitor C8;
[0013] One end of the first capacitor C8 is connected to the second capacitor C10 and the output power supply respectively;
[0014] One end of the second capacitor C10 is connected to the third capacitor C11 and the output power supply, respectively;
[0015] The other ends of the first capacitor C8, the second capacitor C10, and the third capacitor are all grounded.
[0016] In one possible implementation, a display circuit is further provided between the power protection circuit and the first connector, and the display circuit is connected in parallel with the power protection circuit.
[0017] In one possible implementation, the display circuit includes a second resistor R62 and a light-emitting diode D5;
[0018] One end of the second resistor R62 is connected to the input power supply, and the other end is connected to the positive terminal of the light-emitting diode D5;
[0019] The negative terminal of the light-emitting diode D5 is grounded.
[0020] In one possible implementation, the resistance of the first resistor R52 is 10 mol / L.
[0021] In one possible implementation, the system also includes a data acquisition device and a host computer, wherein the data acquisition device is electrically connected to the host computer and the first resistor R52, respectively.
[0022] In one possible implementation, the first connector is further provided with a reserved test point, which is formed by the pin and a zero-ohm resistor connected in series.
[0023] The advantages of this invention compared to existing technologies are as follows: This invention provides a multifunctional debugging device that utilizes a test board with connectors to transfer the CSSD (Object under Test) to the host computer and external measuring equipment. Measurement can be performed without destructive operations on the CSSD itself during testing. Compared to existing technologies, this invention, through the combination of multiple testing structures, enables engineers to achieve non-destructive results during CSSD analysis and debugging, preserving the sample and reducing sample consumption. This not only saves manpower and material costs but also reduces interference caused by destructive operations. Attached Figure Description
[0024] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0025] Figure 1 A schematic diagram of the structure of the multifunctional debugging device provided in the embodiment of this utility model;
[0026] Figure 2 A circuit diagram of the first connector of the multifunctional debugging device provided in this embodiment of the utility model;
[0027] Figure 3 A circuit diagram of the test board interface of the multifunctional debugging device provided in this embodiment of the utility model;
[0028] Figure 4 Pin diagram of the second connector of the multifunctional debugging device provided in this embodiment of the utility model;
[0029] Figure 5 A schematic diagram of the power protection circuit of the multifunctional debugging device provided in this embodiment of the utility model;
[0030] Figure 6 A schematic diagram of the display circuit of the multifunctional debugging device provided in this embodiment of the utility model.
[0031] Figure label:
[0032] 10. Test board; 20. First connector; 30. Test board interface; 40. Second connector; 50. Power protection circuit; 60. Display circuit. Detailed Implementation
[0033] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.
[0034] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.
[0035] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.
[0036] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0037] Please see Figures 1 to 6 , please refer to Figure 1 This utility model embodiment provides a multifunctional debugging device, including a test board 10. The test board 10 is provided with a first connector 20 and a test board interface 30. The first connector 20 is provided with a connector slot, which is inserted into the object under test. The test board interface 30 is located on one side of the first connector 20. One end of the test board interface 30 is connected to the first connector 20, and the other end is connected to the host. A second connector 40 is also provided between the first connector 20 and the test board interface 30. One end of the second connector 40 is connected to the first connector 20, and the other end is connected to an external testing device.
[0038] Specifically, in this embodiment, the device under test is an M.2 interface CSSD, the first connector 20 is an M KEY SOCKET, and the test board interface 30 is an M.2 gold finger. This is only used to illustrate a special application scenario and is not intended to limit the scope of the application.
[0039] Specifically, the test board 10 serves as the foundation of the entire debugging device, supporting and connecting various components. The first connector 20, mounted on the test board 10, has a connector slot for insertion into the device under test (DUT). The DUT connects to the connector slot of the first connector 20 via insertion, achieving a physical connection. The test board interface 30 is located on one side of the first connector 20, with one end connected to the first connector 20 and the other end connected to the host computer, enabling data transmission and communication between the test board 10 and the host computer. The second connector 40 is positioned between the first connector 20 and the test board interface 30, with one end connected to the first connector 20 and the other end connected to external testing equipment, used to introduce signals or data from external testing equipment. When the DUT is inserted into the first connector 20, i.e., when the M.2 interface CSSD is inserted into the M KEY SOCKET, a physical connection is established. Through the connection between the test board interface 30 (M.2 gold fingers) and the host computer, the host computer can send test commands or data to the CSSD and receive its response. Simultaneously, external testing equipment, connected to the CSSD via the second connector 40, can send additional test signals or data for more comprehensive testing. This non-destructive testing method effectively avoids new fault points introduced by scraping green oil and bonding wires in traditional methods, ensuring the authenticity and reliability of test results. Secondly, it reduces labor costs and sample consumption, especially in batch testing environments, which can significantly reduce operating costs. It also supports a variety of testing needs and adapts to the application requirements of different scenarios.
[0040] like Figure 1-3 As shown, the first connector 20 includes several pins. The first connector 20 converts the signal of the device under test through several pins. The signal of the device under test includes high-speed signal and low-speed signal. The test board interface 30 transmits the high-speed signal to the host, and the second connector 40 transmits the low-speed signal to the external test equipment.
[0041] Specifically, high-speed signals typically refer to signals with high data transfer rates, such as high-speed data signals from interfaces like PCIe and SATA. Low-speed signals, on the other hand, typically refer to control signals, status signals, etc., with lower data transfer rates.
[0042] Furthermore, when the device under test (DUT) is inserted into the first connector 20, its pins mate with the corresponding interfaces of the DUT, forming an electrical connection. High-speed signals are transmitted to the host computer via the test board interface 30 (e.g., M.2 gold fingers) for high-speed data transmission and performance testing. Low-speed signals are transmitted to external test equipment via the second connector 40 for more detailed testing and analysis. Direct transmission of high-speed signals to the host computer allows for rapid data processing and analysis, improving testing efficiency. Transmission of low-speed signals to external test equipment via the second connector 40 allows for more detailed analysis and testing, further enhancing the comprehensiveness and accuracy of the test. Moreover, the design of the first connector 20 is compatible with the interface standards of different DUTs on the board, ensuring compatibility with DUTs of different brands and models.
[0043] like Figure 1 and Figure 4 As shown, the second connector 40 is a pin header, which is connected to the pin wire to enable external test equipment to perform debugging on the pin header.
[0044] Specifically, since most CSSD UART reserved ports are covered by solder mask, testing or debugging the disk requires scraping off the solder mask to remove the solder joints. However, scraping off the solder mask and solder joints can easily introduce new location faults into the disk, and once the solder mask or solder joints are scraped off, the disk cannot be shipped and used, resulting in a waste of labor and product costs. In this embodiment, by connecting pins 56 and 58 on the MKEY SOCKET to the J29 header, the serial cable can be directly connected to the header for serial port debugging, thus achieving serial port use without scraping the pins. Secondly, the MKEY SOCKET also reserves some commonly used signals, such as SMBus, clkreq, refclk, and Perst. By connecting these to the J28 header, it is possible to directly test the signals on the header when debugging is required.
[0045] like Figure 1 and Figure 5 As shown, the test board 10 also includes a power protection circuit 50, which is located between the first connector 20 and the test board interface 30, and is electrically connected to the first connector 20 and the test board interface 30 respectively.
[0046] Specifically, the power protection circuit 50 is located between the first connector 20 and the test board interface 30. This is to ensure that the power signal transmitted from the host to the device under test (such as an M.2 interface CSSD) can be monitored and processed by the protection circuit, thereby effectively preventing equipment damage or data loss due to abnormal power supply.
[0047] like Figure 5As shown, the power protection circuit 50 includes: a TVS diode D7, a first resistor R52, a first capacitor C8, a second capacitor C10, and a third capacitor C11; the positive terminal of the TVS diode D7 is connected to the input power supply; the negative terminal of the TVS diode D7 is grounded; one end of the first resistor R52 is connected to the input power supply, and the other end is connected to one end of the first capacitor C8; one end of the first capacitor C8 is connected to the second capacitor C10 and the output power supply respectively; one end of the second capacitor C10 is connected to the third capacitor C11 and the output power supply respectively; the other ends of the first capacitor C8, the second capacitor C10, and the third capacitor C11 are all grounded.
[0048] Specifically, the TVS (Transient Voltage Suppressor) transistor D7, also known as a transient voltage suppressor, is a device used to protect circuits from transient overvoltage surges. In this circuit, the positive terminal of the TVS transistor D7 is connected to the input power supply, and the negative terminal is grounded, used to absorb and suppress transient overvoltages in the input power supply. The first resistor R52 is connected to the input power supply, acting as a current limiter to protect subsequent circuits from excessive current surges. Capacitors are commonly used in circuits for filtering and energy storage. These three capacitors are connected in parallel in the circuit, connected to both the input and output power supplies, acting as a filter to smooth the power supply voltage, reduce voltage fluctuations, and improve power supply stability.
[0049] The working principle of this circuit is as follows: When a transient overvoltage exists in the input power supply, the TVS diode D7 will quickly conduct, diverting the overvoltage to ground, thereby protecting the subsequent circuits from damage. The first resistor R52 acts as a current limiter, restricting the current flowing through the TVS diode D7 and the subsequent circuits to prevent excessive current from damaging the components. The three parallel capacitors (C8, C10, and C11) work together to filter the power supply voltage, smoothing it, reducing voltage fluctuations, and improving power supply stability.
[0050] like Figure 1 and Figure 6 As shown, a display circuit 60 is also provided between the power protection circuit 50 and the first connector 20, and the display circuit 60 is connected in parallel with the power protection circuit 50.
[0051] like Figure 6 As shown, the display circuit 60 includes a second resistor R62 and a light-emitting diode D5; one end of the second resistor R62 is connected to the input power supply, and the other end is connected to the positive terminal of the light-emitting diode D5; the negative terminal of the light-emitting diode D5 is grounded.
[0052] Specifically, the display circuit 60 in this embodiment is used to detect whether the disk is powered on and operating normally. When the input power is on and the power protection circuit 50 is working properly, the current flows into the light-emitting diode D5 after being limited by the second resistor R62, causing it to light up. The light-emitting state of the light-emitting diode D5 (such as brightness, color, etc.) can intuitively display whether the power is on and the working status of the power protection circuit 50. If the power protection circuit 50 detects an abnormality (such as overvoltage, overcurrent, etc.), it may cut off or limit the transmission of the power signal. At this time, the light-emitting diode D5 may turn off or change its light-emitting state (such as reduced brightness, color change, etc.) to remind the user of power problems. The introduction of the display circuit 60 allows users to more conveniently monitor and manage the working status of the test device, enhancing the user experience.
[0053] like Figure 5 As shown, the resistance of the first resistor R52 is 10 mol / L.
[0054] Specifically, the resistance of the first resistor R52 is precisely set to 10 mohm (milliohm), which is a very small resistance value for applications requiring high-precision current measurement.
[0055] In one available embodiment, the multi-functional debugging device further includes a data acquisition unit and a host computer, with the data acquisition unit electrically connected to the host computer and the first resistor R52, respectively.
[0056] Specifically, when current flows through a 10mohm resistor in the 3V3 main power supply link, according to Ohm's law (V=IR), a tiny voltage drop will occur across the resistor. This voltage drop is proportional to the current flowing through the resistor. A high-precision data acquisition instrument can accurately measure this tiny voltage drop and convert it into a current value. Since the resistance value (10mohm) is known, the current value can be accurately calculated by measuring the voltage drop. Based on the current data transmitted by the high-precision data acquisition instrument, combined with the system's operating status and time, the host computer software can calculate the system's power consumption and generate a corresponding report. This method can solve the difficulty of batch power consumption verification in system testing.
[0057] like Figure 2 As shown, the first connector 20 is also provided with a reserved test point, which is formed by connecting a pin in series with a zero-ohm resistor.
[0058] Specifically, the pin, as the core component of the connector, is responsible for signal transmission and power supply. In this embodiment, the pin not only performs these basic functions but is also used as part of a reserved test point. A zero-ohm resistor, also known as a jumper resistor or 0Ω resistor, is actually a special type of resistor with a resistance value close to zero. Here, the zero-ohm resistor is connected in series with the pin, forming a reserved test point together with the pin. The reserved test point is formed by the series connection of the pin and the zero-ohm resistor. In actual circuits, this connection method allows testers to indirectly monitor the signal or power status on the pin by measuring the voltage or current across the zero-ohm resistor without interfering with the normal operation of the circuit.
[0059] Furthermore, when the circuit is operating normally, the zero-ohm resistor at the reserved test point produces almost no voltage drop, thus having no significant impact on the circuit's performance. When testing is required, testers can use testing instruments (such as multimeters, oscilloscopes, etc.) connected to the reserved test point to evaluate parameters such as signal quality and power supply stability on the pins by measuring the voltage or current across the zero-ohm resistor. This reserved test point allows testers to easily test the pins on the connector without requiring additional modifications or damage to the circuit, greatly improving the convenience and efficiency of testing; moreover, the reserved test point does not interfere with the normal operation of the circuit, thereby protecting the circuit's safety and stability.
[0060] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A multifunctional debugging device, characterized in that, The device includes a test board, on which a first connector and a test board interface are provided. The first connector has a connector slot, which is inserted into the device under test. The test board interface is located on one side of the first connector. One end of the test board interface is connected to the first connector, and the other end is connected to the host. A second connector is also provided between the first connector and the test board interface. One end of the second connector is connected to the first connector, and the other end is connected to an external test device.
2. The multifunctional debugging device according to claim 1, characterized in that, The first connector includes a plurality of pins, and the first connector converts the signal of the device under test through the plurality of pins. The signal of the device under test includes a high-speed signal and a low-speed signal. The test board interface transmits the high-speed signal to the host, and the second connector transmits the low-speed signal to the external test equipment.
3. The multifunctional debugging device according to claim 2, characterized in that, The second connector is a pin header, which is connected to the pin wire so that the external testing equipment can be debugged on the pin header.
4. The multifunctional debugging device according to claim 1, characterized in that, The test board also includes a power protection circuit, which is located between the first connector and the test board interface and is electrically connected to both the first connector and the test board interface.
5. The multifunctional debugging device according to claim 4, characterized in that, The power protection circuit includes: TVS diode D7, first resistor R52, first capacitor C8, second capacitor C10 and third capacitor C11; The positive terminal of the TVS diode D7 is connected to the input power supply; The negative terminal of the TVS diode D7 is grounded; One end of the first resistor R52 is connected to the input power supply, and the other end is connected to one end of the first capacitor C8; One end of the first capacitor C8 is connected to the second capacitor C10 and the output power supply respectively; One end of the second capacitor C10 is connected to the third capacitor C11 and the output power supply, respectively; The other ends of the first capacitor, the second capacitor, and the third capacitor are all grounded.
6. The multifunctional debugging device according to claim 5, characterized in that, A display circuit is also provided between the power protection circuit and the first connector, and the display circuit is connected in parallel with the power protection circuit.
7. The multifunctional debugging device according to claim 6, characterized in that, The display circuit includes a second resistor R62 and a light-emitting diode D5; One end of the second resistor R62 is connected to the input power supply, and the other end is connected to the positive terminal of the light-emitting diode D5; The negative terminal of the light-emitting diode D5 is grounded.
8. The multifunctional debugging device according to claim 5, characterized in that, The resistance of the first resistor R52 is 10 mol / L.
9. The multifunctional debugging device according to claim 8, characterized in that, It also includes a data acquisition device and a host computer, wherein the data acquisition device is electrically connected to the host computer and the first resistor R52 respectively.
10. The multifunctional debugging device according to claim 2, characterized in that, The first connector is also provided with a reserved test point, which is formed by connecting the pin in series with a zero-ohm resistor.