Signal multi-channel fan-out circuit and test platform

Abstract

The utility model relates to a signal multi-channel fan-out circuit and a test platform, and the circuit comprises a multiplexer board card which comprises a plurality of positions; at least one of the plurality of positions is provided with a relay, and an input signal and an output signal of the relay are in signal lap joint on the multiplexer board card to form different types of signal fan-out circuits; or at least one of the plurality of positions is provided with a relay, and an input signal and an output signal of the relay are led out to the exterior of the multiplexer board card for signal lap joint at the exterior to form different types of signal fan-out circuits. Based on the scheme provided by the invention, fan-out combination of different types of signals can be realized, and the requirements of chip multi-point testing and low cost are met.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit testing, in particular to a signal multi-path fan-out circuit and a test platform. BACKGROUND

[0002] In the field of integrated circuit testing, with the complication of chip functions, the number of chip pins is also increasing, resulting in more and more resources required for chip testing. According to the testing requirements of the chip, the number of relays required on the hardware test board (a hardware test board for chip testing) is also increasing.

[0003] However, the area of the current hardware test board is limited and cannot accommodate the numerous relays required for chip testing, so it cannot meet the testing requirements of multi-point testing, thereby affecting the testing efficiency. In addition, with the increase in the number of relays in the hardware test board, the complexity of the design of the hardware test board is increased, and the design cost and design period of the hardware test board are also increased. Furthermore, due to the large number of relays in the hardware test board, if a relay malfunctions, it takes a long time to locate and repair, thereby affecting the testing efficiency of the customer. CONTENT OF THE INVENTION

[0004] In view of the above problems of the prior art, the present application provides a signal multi-path fan-out circuit and a test platform, which can realize fan-out of different types of signals and meet the requirements of multi-point testing in chip testing. In addition, the signal multi-path fan-out circuit and test platform provided by the present application also support online self-checking, which facilitates the positioning of faulty relays and facilitates maintenance.

[0005] To achieve the above-mentioned purpose, the first aspect of the present application provides a signal multi-path fan-out circuit, comprising: a multiplexer board card, the multiplexer board card comprising a plurality of positions; at least one position of the plurality of positions is arranged with a relay, and the input signal and the output signal of the relay are signal-spliced on the multiplexer board card to form different types of signal fan-out circuits; or at least one position of the plurality of positions is arranged with a relay, and the input signal and the output signal of the relay are led out to the outside of the multiplexer board card for signal-splicing outside to form different types of signal fan-out circuits.

[0006] From the above, by splicing the input signal and the output signal of the relay on the multiplexer board card, a plurality of different types of signal fan-out circuits can be formed, meeting the requirements of multi-point testing in chip testing. In addition, the input signal and the output signal of the relay can also be led out for signal-splicing outside, thereby forming a plurality of different types of signal fan-out circuits, meeting the requirements of multi-point testing and low cost in chip testing.

[0007] As an implementation manner of the aspect, the relay at least includes two input terminals constituting a Kelvin connection, a first input terminal for connecting a driving signal, and a second input terminal for connecting a sensing signal; the relay at least includes four output terminals, a first output terminal for outputting a first driving signal, and a third output terminal for outputting a first sensing signal; a second output terminal for outputting a second driving signal, and a fourth output terminal for outputting a second sensing signal; wherein the first driving signal and the first sensing signal constitute a first signal group; and the second driving signal and the second sensing signal constitute a second signal group.

[0008] As an implementation manner of the aspect, the plurality of positions at least include a first position, a second position, and a third position; the first position is arranged with a first relay, a first input terminal of the first relay is connected with a corresponding driving signal thereof, and a second input terminal of the first relay is connected with a corresponding sensing signal thereof; four output terminals of the first relay are respectively connected with switching devices for controlling the on-off of each output terminal; the second position is arranged with a second relay, a first input terminal of the second relay is connected with a first output terminal of the first relay through a switching device, and the first input terminal of the second relay is further connected with a corresponding driving signal thereof through a switching device; a second input terminal of the second relay is connected with a third output terminal of the first relay through a switching device, and the second input terminal of the second relay is further connected with a corresponding sensing signal thereof through a switching device; a first output terminal and a third output terminal of the second relay are connected through a switching device, and a second output terminal and a fourth output terminal of the second relay are connected through a switching device; the third position is arranged with a third relay, a first input terminal of the third relay is connected with a second output terminal of the first relay through a switching device, and the first input terminal of the third relay is further connected with a corresponding driving signal thereof through a switching device; a second input terminal of the third relay is connected with a fourth output terminal of the first relay through a switching device, and the second input terminal of the third relay is further connected with a corresponding sensing signal thereof through a switching device; a first output terminal and a third output terminal of the third relay are connected through a switching device, and a second output terminal and a fourth output terminal of the third relay are connected through a switching device.

[0009] As an implementation form of the aspect, a first sub-branch exists between the first input end of the first relay and the driving signal corresponding to the first input end, the first sub-branch comprising a first switch device and a first resistor connected in series, one end of the first resistor away from the first switch device being connected to a positive electrode; a second sub-branch exists between the second input end of the first relay and the sensing signal corresponding to the second input end, the second sub-branch comprising a second switch device and a second resistor connected in series, one end of the second resistor away from the second switch device being connected to a ground; in the second sub-branch, an analog-to-digital converter is further connected between the second switch device and the second resistor.

[0010] As described above, the self-checking of the relay fault can be realized by the circuit, and the fault positioning is facilitated.

[0011] As an implementation form of the aspect, the first relay, the second relay and the third relay constitute a first sub-circuit; at least one first sub-circuit is arranged on the multiplexer board card.

[0012] As described above, by arranging multiple groups of first sub-circuits on the multiplexer board card, multiple signal fan-out circuits can be formed.

[0013] As an implementation form of the aspect, the multiple positions further comprise a fourth position; a fourth relay is arranged at the fourth position, a first input end of the fourth relay being connected with a driving signal corresponding to the first input end, a second input end of the fourth relay being connected with a sensing signal corresponding to the second input end; four output ends of the fourth relay are respectively connected with switch devices for controlling the on-off of the respective output ends; a first output end of the fourth relay is connected with a first input end of the third relay through a switch device, a third output end of the fourth relay is connected with a second input end of the third relay through a switch device; a second output end of the fourth relay is connected with a first input end of the second relay through a switch device, a fourth output end of the fourth relay is connected with a second input end of the second relay through a switch device.

[0014] As an implementation form of the aspect, a third sub-branch exists between the first input end of the fourth relay and the driving signal corresponding to the first input end, the third sub-branch comprising a third switch device and a third resistor connected in series, one end of the third resistor away from the third switch device being connected to a positive electrode; a fourth sub-branch exists between the second input end of the fourth relay and the sensing signal corresponding to the second input end, the fourth sub-branch comprising a fourth switch device and a fourth resistor connected in series, one end of the fourth resistor away from the fourth switch device being connected to a ground; in the fourth sub-branch, an analog-to-digital converter is further connected between the fourth switch device and the fourth resistor.

[0015] As an implementation form of the aspect, the first relay, the second relay, the third relay and the fourth relay form a second sub-circuit; and at least one second sub-circuit is arranged on the multiplexer board card.

[0016] According to the above, by arranging multiple groups of second sub-circuits on the multiplexer board card, multiple signal fan-out circuits can be formed.

[0017] As an implementation form of the aspect, the multiple positions at least include a fifth position and a sixth position; a fifth relay is arranged at the fifth position, two input ends and four output ends of the fifth relay are led out to outside of the multiplexer board card; a sixth relay is arranged at the sixth position, two input ends and four output ends of the sixth relay are led out to outside of the multiplexer board card; a first input end of the fifth relay is connected with a corresponding driving signal, a second input end of the fifth relay is connected with a corresponding sensing signal; a first output end of the fifth relay is connected with a first input end of the sixth relay, and a third output end of the fifth relay is connected with a second input end of the sixth relay.

[0018] As an implementation form of the aspect, the multiple positions further include a seventh position; a seventh relay is arranged at the seventh position, two input ends and four output ends of the seventh relay are led out to outside of the multiplexer board card; a first input end of the seventh relay is connected with a first output end of the sixth relay, and a second input end of the seventh relay is connected with a third output end of the sixth relay.

[0019] The second aspect of the application provides a test platform, comprising: multiple circuits according to any one of the first aspect.

[0020] The multiple circuits are arranged in the form of stacked boards through a multiplexer board card.

[0021] The beneficial effects of the aspect can also be referred to the description of the beneficial effects of each part of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0022] The various technical features of the application and the relationship between them will be further described below with reference to the accompanying drawings. The drawings are exemplary, some technical features are not shown in actual proportion, and some technical features in the drawings can be omitted, which are conventional in the technical field to which the application belongs and are not essential for understanding and implementing the application, or additional technical features are shown, which are not essential for understanding and implementing the application, that is, the combination of various technical features shown in the drawings is not used to limit the application. In addition, in the entire application, the same reference signs refer to the same contents. The specific drawings are as follows:

[0023] Figure 1 A structure diagram of a first electronic path in a signal multi-path fan-out circuit provided by an embodiment of the present application;

[0024] Figure 2 A structure diagram of a signal multi-path fan-out circuit provided by an embodiment of the present application;

[0025] Figure 3 A structure diagram of a second electronic path in a signal multi-path fan-out circuit provided by an embodiment of the present application;

[0026] Figure 4 A 1 / 2 signal fan-out circuit schematic diagram formed by a signal external lead provided by an embodiment of the present application;

[0027] Figure 5 A 1 / 3 signal fan-out circuit schematic diagram formed by a signal external lead provided by an embodiment of the present application;

[0028] Figure 6 A 1 / 4 signal fan-out circuit schematic diagram formed by a signal external lead provided by an embodiment of the present application;

[0029] Figure 7 An application schematic diagram of a 1 / 3 signal fan-out circuit formed by a signal external lead provided by an embodiment of the present application;

[0030] Figure 8 A structure diagram of a diagnosis board for offline diagnosis provided by an embodiment of the present application;

[0031] Figure 9 A schematic diagram of a test platform provided by an embodiment of the present application;

[0032] Figure 10a A first arrangement position schematic diagram for a MUX provided by an embodiment of the present application;

[0033] Figure 10b A second arrangement position schematic diagram for a MUX provided by an embodiment of the present application;

[0034] Figure 10c A third arrangement position schematic diagram for a MUX provided by an embodiment of the present application;

[0035] Figure 10d A fourth arrangement position schematic diagram for a MUX provided by an embodiment of the present application. DETAILED DESCRIPTION

[0036] The technical solutions provided by the present application are further described below in combination with the drawings and examples. It should be understood that the system structure and service scenarios provided in the examples of the present application are mainly to illustrate possible implementation manners of the technical solutions of the present application, and should not be interpreted as the only limitation of the technical solutions of the present application. Those skilled in the art can know that the technical solutions provided by the present application are also applicable to similar technical problems as the system structure evolves and new service scenarios appear.

[0037] It should be understood that the examples of the present application provide a signal multi-fanout circuit and a test platform. Since the principles of solving problems of these technical solutions are the same or similar, in the introduction of the following specific examples, some repetitions may not be described again, but should be regarded as mutual reference and mutual combination between these specific examples.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. If there is any inconsistency, the meaning explained in the specification or derived from the content described in the specification shall prevail. In addition, the terms used herein are only for the purpose of describing the examples of the present application and are not intended to limit the present application.

[0039] Before detailing the examples of the present application, first introduce the application scenarios of the signal multi-fanout circuit and the test platform provided by the examples of the present application. For example, in the test of a battery management system (BMS) chip, the battery management system usually includes multiple battery units to be tested, and each battery unit often has multiple pins, such as voltage detection pins, temperature detection pins, current detection pins, etc. Therefore, the number of pins to be tested in the entire battery management system is often large. In the test process, it is generally necessary to flexibly switch and manage each pin to ensure that each pin can be tested. The signal multi-fanout circuit and the test platform provided by the present application can provide fanout combination of multiple different types of signals, thereby making the battery management system test more convenient and improving the test efficiency.

[0040] It should be understood that the above application scenarios are exemplary descriptions and are not intended to limit the scope of the present application. The signal multi-fanout circuit and the test platform provided by the present application are applicable to any test scenario requiring different signal fanout, such as test of electronic devices, test of semiconductor devices, test in the automotive field, test in the communication field, etc.

[0041] Next, the signal multi-fanout circuit provided by the present application will be described in detail in combination with the drawings.

[0042] First, it should be noted that the switching devices used in the following embodiments of this application may include mechanical switches, such as relays, toggle switches, push-button switches, etc.; they may also include semiconductor switches, such as transistors, field-effect transistors, insulated-gate bipolar transistors, thyristors, etc.; they may also include photoelectric switches, such as optocouplers, photodiodes, etc.; and they may also include magnetic switches, such as reed switches, etc.

[0043] This embodiment provides a signal fan-out circuit 10 including a multiplexer (MUX) board 100. The multiplexer board 100 includes multiple positions, at least one of which is equipped with a relay. The input signal and output signal of the relay are signal-connected on the multiplexer board 100 to form different types of signal fan-out circuits.

[0044] like Figure 1 As shown, the multiplexer board 100 includes a first position, a second position, and a third position.

[0045] A first relay K1 is placed at the first position. In one implementation, this first relay K1 is a double-pole double-throw relay.

[0046] The first relay K1 includes two input terminals that form a Kelvin connection. The first input terminal is connected to its corresponding drive signal Bus1_Force, and the second input terminal is connected to its corresponding sensing signal Bus1_Sense.

[0047] The first relay K1 also includes four output terminals. The first output terminal outputs its corresponding first drive signal Bus1_CH0_Force through switching device S11, and the third output terminal outputs its corresponding first sensing signal Bus1_CH0_Sense through switching device S13. The second output terminal outputs its corresponding second drive signal Bus1_CH1_Force through switching device S12, and the fourth output terminal outputs its corresponding second sensing signal Bus1_CH1_Sense through switching device S14. Switching devices S11, S12, S13, and S14 are used to control the on / off state of their respective output terminals.

[0048] In this embodiment, the first driving signal Bus1_CH0_Force and the first sensing signal Bus1_CH0_Sense constitute a first signal group. The second driving signal Bus1_CH1_Force and the second sensing signal Bus1_CH1_Sense constitute a second signal group.

[0049] In the embodiment, the first output terminal and the third output terminal are turned on by switching the first relay K1 to the upper path and controlling the switch devices S11 and S13 to be turned on. The second output terminal and the fourth output terminal are turned on by switching the first relay K1 to the lower path and controlling the switch devices S12 and S14 to be turned on.

[0050] The first input terminal of the first relay K1 and the corresponding driving signal Bus1_Force further have a first sub-branch, which includes a switch device S1 and a resistor connected in series, and the other end of the resistor is connected to the positive terminal VCC. The second input terminal of the first relay K1 and the corresponding sensing signal Bus1_Sense further have a second sub-branch, which includes a switch device S2 and a resistor connected in series, and the other end of the resistor is connected to the ground terminal. In the second sub-branch, an analog-to-digital converter ADC is further connected between the switch device S2 and the resistor. By setting the first sub-branch and the second sub-branch, the self-checking function of the circuit 10 can be realized, and the specific implementation manner is described in detail below.

[0051] The second relay K2 is arranged at the second position. As an implementation manner, the second relay K2 is a double-pole double-throw relay.

[0052] The second relay K2 includes two input terminals constituting a Kelvin connection, the first input terminal is connected to the corresponding driving signal Bus2_Force through the switch device S15, and the second input terminal is connected to the corresponding sensing signal Bus2_Sense through the switch device S17. The first input terminal of the second relay K2 is further connected to the first output terminal of the first relay K1 through the switch device S7. The second input terminal of the second relay K2 is further connected to the third output terminal of the first relay K1 through the switch device S9.

[0053] The second relay K2 further includes four output terminals, the first output terminal is used to output the corresponding first driving signal Bus2_CH0_Force, and the third output terminal is used to output the corresponding first sensing signal Bus2_CH0_Sense. The second output terminal is used to output the corresponding second driving signal Bus2_CH1_Force, and the fourth output terminal is used to output the corresponding second sensing signal Bus2_CH1_Sense. The first output terminal and the third output terminal are connected through the switch device S3, and the second output terminal and the fourth output terminal are connected through the switch device S4.

[0054] The third relay K3 is arranged at the third position. As an implementation manner, the third relay K3 is a double-pole double-throw relay.

[0055] The third relay K3 includes two inputs which form a Kelvin connection. The first input is connected to its corresponding driving signal Bus3_Force through the switching device S16, and the second input is connected to its corresponding sensing signal Bus3_Sense through the switching device S18. The first input of the third relay K3 is also connected to the second output of the first relay K1 through the switching device S8. The second input of the third relay K3 is also connected to the fourth output of the first relay K1 through the switching device S10.

[0056] The third relay K3 also includes four outputs. The first output is used to output its corresponding first driving signal Bus3_CH0_Force, and the third output is used to output its corresponding first sensing signal Bus3_CH0_Sense. The second output is used to output its corresponding second driving signal Bus3_CH1_Force, and the fourth output is used to output its corresponding second sensing signal Bus3_CH1_Sense. The first output and the third output are connected through the switching device S5, and the second output and the fourth output are connected through the switching device S6.

[0057] From the above, the first sub-circuit is formed by the first relay K1 at the first position, the second relay K2 at the second position, and the third relay K3 at the third position. It should be understood that the first sub-circuit herein can be understood as a group of circuits. In some embodiments, a plurality of first sub-circuits can be arranged on the multiplexer board card 100, for example Figure 2 In the illustrated embodiment, 12 groups of first sub-circuits are arranged on one multiplexer board card 100, wherein Bus1-Bus3 are the first group of first sub-circuits, and Bus34-Bus36 are the twelfth group of first sub-circuits. It should be noted that the 12 groups are only exemplary descriptions, and in other embodiments, the number of groups arranged can be determined according to specific needs or the size of the multiplexer board card 100.

[0058] Next, the different signal fan-out circuits formed by different signal splicing will be described with Figure 2 as an example.

[0059] Type one: form 36-way 1 / 2 signal fan-out.

[0060] The switching devices S1-S10 are controlled to be open, and the switching devices S11-S18 are controlled to be closed.

[0061] 1 / 2 signal fan-out for the first path: First, switch the first relay K1 to the upper path conduction. The signal is input from the two input terminals of the first relay K1 (i.e., input from Bus1_Force and Bus1_Sense), and the signal is output from the first output terminal and the third output terminal of the first relay K1 (i.e., output from Bus1_CH0_Force and Bus1_CH0_Sense) via the switching devices S11 and S13. Then, switch the first relay K1 to the lower path conduction. The signal is input from the two input terminals of the first relay K1 (i.e., input from Bus1_Force and Bus1_Sense), and the signal is output from the second output terminal and the fourth output terminal of the first relay K1 (i.e., output from Bus1_CH1_Force and Bus1_CH1_Sense) via the switching devices S12 and S14. Thus, 1 / 2 signal fan-out is achieved.

[0062] 1 / 2 signal fan-out for the second path: First, switch the second relay K2 to the upper path conduction. The signal is input from the two input terminals of the second relay K2 (i.e., input from Bus2_Force and Bus2_Sense), and the signal is output from the first output terminal and the third output terminal of the second relay K2 (i.e., output from Bus2_CH0_Force and Bus2_CH0_Sense) via the switching devices S15 and S17. Then, switch the second relay K2 to the lower path conduction. The signal is input from the two input terminals of the second relay K2 (i.e., input from Bus2_Force and Bus2_Sense), and the signal is output from the second output terminal and the fourth output terminal of the second relay K2 (i.e., output from Bus2_CH1_Force and Bus2_CH1_Sense) via the switching devices S15 and S17. Thus, 1 / 2 signal fan-out is achieved.

[0063] 1 / 2 signal fan-out for the third path: First, switch the third relay K3 to the upper path conduction. The signal is input from the two input terminals of the third relay K3 (i.e., input from Bus3_Force and Bus3_Sense), and the signal is output from the first output terminal and the third output terminal of the third relay K3 (i.e., output from Bus3_CH0_Force and Bus3_CH0_Sense) via the switching devices S16 and S18. Then, switch the third relay K3 to the lower path conduction. The signal is input from the two input terminals of the third relay K3 (i.e., input from Bus3_Force and Bus3_Sense), and the signal is output from the second output terminal and the fourth output terminal of the third relay K3 (i.e., output from Bus3_CH1_Force and Bus3_CH1_Sense) via the switching devices S16 and S18. Thus, 1 / 2 signal fan-out is achieved.

[0064] Since the first relay K1, the second relay K2, and the third relay K3 constitute the first sub-circuit, the first sub-circuit can form a 3-way 1-to-2 signal fan-out, and Figure 2 There are 12 groups of the first sub-circuit in the circuit shown, and other signal fan-out principles are the same, so Figure 2 The circuit shown can form a 36-way (12 groups * 3 ways) 1-to-2 signal fan-out.

[0065] Type two: form a 12-way 1-to-3 signal fan-out + a 12-way 1-to-2 signal fan-out.

[0066] The control switch devices S1-S6, S8, S10, S11, S13, S15, and S17 are open, and the control switch devices S7, S9, S12, S14, S16, and S18 are closed.

[0067] 1-to-3 signal fan-out: first switch the first relay K1 to the lower pass conduction. The signal is input from the two input ends of the first relay K1 (i.e., input from Bus1_Force and Bus1_Sense), and output from the second output end and the fourth output end of the first relay K1 (i.e., output from Bus1_CH1_Force and Bus1_CH1_Sense) via the switch devices S12 and S14, thereby realizing the fan-out of the first way of signal. Then switch the first relay K1 to the upper pass conduction, and switch the second relay K2 to the upper pass conduction, the signal is input from the two input ends of the second relay K2 (i.e., input from Bus2_Force and Bus2_Sense), and output from the first output end and the third output end of the second relay K2 (i.e., output from Bus2_CH0_Force and Bus2_CH0_Sense) via the switch devices S15 and S17, thereby realizing the fan-out of the second way of signal. Then switch the first relay K1 to the upper pass conduction, and switch the second relay K2 to the lower pass conduction, the signal is input from the two input ends of the second relay K2 (i.e., input from Bus2_Force and Bus2_Sense), and output from the second output end and the fourth output end of the second relay K2 (i.e., output from Bus2_CH1_Force and Bus2_CH1_Sense) via the switch devices S15 and S17, thereby realizing the fan-out of the third way of signal.

[0068] Therefore, the 1-to-3 signal fan-out is realized.

[0069] 1 / 2 signal fan-out: switch the third relay K3 to the upper path conduction. The signal is input from the two input terminals of the third relay K3 (i.e. input from Bus3_Force and Bus3_Sense), and via the switching devices S16 and S18, the signal is output from the first output terminal and the third output terminal of the third relay K3 (i.e. output from Bus3_CH0_Force and Bus3_CH0_Sense). Then switch the third relay K3 to the lower path conduction. The signal is input from the two input terminals of the third relay K3 (i.e. input from Bus3_Force and Bus3_Sense), and via the switching devices S16 and S18, the signal is output from the second output terminal and the fourth output terminal of the third relay K3 (i.e. output from Bus3_CH1_Force and Bus3_CH1_Sense). Thus, 1 / 2 signal fan-out is achieved.

[0070] From the above, 1 / 2 signal fan-out is achieved.

[0071] Similarly, since the first relay K1, the second relay K2, and the third relay K3 constitute the first sub-circuit, the first sub-circuit can form 1 / 3 signal fan-out + 1 / 2 signal fan-out, then Figure 2 The 12 groups of the first sub-circuit shown can form 12-way 1 / 3 signal fan-out + 12-way 1 / 2 signal fan-out.

[0072] Type three: form 12-way 1 / 4 signal fan-out.

[0073] The switching devices S1-S6 and S11-S18 are controlled to be open, and the switching devices S7-S10 are controlled to be closed.

[0074] 1st signal fan-out: switch the first relay K1 and the second relay K2 to the upper path conduction, and the state of the third relay K3 remains (it should be understood that the default state of the double-pole double-throw relay is that both poles are in the upper path after power-on, and the state here remains refers to remaining in the default state). The signal is input from the two input terminals of the first relay K1 (i.e. input from Bus1_Force and Bus1_Sense), and via the upper path of the first relay K1, the switching devices S7 and S9, and the upper path of the second relay K2, the signal is output from the first output terminal and the third output terminal of the second relay K2 (i.e. output from Bus2_CH0_Force and Bus2_CH0_Sense), thereby achieving the 1st signal fan-out.

[0075] The 2nd signal fan-out: switch the first relay K1 to the upper pass conductive, switch the second relay K2 to the lower pass conductive, and keep the third relay K3. The signal is input from the two input terminals of the first relay K1 (i.e. input from Bus1_Force and Bus1_Sense), and is output from the second output terminal and the fourth output terminal of the second relay K2 (i.e. output from Bus2_CH1_Force and Bus2_CH1_Sense) via the upper pass of the first relay K1, the switching devices S7 and S9, and the lower pass of the second relay K2, thereby realizing the 2nd signal fan-out.

[0076] The 3rd signal fan-out: switch the first relay K1 to the lower pass conductive, switch the third relay K3 to the upper pass conductive, and keep the second relay K2. The signal is input from the two input terminals of the first relay K1 (i.e. input from Bus1_Force and Bus1_Sense), and is output from the first output terminal and the third output terminal of the third relay K3 (i.e. output from Bus3_CH0_Force and Bus3_CH0_Sense) via the lower pass of the first relay K1, the switching devices S8 and S10, and the upper pass of the third relay K3, thereby realizing the 3rd signal fan-out.

[0077] The 4th signal fan-out: switch the first relay K1 to the lower pass conductive, switch the third relay K3 to the lower pass conductive, and keep the second relay K2. The signal is input from the two input terminals of the first relay K1 (i.e. input from Bus1_Force and Bus1_Sense), and is output from the second output terminal and the fourth output terminal of the third relay K3 (i.e. output from Bus3_CH1_Force and Bus3_CH1_Sense) via the lower pass of the first relay K1, the switching devices S8 and S10, and the lower pass of the third relay K3, thereby realizing the 4th signal fan-out.

[0078] Similarly, since the first relay K1, the second relay K2, and the third relay K3 form the first sub-circuit, the first sub-circuit can form a 1-to-4 signal fan-out, and then Figure 2 The 12 groups of the first sub-circuit shown can form a 12-way 1-to-4 signal fan-out.

[0079] The above-mentioned type one, type two, and type three are all formed by different signal connections on the multiplexer board card to form different types of signal fan-out circuits. It should be understood that the above-mentioned three types are only exemplary descriptions, and in other embodiments, other forms of signal connections can be performed to form signal fan-out circuits different from the above-mentioned three types, which are not limited in the present application.

[0080] In some embodiments, asFigure 3 As shown, a fourth position is further included on the multiplexer board card 100.

[0081] A fourth relay K4 is arranged at the fourth position. As an implementation manner, the fourth relay K4 is a double-pole double-throw relay.

[0082] The fourth relay K4 includes two inputs constituting a Kelvin connection, a first input being connected with its corresponding driving signal Bus4_Force, and a second input being connected with its corresponding sensing signal Bus4_Sense.

[0083] The fourth relay K4 further includes four outputs, a first output outputting its corresponding first driving signal Bus4_CH0_Force through a switching device S21, and a third output outputting its corresponding first sensing signal Bus4_CH0_Sense through a switching device S23. A second output outputs its corresponding second driving signal Bus4_CH1_Force through a switching device S22, and a fourth output outputs its corresponding second sensing signal Bus4_CH1_Sense through a switching device S24. The switching device S21, the switching device S22, the switching device S23, and the switching device S24 are respectively used to realize control of the on-off of the corresponding output.

[0084] The first output of the fourth relay K4 is connected with the first input of the third relay K3 through a switching device S25, and the third output of the fourth relay K4 is connected with the second input of the third relay K3 through a switching device S26. The second output of the fourth relay K4 is connected with the first input of the second relay K2 through a switching device S27, and the fourth output of the fourth relay K4 is connected with the second input of the second relay K2 through a switching device S28.

[0085] There is also a third sub-branch between the first input of the fourth relay K4 and its corresponding driving signal Bus4_Force, and the third sub-branch includes a switching device S19 and a resistor connected in series, and the other end of the resistor is connected with the positive terminal VCC. There is also a fourth sub-branch between the second input of the fourth relay K4 and its corresponding sensing signal Bus4_Sense, and the fourth sub-branch includes a switching device S20 and a resistor connected in series, and the other end of the resistor is connected to the ground terminal. In the fourth sub-branch, an analog-to-digital converter ADC is further connected between the switching device S20 and the resistor.

[0086] From the above, the second sub-circuit is formed by the first relay K1 at the first position, the second relay K2 at the second position, the third relay K3 at the third position, and the fourth relay K4 at the fourth position. The second sub-circuit herein can be understood as a minimum unit of a group of circuits. In some embodiments, a plurality of second sub-circuits can be arranged on the multiplexer board card 100 according to specific requirements or the size of the area of the multiplexer board card 100, and the number of the second sub-circuits is not limited in the present application.

[0087] In some embodiments, by connecting different types of signals on the multiplexer board card 100, the above Figure 3 The circuit shown forms a plurality of different signal fan-out circuits, including but not limited to 4-way 1-to-2 signal fan-out, 2-way 1-to-3 signal fan-out, 1-way 1-to-4 signal fan-out + 1-way 1-to-2 signal fan-out, etc. Based on the description of the above type 1 to type 3 signal connection, the signal connection herein will not be described again in the embodiments of the present application.

[0088] In some embodiments, the multiplexer board card 100 includes a plurality of positions, at least one position is arranged with a relay, and the input signal and the output signal of the relay are led out to the outside of the multiplexer board card 100 for signal connection outside to form different types of signal fan-out circuits. The essence of this way is to only keep the main relays on the multiplexer board card 100, and the remaining switching devices are not used, and the input signals and the output signals of all the main relays are led out to the outside of the board card, so as to perform signal connection outside, thereby saving costs and realizing expansion of different signal fan-out types.

[0089] As Figure 4 Fig. 6 shows a schematic diagram of leading out the input signal and the output signal to the outside of the board card for signal connection to form a 1-to-2 signal fan-out circuit. In this example, the multiplexer board card 100 includes 36 positions for arranging the first relay K1 to the thirty-sixth relay K36. Among them, the first relay K1 to the thirty-sixth relay K36 are all double-pole double-throw relays.

[0090] Each relay includes two input terminals constituting a Kelvin connection, both of which are led out to the outside of the multiplexer board card, the first input terminal is connected with the corresponding driving signal BusN_Force, and the second input terminal is connected with the corresponding sensing signal BusN_Sense.

[0091] Each relay includes four outputs, all of which are led out of the multiplexer board card, the first output is used to output its corresponding first drive signal BusN_CH0_Force, and the third output is used to output its corresponding first sensing signal BusN_CH0_Sense. The second output is used to output its corresponding second drive signal BusN_CH1_Force, and the fourth output is used to output its corresponding second sensing signal BusN_CH1_Sense.

[0092] Since Figure 4 The first relay K1 to the thirty-sixth relay K36 in the circuit shown are all double-pole double-throw relays, so that by controlling the upper pass or the lower pass of each relay to be turned on. 36-way 1 / 2 signal fan-out can be achieved.

[0093] As Figure 5 The 1 / 3 signal fan-out circuit formed by signal splicing on the circuit shown. Figure 4 As Figure 5 The fifth position and the sixth position are included on the multiplexer board card 100.

[0094] The fifth relay K5 is arranged at the fifth position, and the sixth relay K6 is arranged at the sixth position. As an implementation manner, the fifth relay K5 and the sixth relay K6 are both double-pole double-throw relays.

[0095] The two input terminals and the four output terminals of the fifth relay K5 are all led out of the multiplexer board card 100, and the two input terminals and the four output terminals of the sixth relay K6 are also led out of the multiplexer board card 100. The first input terminal of the fifth relay K5 is connected with its corresponding drive signal Bus5_Force, and the second input terminal of the fifth relay K5 is connected with its corresponding sensing signal Bus5_Sense. The first output terminal Bus5_CH0_Force of the fifth relay is connected with the first input terminal Bus6_Force of the sixth relay K6, and the third output terminal Bus5_CH0_Sense of the fifth relay is connected with the second input terminal Bus6_Sense of the sixth relay K6.

[0096] 1 / 3 signal fan-out:

[0097] Both the fifth relay K5 and the sixth relay K6 are switched to the upper channel conduction. The signal is input from the two input terminals of the fifth relay K5 (i.e., from Bus5_Force and Bus5_Sense), then through the first and third output terminals of the fifth relay K5 (i.e., from Bus5_CH0_Force and Bus5_CH0_Sense) to the two input terminals of the sixth relay K6 (i.e., from Bus6_Force and Bus6_Sense), and then flows through the upper channel of the sixth relay K6. The signal is output from the first and third output terminals of the sixth relay K6 (i.e., from Bus6_CH0_Force and Bus6_CH0_Sense), thus realizing the signal fan-out of the first channel.

[0098] The fifth relay K5 is switched to the upper channel conduction, and the sixth relay is switched to the lower channel conduction. The signal is input from the two input terminals of the fifth relay K5 (i.e., from Bus5_Force and Bus5_Sense), then flows through the first and third output terminals of the fifth relay K5 (i.e., from Bus5_CH0_Force and Bus5_CH0_Sense) to the two input terminals of the sixth relay K6 (i.e., from Bus6_Force and Bus6_Sense), and then flows through the lower channel of the sixth relay K6. The signal is output from the second and fourth output terminals of the sixth relay K6 (i.e., from Bus6_CH1_Force and Bus6_CH1_Sense), thus realizing the signal fan-out of the second channel.

[0099] Switch the fifth relay K5 to the lower path conduction. The signal is input from the two input terminals of the fifth relay K5 (i.e., from Bus5_Force and Bus5_Sense), and then output from the second and fourth output terminals of the fifth relay K5 (i.e., from Bus5_CH1_Force and Bus5_CH1_Sense) via the lower path of the fifth relay K5, thus realizing the signal fan-out of the third channel.

[0100] Thus, the signal fan-out of 1 to 3 is achieved.

[0101] like Figure 6 The image shows the result of... Figure 4 The circuit shown is a 1-to-4 signal fan-out circuit formed by signal bonding. Figure 6 As shown, the multiplexer board 100 also includes a seventh position.

[0102] A seventh relay K7 is arranged at the seventh position. As one implementation method, the seventh relay K7 is a double-pole double-throw relay.

[0103] The two input terminals and four output terminals of the seventh relay K7 are led out to the outside of the multiplexer board card 100. The first input terminal Bus7_Force of the seventh relay K7 is connected with the first output terminal Bus6_CH0_Force of the sixth relay K6, and the second input terminal Bus7_Sense of the seventh relay K7 is connected with the third output terminal Bus6_CH0_Sense of the sixth relay K6.

[0104] In the embodiment, through switching the pass of the fifth relay K5, the sixth relay K6 and the seventh relay K7, the 1 / 4 signal fan-out can be realized, which will not be described here.

[0105] Next, the application of the above-mentioned embodiments of the present application will be described by taking chip testing as an example.

[0106] As shown in Figure 7 , it is an application of the above-mentioned Figure 5 1 / 3 signal fan-out circuit. As shown in Figure 7 , X1 is a chip to be tested, X2 is a FOVIe board card, and X3 is an FPVIe board card. The FOVIe is an 8-channel voltage and current source, which can provide 8 independent voltage and current source channels, and each channel can be independently controlled. The FPVIe is a 2-channel voltage and current source, which can provide 2 independent voltage and current source channels, and each channel can be independently controlled. In the example, the FOVIe board card is used to provide voltage or current for the chip to be tested, and the FPVIe is used to provide load for the chip to be tested.

[0107] In Figure 7 , the pins of X1 are connected to the two input terminals (i.e. Bus5_Force and Bus5_Sense) of the fifth relay K5, the pins of X2 are connected to the first output terminal and the third output terminal (i.e. Bus6_CH0_Force and Bus6_CH0_Sense) of the sixth relay K6, the pins of X3 are connected to the second output terminal and the fourth output terminal (i.e. Bus6_CH1_Force and Bus6_CH1_Sense) of the sixth relay K6, and the second output terminal and the fourth output terminal (i.e. Bus5_CH1_Force and Bus5_CH1_Sense) of the fifth relay K5 are grounded, and the rest of the connection relationship is the same as that in Figure 5 , which will not be described here.

[0108] In this example, if the fifth relay K5 is switched to the lower path conduction, then the pin of the chip X1 under test is grounded. If the fifth relay K5 and the sixth relay K6 are both switched to the upper path conduction, then the chip X1 under test is connected to the corresponding FOVIe board card of X2. If the fifth relay K5 is switched to the upper path conduction and the sixth relay K6 is switched to the lower path conduction, then the chip X1 under test is connected to the corresponding FPVIe board card of X3. The detection of the chip under test can be achieved by switching the above-mentioned relay switching states.

[0109] Next, the on-line self-checking function of the circuit is introduced by taking Figure 1 In other embodiments, if the multiplexing board card 100 includes multiple groups of the first sub-circuit, the same method can be used for fault self-checking.

[0110] First of all, it should be pointed out that for a double-pole double-throw relay, the default state when powered on is the upper path conduction, so in the following, the state retention of the initial state of the relay indicates the upper path conduction, and the state retention after the switching of the relay indicates the retention of the previous state without switching. For the switching device, the state retention also indicates the retention of the previous state without switching.

[0111] Step 1: control the closing of the switching devices S1, S2, S3, S7, S9, and the opening of the other switching devices.

[0112] Step 2: switch the first relay K1 and the second relay K2 to the upper path conduction, and retain the state of the third relay K3. If the ADC in the second sub-branch detects a high level, it can be determined that the upper path and the lower path of the first relay K1 and the second relay K2 are both fault-free, and then step 3 is executed. If the ADC in the second sub-branch detects a low level, it can be determined that the first relay K1 or the second relay K2 has a fault.

[0113] Step 3: control the lower path conduction of the second relay K2, and retain the states of the first relay K1 and the third relay K3. If the ADC in the second sub-branch detects a low level, step 4 is executed. If the ADC in the second sub-branch detects a high level, the upper path of the second relay K2 has a fault.

[0114] Step 4: retain the states of the first relay K1, the second relay K2, and the third relay K3, control the opening of the switching device S3 while controlling the closing of the switching device S4. If the ADC in the second sub-branch detects a high level, it can be determined that the upper path and the lower path of the second relay K2 are both fault-free, and then step 5 is executed. If the ADC in the second sub-branch detects a low level, it is determined that the upper path of the second relay K2 has a fault, and then the detection of the second relay K2 is completed.

[0115] Step 5: Switch the first relay K1 to the lower path conduction, and the second relay K2 and the third relay K3 remain unchanged. At the same time, the switch device S3 and the switch device S4 remain unchanged. If the ADC in the second sub-branch detects a low level, it is determined that the upper path of the first relay K1 is fault-free, and step 6 is performed; if the ADC in the second sub-branch detects a high level, it is determined that the upper path of the first relay K1 is faulty.

[0116] Step 6: Keep the first relay K1 unchanged, switch the third relay K3 to the upper path conduction, control the switch device S5 to be closed while controlling the switch devices S3, S4, and S6 to be opened. If the ADC in the second sub-branch detects a high level, it is determined that the first relay K1 is fault-free, and the detection of the first relay K1 is completed, and then step 7 is performed. If the ADC in the second sub-branch detects a low level, the first relay K1 or the third relay K3 is faulty.

[0117] Step 7: Switch the third relay to the lower path conduction, and the first relay K1 and the second relay K2 remain unchanged. If the ADC in the second sub-branch detects a low level, step 8 is performed. If the ADC in the second sub-branch detects a high level, it is determined that the upper path of the third relay K3 is faulty.

[0118] Step 8: Switch the third relay to the lower path conduction, and the first relay K1 and the second relay K2 remain unchanged. Control the switch device S5 to be opened while controlling the switch device S6 to be closed. If the ADC in the second sub-branch detects a high level, it is determined that the third relay K3 is fault-free. If the ADC in the second sub-branch detects a low level, it is determined that the upper path of the third relay K3 is faulty.

[0119] Through the above steps 1-8, the online self-checking of a group of first sub-circuits is completed. Through the online self-checking, problems can be quickly found.

[0120] The circuit provided in the application also supports offline self-checking function.

[0121] As Figure 8 It is shown as a diagnosis board for realizing the offline diagnosis function of the circuit provided in the above embodiments. In this example, a maximum of 12 MUX board cards are simultaneously diagnosed. It should be understood that in other embodiments, the number of simultaneously diagnosed MUXs can be arranged according to the area and needs of the diagnosis board.

[0122] Next, taking detection of a MUX_1 board card as an example to illustrate the off-line diagnosis function. Among them, two input ends of the first relay MUX_1_K1 on the MUX_1 board card are connected to a resistor through a switching device VCC_K1 and a switching device VCC_K2, and the other end of the resistor is connected to a 3.3V positive voltage (VCC_3.3V). The first output end and the fourth output end of the first relay MUX_1_K1 on the MUX_1 board card are suspended, the second output end is connected to the first IO port (i.e. IO1) of the FPGA chip through the bus control switch K3_Bus; the third output end is connected to the second IO port (i.e. IO2) of the FPGA chip through the bus control switch K4_Bus, and the first IO port and the second IO port are respectively connected to the ground end through a resistor. The connection mode of other relays on the MUX_1 board card is the same as that of the first relay MUX_1_K1, and the whole diagnosis board shares the control bus, and the control bit is provided by the C-Bit (Control Bit) board card. Whether each relay is faulty can be determined by identifying the high and low levels of IO1 and IO2.

[0123] For example, when detecting whether the first relay MUX_1_K1 on the MUX_1 board card has a fault: control the switching device VCC_K1, the switching device VCC_K2, the bus control switch K3_Bus and the bus control switch K4_Bus to be closed, when the first relay is in the default state (i.e. the double knife is placed in the upper passage), if IO1 is low and IO2 is high, switch the first relay (i.e. the double knife is placed in the lower passage), if IO1 is high and IO2 is low, it is considered that the first relay is normal. For other states of IO1 and IO2, it is considered that the first relay has a fault.

[0124] In order to more clearly describe the fault detection, the following provided diagnosis truth table can be referred to:

[0125]

[0126]

[0127] It should be understood that the first relay MUX_K1 is taken as an example in the embodiment, and the detection process and the diagnosis truth table of other relays are the same as those of the first relay MUX_K1, so the description is not repeated.

[0128] Another embodiment of the application also provides a hardware test platform (Test Hardware Board, a hardware test board for chip testing), as shown in Figure 9 The signal multi-fanout circuit provided in the above embodiment can be installed on the back of the hardware test platform, that is, the MUX board card is installed on the back of the hardware test platform.

[0129] In some embodiments, due to the existence of more stiffeners on the hardware test platform, the installation of the test module in the hardware test platform is limited by the area, and the area of the MUX board card in the present embodiment is 80mm*55mm, which can be adapted to the hardware test platform. In other embodiments, the area size of the MUX board card can be set as needed, which is not specifically limited here.

[0130] In order to further reduce the layout pressure of the hardware test platform, the MUX board card of the present application can also be laid out in the form of a stacked board, that is, a plurality of (for example, two) MUX boards are stacked together, which not only solves the problem of limited layout, but also forms more resource fan-outs. Among them, the schematic diagram of the stacked board can refer to FIG. 10. In FIG. 10, HFD5 and AC30 represent the selected relay model.

[0131] As shown in FIG. 9, for different types of stiffeners, the layout position of the MUX is shown. Figures 10a to 10d As shown in FIG. 9, for different types of stiffeners, the layout position of the MUX is shown.

[0132] As shown in FIG. 9, for different types of stiffeners, the layout position of the MUX is shown. Figure 10a As shown in FIG. 9, for different types of stiffeners, the layout position of the MUX is shown. As shown in FIG. 9, for different types of stiffeners, the layout position of the MUX is shown.

[0133] As shown in FIG. 9, for different types of stiffeners, the layout position of the MUX is shown. Figure 10b As shown in FIG. 9, for different types of stiffeners, the layout position of the MUX is shown. As shown in FIG. 9, for different types of stiffeners, the layout position of the MUX is shown.

[0134] As shown in FIG. 9, for different types of stiffeners, the layout position of the MUX is shown. Figure 10c As shown in FIG. 9, for different types of stiffeners, the layout position of the MUX is shown. As shown in FIG. 9, for different types of stiffeners, the layout position of the MUX is shown.

[0135] As shown in FIG. 9, for different types of stiffeners, the layout position of the MUX is shown. Figure 10d As shown in FIG. 9, for different types of stiffeners, the layout position of the MUX is shown. Figure 10d As shown in FIG. 9, for different types of stiffeners, the layout position of the MUX is shown.

[0136] In another embodiment of the present application, the MUX board card can include an FPGA circuit and a driving circuit of a relay, and the hardware test platform system communicates with the plurality of MUXs through an I2C bus, and controls the action of the relay through an API function based on the driving circuit, so that the control of the relay does not need to occupy the control bit resources of the C-Bit board card, thereby saving resources.

[0137] Note that the above merely describes preferred embodiments of the present application and the applied technical principles. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, modifications and substitutions can be made without departing from the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and all fall within the scope of the present application.

Claims

1. A signal multiplexing fan-out circuit, characterized in that, include: A multiplexer board, the multiplexer board including multiple locations; At least one of the plurality of locations is equipped with a relay, and the input and output signals of the relay are signal-overlapped on the multiplexer board to form different types of signal fan-out circuits; or At least one of the plurality of locations is provided with a relay, the input and output signals of which are led out to the outside of the multiplexer board for signal bonding to form different types of signal fan-out circuits.

2. The circuit according to claim 1, characterized in that, The relay includes at least: The two input terminals that form a Kelvin connection are: the first input terminal is used to connect the drive signal, and the second input terminal is used to connect the sensing signal. The relay includes at least four output terminals: a first output terminal for outputting a first drive signal, a third output terminal for outputting a first sensing signal, a second output terminal for outputting a second drive signal, and a fourth output terminal for outputting a second sensing signal; wherein the first drive signal and the first sensing signal constitute a first signal group; and the second drive signal and the second sensing signal constitute a second signal group.

3. The circuit according to claim 2, characterized in that, The plurality of positions includes at least a first position, a second position, and a third position; A first relay is arranged at the first position. The first input terminal of the first relay is connected to its corresponding drive signal, and the second input terminal of the first relay is connected to its corresponding sensing signal. The four output terminals of the first relay are respectively connected to switching devices to control the on / off state of each output terminal. A second relay is arranged at the second position. The first input terminal of the second relay is connected to the first output terminal of the first relay through a switching device. A switching device is also connected between the first input terminal of the second relay and its corresponding drive signal. The second input terminal of the second relay is connected to the third output terminal of the first relay through a switching device. A switching device is also connected between the second input terminal of the second relay and its corresponding sensing signal. The first and third output terminals of the second relay are connected by a switching device, and the second and fourth output terminals of the second relay are connected by a switching device. A third relay is arranged at the third position. The first input terminal of the third relay is connected to the second output terminal of the first relay via a switching device. A switching device is also connected between the first input terminal of the third relay and its corresponding drive signal. The second input terminal of the third relay is connected to the fourth output terminal of the first relay via a switching device. A switching device is also connected between the second input terminal of the third relay and its corresponding sensing signal. The first and third output terminals of the third relay are connected via a switching device, and the second and fourth output terminals of the third relay are connected via a switching device.

4. The circuit according to claim 3, characterized in that, There is a first sub-branch between the first input terminal of the first relay and its corresponding drive signal. The first sub-branch includes a first switching device and a first resistor connected in series. The end of the first resistor away from the first switching device is connected to the positive terminal. There is a second sub-branch between the second input terminal of the first relay and its corresponding sensing signal. The second sub-branch includes a second switching device and a second resistor connected in series. The end of the second resistor away from the second switching device is connected to ground. In the second sub-branch, an analog-to-digital converter is also connected between the second switching device and the second resistor.

5. The circuit according to claim 3 or 4, characterized in that, The first relay, the second relay, and the third relay constitute the first sub-circuit; At least one of the first sub-circuits is arranged on the multiplexer board.

6. The circuit according to claim 3, characterized in that, The plurality of positions also includes a fourth position; A fourth relay is arranged at the fourth position. The first input terminal of the fourth relay is connected to its corresponding drive signal, and the second input terminal of the fourth relay is connected to its corresponding sensing signal. The four output terminals of the fourth relay are respectively connected to switching devices to control the on / off state of each output terminal. The first output terminal of the fourth relay is connected to the first input terminal of the third relay via a switching device, and the third output terminal of the fourth relay is connected to the second input terminal of the third relay via a switching device. The second output terminal of the fourth relay is connected to the first input terminal of the second relay via a switching device, and the fourth output terminal of the fourth relay is connected to the second input terminal of the second relay via a switching device.

7. The circuit according to claim 6, characterized in that, There is a third sub-branch between the first input terminal of the fourth relay and its corresponding drive signal. The third sub-branch includes a third switching device and a third resistor connected in series. The end of the third resistor away from the switching device is connected to the positive terminal. There is a fourth sub-branch between the second input terminal of the fourth relay and its corresponding sensing signal. The fourth sub-branch includes a fourth switching device and a fourth resistor connected in series. The end of the fourth resistor away from the fourth switching device is connected to ground. In the fourth sub-branch, an analog-to-digital converter is also connected between the fourth switching device and the fourth resistor.

8. The circuit according to claim 6 or 7, characterized in that, The first relay, the second relay, the third relay, and the fourth relay constitute the second sub-circuit; At least one second sub-circuit is arranged on the multiplexer board.

9. The circuit according to claim 2, characterized in that, The plurality of positions includes at least a fifth position and a sixth position; A fifth relay is arranged at the fifth position, and the two input terminals and four output terminals of the fifth relay are all led out to the outside of the multiplexer board. A sixth relay is arranged at the sixth position, and the two input terminals and four output terminals of the sixth relay are all led out to the outside of the multiplexer board. The first input terminal of the fifth relay is connected to its corresponding drive signal, and the second input terminal of the fifth relay is connected to its corresponding sensing signal; the first output terminal of the fifth relay is connected to the first input terminal of the sixth relay, and the third output terminal of the fifth relay is connected to the second input terminal of the sixth relay.

10. The circuit according to claim 9, characterized in that, The plurality of positions also includes a seventh position; A seventh relay is arranged at the seventh position, and the two input terminals and four output terminals of the seventh relay are all led out to the outside of the multiplexer board. The first input terminal of the seventh relay is connected to the first output terminal of the sixth relay, and the second input terminal of the seventh relay is connected to the third output terminal of the sixth relay.

11. A testing platform, characterized in that, include: The circuit according to any one of claims 1-10; The circuits are arranged on the test platform in a stacked manner using multiplexer boards.

Images