FC packaging structure

Abstract

The utility model relates to the technical field of semiconductor packaging substrates, and discloses an FC packaging structure which comprises a substrate, a plurality of clamping strips are fixedly connected to the top of the substrate, a plurality of wafers are fixedly connected to the top of the substrate, grooves are formed in the bottoms of the wafers, a dielectric layer is fixedly connected to the top of the substrate, and the clamping strips are fixedly connected to the top of the substrate. The top of the dielectric layer is fixedly connected with a rewiring layer, the top of the rewiring layer is provided with a protection assembly used for protection, the outside of the substrate is fixedly connected with a plastic packaging layer, the protection assembly comprises an electromagnetic shielding layer, and the bottom of the electromagnetic shielding layer is fixedly connected to the top of the rewiring layer. According to the utility model, the packaging density is greatly improved, compared with a traditional packaging mode, more functional circuits can be integrated in a limited space, the damage risk of the chip is reduced, the reliability of the chip is improved, the service life of the chip is prolonged, the targets of increasing output and reducing cost are achieved, and the packaging efficiency and quality are comprehensively improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging substrate technology, and in particular to an FC packaging structure. Background Technology

[0002] FC packaging (Flip-Chip packaging) is an advanced chip packaging technology. In FC packaging, the active side of the chip faces down, and the chip is directly connected to the pads on the packaging substrate or circuit board via bumps. Compared to traditional packaging, this method shortens the connection length between the chip and the substrate. Due to the shortened signal transmission path, signal delay is effectively reduced, resulting in superior chip performance at high frequencies and speeds. It is particularly suitable for chips with extremely high requirements for signal transmission speed and integrity, such as high-performance processors and high-speed communication chips.

[0003] Current FC packaging involves using a strip-sized substrate on the packaging production line, attaching the FC chip to the substrate, and then using molding compound to encapsulate the chip and substrate together.

[0004] However, existing FC packages are mostly strip small-size packages or single-unit packages, which have low packaging efficiency and high cost. Therefore, in order to address the above shortcomings, an FC package structure is proposed to solve the above problems. Utility Model Content

[0005] To overcome the above shortcomings, this utility model provides an FC packaging structure, which aims to improve the problems of low packaging efficiency and high cost of existing FlipChip packaging, which is either strip small-size packaging or single-unit packaging.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] An FC packaging structure includes a substrate, a plurality of clips fixedly connected to the top of the substrate, a plurality of wafers fixedly connected to the top of the substrate, grooves formed on the bottom of each of the plurality of wafers, a dielectric layer fixedly connected to the top of the substrate, a redistribution layer fixedly connected to the top of the dielectric layer, a protective component for protection disposed on the top of the redistribution layer, and a molding compound fixedly connected to the outside of the substrate.

[0008] As a further description of the above technical solution:

[0009] The protection component includes an electromagnetic shielding layer, the bottom of which is fixedly connected to the top of the redistribution layer, and a protective layer is fixedly connected to the top of the electromagnetic shielding layer.

[0010] As a further description of the above technical solution:

[0011] The card bar is externally slidably connected to the inside of the trench, and the wafer is nested on top of the substrate using the mSAP process;

[0012] As a further description of the above technical solution:

[0013] The redistribution layer is fabricated using a plastic C-mold method to complete the layer addition. The surface of the wafer is used to fabricate the RDL using Fanin technology to achieve board-level packaging.

[0014] As a further description of the above technical solution:

[0015] The dielectric layer is made of silicon nitride and is manufactured by compression molding.

[0016] As a further description of the above technical solution:

[0017] The electromagnetic shielding layer is made of copper foil, and the protective layer is made of polyimide.

[0018] This utility model has the following beneficial effects:

[0019] 1. In this invention, by applying Fan-in technology to fabricate the RDL on the wafer surface, high-density wiring connections are achieved within a small wafer size range, realizing board-level packaging and greatly improving packaging density. Compared with traditional packaging methods, more functional circuits can be integrated within a limited space. The dielectric layer fabrication method using compression molding replaces the original ABF (Alternating Aspect Foil) method. The compression molding process forms a uniform and stable dielectric layer structure, effectively isolating different conductive layers, preventing electrical signal interference and leakage, and ensuring stable and reliable electrical performance. Furthermore, the exposure and development characteristics of optical dielectric materials replace laser windowing to avoid chip damage, reducing the risk of chip damage and improving chip reliability and lifespan. Grooves are etched into the wafer base for easy nesting with the substrate, while also improving the shortcomings of the dicing process after board-level packaging, reducing defects in the wafer and substrate during dicing, and improving yield. Combined with the large-board-level packaging process of directly packaging the entire wafer and the entire Pnl substrate, the goal of increasing output and reducing costs is achieved, comprehensively improving packaging efficiency and quality.

[0020] 2. In this invention, the electromagnetic shielding layer is made of copper foil and is connected to the top of the redistribution layer. This effectively blocks external electromagnetic interference signals from entering the encapsulation structure, preventing internal electromagnetic signal leakage and avoiding interference from the external electromagnetic environment on the electrical signal transmission on the substrate, thus ensuring the accuracy and stability of signal transmission. The protective layer, made of polyimide and located on top of the electromagnetic shielding layer, resists the erosion and damage to the internal structure caused by external factors such as high temperature, high humidity, and chemical corrosion. It particularly protects the substrate, extending the service life of the substrate and the entire encapsulation structure. The plastic encapsulation layer on the outside of the substrate wraps the entire structure, preventing dust, moisture, and other impurities from entering and causing short circuits or other adverse effects on the substrate and internal circuitry. It also buffers mechanical impacts, ensuring the substrate's normal operation in various complex environments, thereby guaranteeing stable signal transmission throughout the entire encapsulation structure. Attached Figure Description

[0021] Figure 1 This is a perspective view of an FC packaging structure proposed in this utility model;

[0022] Figure 2 This is a schematic diagram of the encapsulation layer structure of an FC packaging structure proposed in this utility model;

[0023] Figure 3 This is a schematic diagram of the wafer structure of an FC packaging structure proposed in this utility model;

[0024] Figure 4 This is a schematic diagram of the protective layer structure of an FC packaging structure proposed in this utility model.

[0025] Legend:

[0026] 1. Substrate; 2. Card strip; 3. Wafer; 4. Trench; 5. Dielectric layer; 6. Rewiring layer; 7. Electromagnetic shielding layer; 8. Protective layer; 9. Molding layer. Detailed Implementation

[0027] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0028] Reference Figures 1 to 3This utility model provides an embodiment of an FC packaging structure, including a substrate 1. Multiple clips 2 are fixedly connected to the top of the substrate 1. The clips 2 play a crucial role in positioning and fixing the wafers 3 during the mounting process, preventing displacement of the wafers 3 during packaging and ensuring the smooth execution of subsequent processes such as mSAP and Fan-in technology for RDL fabrication. Multiple wafers 3 are fixedly connected to the top of the substrate 1. The wafers 3 are nested on top of the substrate 1 using the mSAP process. Fan-in technology is used to fabricate RDLs on the surface of the wafers 3, achieving board-level packaging. The wafers 3 are directly nested and mounted on the surface of the substrate 1 using the mSAP process. The Fan-in technology for RDL fabrication on the surface of the wafers 3 enables high-density wiring connections within a relatively small wafer size, thus achieving board-level packaging. Grooves 4 are formed at the bottom of each of the multiple wafers 3. The external parts of the clips 2 are slidably connected to the inside of the grooves 4. The cooperation between the clips 2 and the grooves 4 ensures the positional accuracy of the wafers 3 on the substrate 1.

[0029] Reference Figures 2 to 4 A dielectric layer 5, made of silicon nitride, is fixedly connected to the top of substrate 1. The dielectric layer 5 is fabricated using a compression molding process, effectively isolating different conductive layers and preventing electrical signal interference and leakage. This compression molding method replaces traditional ABF (Alternating Aspect Fold) methods. This method utilizes the characteristics of compression molding to form a uniform and stable dielectric layer 5 structure on the top of substrate 1. The dielectric layer 5 plays a crucial role in insulation and isolation within the entire packaging structure, ensuring stable electrical performance between the conductive layers. A redistribution layer 6 is fixedly connected to the top of the dielectric layer 5. The redistribution layer 6 is fabricated using a C-mold molding process, completing the layer addition. After applying Fan-in technology to fabricate the RDL (Redirect Layer) on the wafer 3 surface for board-level packaging, the redistribution layer 6 further optimizes and expands the electrical connections. By using C-mold encapsulation, a layer of protection and connectivity is added to the entire package structure while ensuring good electrical connection performance. The redistribution layer 6 can rearrange and transmit signals according to actual circuit design requirements, enabling the package structure to better adapt to different application scenarios and circuit requirements, thus improving the flexibility and adaptability of the package structure. A protective component is provided on the top of the redistribution layer 6, and the encapsulation layer 9 is fixedly connected to the outside of the substrate 1.

[0030] Reference Figure 1 , Figure 2 and Figure 4The protective components include an electromagnetic shielding layer 7, which is made of copper foil. The electromagnetic shielding layer 7 effectively blocks external electromagnetic interference signals from entering the package structure and also prevents internal electromagnetic signals from leaking into the external environment. The bottom of the electromagnetic shielding layer 7 is fixedly connected to the top of the redistribution layer 6. A protective layer 8, made of polyimide, is fixedly connected to the top of the electromagnetic shielding layer 7. The protective layer 8 effectively resists the erosion and damage of these external factors to the internal structure, extends the service life of the package structure, ensures the normal operation of internal chips and circuits, and thus guarantees the performance and reliability of the entire electronic device.

[0031] Working Principle: First, multiple wafers 3 engage with the clips 2 on the top of the substrate 1 via grooves 4 at the bottom. The clips 2 position and fix the wafers 3 directly onto the surface of the substrate 1 using mSAP technology, ensuring smooth subsequent processes. Fan-in technology is applied to the surface of wafers 3 to create an RDL (Redistributed Leading Array), achieving high-density wiring connections within a smaller area to realize board-level packaging. This technology replaces traditional methods, increasing packaging density. The dielectric layer 5 is made of silicon nitride and fabricated using a compression molding process, replacing traditional ABF (Alternating Aspect Foil Forming) methods. This forms a uniform and stable structure on the top of the substrate 1, effectively isolating different conductive layers and preventing electrical signal interference and leakage. The redistribution layer 6 is fabricated using C-mold molding and further optimizes and expands electrical connections based on the Fan-in RDL fabrication for board-level packaging. Signals are rearranged and transmitted according to circuit design requirements, enhancing the flexibility and adaptability of the packaging structure. The electromagnetic shielding layer 7, made of copper foil, is connected to the top of the redistribution layer 6, blocking external electromagnetic interference signals and preventing internal signal leakage. The protective layer 8, made of polyimide, is located on top of the electromagnetic shielding layer 7. It resists external erosion and damage, extends the lifespan of the packaged structure, and ensures the normal operation of internal chips and circuits. Finally, the molding compound 9 on the outside of the substrate 1 encapsulates the entire structure, preventing impurities from entering and buffering mechanical shocks. Through the coordinated work of the above structures, combined with the large-board packaging process of directly packaging the entire wafer and the entire Pnl substrate, not only is high-density, high-performance packaging achieved, but output is also increased, costs are reduced, defects in the wafer and substrate cutting process are reduced, and yield and packaging efficiency are improved.

[0032] Finally, it should be noted that the above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. An FC packaging structure, comprising a substrate (1), characterized in that: The top of the substrate (1) is fixedly connected to multiple clips (2), and the top of the substrate (1) is fixedly connected to multiple wafers (3). The bottom of each of the multiple wafers (3) is provided with a groove (4). The top of the substrate (1) is fixedly connected to a dielectric layer (5), and the top of the dielectric layer (5) is fixedly connected to a redistribution layer (6). The top of the redistribution layer (6) is provided with a protective component for protection. The outside of the substrate (1) is fixedly connected to a molding compound (9).

2. The FC packaging structure according to claim 1, characterized in that: The protective component includes an electromagnetic shielding layer (7), the bottom of which is fixedly connected to the top of the redistribution layer (6), and a protective layer (8) is fixedly connected to the top of the electromagnetic shielding layer (7).

3. The FC packaging structure according to claim 1, characterized in that: The card strip (2) is externally slidably connected to the inside of the trench (4), and the wafer (3) is nested on top of the substrate (1) by mSAP process.

4. The FC packaging structure according to claim 1, characterized in that: The redistribution layer (6) is fabricated using the C-mold molding method to complete the layer addition. The surface of the wafer (3) is fabricated using Fan-in technology to create an RDL, thereby achieving board-level packaging.

5. The FC packaging structure according to claim 1, characterized in that: The dielectric layer (5) is made of silicon nitride and is manufactured by compression molding.

6. An FC packaging structure according to claim 2, characterized in that: The electromagnetic shielding layer (7) is made of copper foil, and the protective layer (8) is made of polyimide.

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