Semiconductor device and electronic device
By using a patterned hard mask layer to protect the island membrane structure during the fabrication of MEMS pressure sensors, the problems of thickness non-uniformity and surface unevenness are solved, improving the stability and reliability of the device and preventing silicon pillar formation.
Patent Information
- Application Number
- CN202520007119.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-02
- Publication Date
- 2025-12-16
- Estimated Expiration
- 2035-01-02
AI Technical Summary
MEMS pressure sensors have poor uniformity in island membrane structure thickness and uneven surface, which affects the stability and reliability of the device and is prone to forming silicon pillars, leading to performance degradation.
A patterned hard mask layer containing voids and a protective layer is formed on the surface of a first substrate. This layer protects the thickness uniformity of the island film structure during etching, ensures the planarization of the island film structure surface, prevents silicon pillar formation, and enhances stress balance.
It achieves uniform thickness and planar surface of island membrane structure, improves device stability and reliability, and allows thickness adjustment according to requirements.
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Figure CN223674324U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, in particular to a semiconductor device and an electronic device. BACKGROUND
[0002] The MEMS pressure sensor is a frontier research field developed on the basis of the MEMS process, which is suitable for harsh environments such as high impact, high overload, conduction, corrosion and radiation, and is widely used in the fields of aerospace, electronics, industry and the like.
[0003] In the related art, as shown in the prior art, the thickness uniformity of the island film structure etched in the back cavity of the pressure sensor is poor, and the island film structure is not a planar structure, which affects the stability and reliability of the device. Figure 1 In the related art, as shown in the prior art, the thickness uniformity of the island film structure etched in the back cavity of the pressure sensor is poor, and the island film structure is not a planar structure, which affects the stability and reliability of the device. UTILITARIAN CONTENT
[0004] In the utilitarian content part, a series of simplified concepts are introduced, which will be further described in detail in the specific embodiment part. The utilitarian content part of the present application does not mean to try to limit the key features and necessary technical features of the claimed technical solution, nor does it mean to try to determine the protection scope of the claimed technical solution.
[0005] In view of the existing problems, the present application provides a semiconductor device, which comprises:
[0006] A first substrate and a second substrate arranged in a stack, a first surface of the first substrate and a second surface of the second substrate are joined;
[0007] A back cavity penetrating through the first substrate and extending into the second substrate, wherein an island film structure protruding downward is formed on the center area of the bottom surface of the back cavity;
[0008] A protective layer located on the lower surface of the island film structure.
[0009] Exemplarily, further comprising:
[0010] A stop layer located in the second substrate, the back cavity exposes part of the stop layer, and the island film structure is located on the lower surface of the stop layer.
[0011] Exemplarily, the protective layer comprises silicon oxide.
[0012] Exemplarily, further comprising:
[0013] A first dielectric layer located on the first surface of the first substrate, one side of the first dielectric layer away from the first substrate is joined with the second substrate.
[0014] Exemplarily, the first dielectric layer and the stop layer are the same material layer.
[0015] Exemplarily, the first dielectric layer and the stop layer comprise silicon oxide.
[0016] Exemplarily, further comprising:
[0017] a second dielectric layer on the first surface of the second substrate;
[0018] a passivation layer on the second dielectric layer.
[0019] Exemplarily, further comprising:
[0020] a wire resistance and a pressure sensitive resistance electrically connected to each other, in the substrate on the first surface side of the second substrate;
[0021] a conductive plug in the second dielectric layer and the passivation layer and electrically connected to the wire resistance;
[0022] a pad electrically connected to the wire resistance through the conductive plug.
[0023] Exemplarily, the passivation layer comprises silicon nitride.
[0024] In still another aspect, the present application provides an electronic device comprising the semiconductor device of any one of the above.
[0025] The semiconductor device and the electronic device of the present application can protect the island film structure by forming a protective layer on the lower surface of the island film structure, and the protective layer can protect the island film structure, thereby ensuring that the island film structure has a uniform thickness and a planar surface structure, effectively preventing the formation of silicon pillars on the island film structure, enhancing the effect of balancing the stress of the island film structure, and improving the stability and reliability of the device. The thickness of the island film structure can be adjusted according to the requirements. BRIEF DESCRIPTION OF DRAWINGS
[0026] The following drawings of the present application are hereby incorporated as part of the present application for the purpose of understanding the present application. The embodiments of the present application and their descriptions shown in the drawings are used to explain the principles of the present application.
[0027] In the drawings:
[0028] Figure 1 A cross-sectional schematic diagram of a MEMS pressure sensor in the related art is shown;
[0029] Figure 2 A topographic diagram of a part of a MEMS pressure sensor in the related art is shown;
[0030] Figure 3 A flowchart of a manufacturing method of a semiconductor device of one specific embodiment of the present application is shown;
[0031] Figures 4A to 4F Fig. 1 shows cross-sectional views of a semiconductor device obtained by sequentially performing a manufacturing method of a semiconductor device according to one embodiment of the present application;
[0032] Figure 5 Fig. 2 shows a schematic view of an electronic device according to one embodiment of the present application. DETAILED DESCRIPTION
[0033] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily obscure the present application.
[0034] It is to be understood that the present application can be carried out by different embodiments and that the embodiments presented are only by way of example. It is further to be understood that the present application is not limited to these embodiments but also covers any technically possible alternative. In the drawings, the size and relative sizes of layers and regions can be exaggerated for clarity. Like reference numerals designate like elements throughout.
[0035] It will be understood that when an element or layer is referred to as being "on" or "adjacent" another element or layer, it can be directly on or adjacent the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly adjacent" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms since such terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
[0036] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptions used herein interpreted accordingly.
[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0038] For a thorough understanding of the present application, reference will be made to the following detailed description, in conjunction with the accompanying drawings, in which:
[0039] In the related art, as shown in Figure 1 , the thickness uniformity of the island film structure etched in the back cavity of the pressure sensor is poor, the surface of the island film structure is not a planar structure, so that the island film structure has poor stress balancing effect; or, as shown in Figure 2 , a silicon column is formed on the island film structure, which seriously affects the stability and reliability of the device.
[0040] Therefore, in view of the foregoing technical problems, the present application proposes a manufacturing method of a semiconductor device, as shown in Figure 3 , comprising:
[0041] Step S1, providing a first substrate and a second substrate, a stop layer is formed in the second substrate;
[0042] Step S2, forming a patterned hard mask layer on a first surface of the first substrate, the hard mask layer has an empty area and a protection layer located in the empty area;
[0043] Step S3, the hard mask layer is bonded to the second surface of the second substrate away from the first substrate;
[0044] Step S4, a patterned photoresist layer is formed on the second surface of the first substrate, the photoresist layer has an opening exposing the first substrate, the opening corresponds to the empty area and the protection layer;
[0045] Step S5, etching is performed based on the photoresist layer to remove the first substrate corresponding to the opening and the second substrate corresponding to the empty area on the lower surface side of the stop layer, and leave the second substrate corresponding to the protection layer on the lower surface side of the stop layer as an island film structure.
[0046] The manufacturing method of the semiconductor device of the present application forms a patterned hard mask layer on the first surface of the first substrate, the hard mask layer has an empty area and a protection layer in the empty area, so that the protection layer can play a protective role for the island film structure in the subsequent etching process of the second substrate to form the island film structure, thereby ensuring that the island film structure has a uniform thickness, its surface is a planar structure, effectively preventing the formation of silicon pillars on the island film structure, enhancing the effect of balancing the stress of the island film structure, and improving the stability and reliability of the device, and the thickness of the island film structure can be adjusted according to the requirements.
[0047] Embodiment one
[0048] Next, with reference to Figures 4A to 4F The manufacturing method of the semiconductor device of the present application is described in detail, wherein, Figures 4A to 4F The cross-sectional schematic diagram of the semiconductor device obtained by sequentially implementing the manufacturing method of one specific embodiment of the present application is shown.
[0049] Exemplarily, the manufacturing method of the semiconductor device of the present application includes the following steps:
[0050] First, step one is performed, such as Figure 4A And Figure 4B The first substrate 110 and the second substrate 130 are provided, and the stop layer 131 is formed in the second substrate 130.
[0051] The first substrate 110 and the second substrate 130 can be any suitable semiconductor substrate, such as a bulk silicon substrate, which can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductor, including a multi-layer structure of these semiconductors, etc., or a silicon-on-insulator (SOI), a silicon-on-silicon-on-insulator (SSOI), a silicon-germanium-on-insulator (S-SiGeOI), a silicon-germanium-on-insulator (SiGeOI), and a germanium-on-insulator (GeOI), or can also be a double side polished wafer (DSP), a ceramic substrate such as an aluminum oxide, a quartz or a glass substrate, etc.
[0052] The stop layer 131 in the second substrate 130 can be silicon oxide or any other suitable material, without limitation.
[0053] Next, step two is performed, as shown in FIG. 2B, a patterned hard mask layer 120 is formed on the first surface of the first substrate 110, the hard mask layer 120 has an empty area 121 and a protection layer 122 in the empty area 121. Figure 4A
[0054] In some embodiments, forming the patterned hard mask layer 120 on the first surface of the first substrate 110, the hard mask layer 120 has an empty area 121 and a protection layer 122 in the empty area 121 includes the following steps S211-S213:
[0055] Step S211, forming a hard mask layer 120 on the first substrate 110.
[0056] The hard mask layer 120 can be formed by various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc. The material of the hard mask layer 120 can be silicon oxide, etc., without limitation. After forming the hard mask layer 120, a planarization process can also be performed on the hard mask layer 120. Non-limiting examples of the planarization method include mechanical planarization or chemical mechanical polishing planarization.
[0057] Step S212, forming a photoresist layer on the hard mask layer 120, the photoresist layer is defined with a pattern to be formed into the empty area 121 and the protection layer 122.
[0058] Specifically, a photoresist mask layer can be formed on the hard mask layer 120 obtained after step S211, and the photoresist mask layer is patterned by exposure, development and other processes to form a photoresist layer defining the to-be-formed empty area 121 and the protection layer 122.
[0059] In step S213, the hard mask layer 120 is etched based on the photoresist layer to form the empty area 121 and the protection layer 122 in the hard mask layer 120.
[0060] In actual manufacturing, the hard mask layer 120 can be etched by dry etching or wet etching. Taking wet etching as an example, the hard mask layer 120 not covered by the photoresist layer is removed by chemical reaction between the etchant and the hard mask layer 120, and the hard mask layer 120 covered by the photoresist layer is protected, so as to form the empty area 121 and the protection layer 122 in the hard mask layer 120.
[0061] Next, step three is performed, and as shown in Figure 4C the side of the hard mask layer 120 away from the first substrate 110 is bonded to the second surface of the second substrate 130.
[0062] Specifically, taking the example that the hard mask layer 120 includes silicon oxide, the side of the hard mask layer 120 away from the first substrate 110 can be bonded to the second surface of the second substrate 130 by silicon-oxygen bonding.
[0063] Next, step four is performed, and a patterned photoresist layer is formed on the second surface of the first substrate 110, the photoresist layer having an opening exposing the first substrate 110, the opening corresponding to the empty area 121 and the protection layer 122.
[0064] Taking the example that the photoresist layer formed on the second surface of the first substrate 110 includes positive photoresist, the photoresist layer formed on the second surface of the first substrate 110 has an opening exposing the first substrate 110, the opening corresponding to the empty area 121 and the protection layer 122 can include the following steps:
[0065] The positive photoresist is coated on the second surface of the first substrate 110, and then the positive photoresist is exposed based on a first mask having a corresponding pattern formed thereon, and then the exposed positive photoresist is developed by using a positive photoresist developer, the positive photoresist in the exposed area is dissolved in the positive photoresist developer, and the positive photoresist in the non-exposed area, i.e., the photoresist layer, is left. The photoresist layer formed has an opening exposing the first substrate 110, the opening corresponding to the empty area 121 and the protection layer 122.
[0066] For example, the photoresist layer formed on the second surface of the first substrate 110 includes a negative photoresist, the photoresist layer formed on the second surface of the first substrate 110 is patterned, the photoresist layer has openings exposing the first substrate 110, and the openings correspond to the air region 121 and the protection layer 122. The photoresist layer can include the following steps:
[0067] The negative photoresist is coated on the second surface of the first substrate 110, then a second mask is used, the second mask has a corresponding pattern defined thereon, the negative photoresist is exposed based on the second mask, and then developed using a negative photoresist developer. The negative photoresist in the unexposed area is dissolved in the negative photoresist developer, leaving the negative photoresist in the exposed area, that is, the photoresist layer. The photoresist layer formed has openings exposing the first substrate 110, and the openings correspond to the air region 121 and the protection layer 122.
[0068] Next, step five is performed, as shown in Figure 4E and 4F , etching is performed based on the photoresist layer to remove the first substrate 110 corresponding to the openings and the second substrate 130 corresponding to the air region 121 on the lower surface side of the stop layer 131, and leave the second substrate 130 corresponding to the protection layer 122 on the lower surface side of the stop layer 131 as an island film structure 132.
[0069] In actual manufacturing, etching can be performed by dry etching or wet etching. For example, wet etching is used, as shown in Figure 4E , the etchant first chemically reacts with the first substrate 110 to remove the first substrate 110 corresponding to the openings to expose the protection layer 122 and the second substrate 130 corresponding to the air region 121. Then, as shown in Figure 4F , the etchant continues to chemically react with the second substrate 130 exposed by the air region 121 to remove the second substrate 130. Since the second substrate 130 is provided with the stop layer 131, the etchant can only remove the second substrate 130 corresponding to the air region 121 on the lower surface side of the stop layer 131, leaving the second substrate 130 corresponding to the protection layer 122 on the lower surface side of the stop layer 131 as an island film structure 132.
[0070] For example, after removing the first substrate 110 corresponding to the openings and the second substrate 130 corresponding to the air region 121 on the lower surface side of the stop layer 131, a back cavity 190 is formed, and the island film structure 132 is located in the back cavity 190.
[0071] In one example, for example, as shown in Figure 4DAs shown, the second substrate 130 further includes a conductive plug 181 and a pad 182. The conductive plug 181 is formed in the dielectric layer 140 and the passivation layer 150, and is electrically connected to the conductive wire resistor 160. The pad 182 is formed in the dielectric layer 140 and the passivation layer 150, and is electrically connected to the conductive plug 181.
[0072] Next, as shown in FIG. 1C, the second substrate 130 further includes a dielectric layer 140 and a passivation layer 150. The dielectric layer 140 is formed on the first surface of the second substrate 130, and the passivation layer 150 is formed on the dielectric layer 140. Figure 4D
[0073] The dielectric layer 140 and the passivation layer 150 can be formed by various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc. The material of the dielectric layer 140 can be silicon oxide, etc., and the material of the passivation layer 150 can be silicon nitride, etc. After the dielectric layer 140 or the passivation layer 150 is formed, a planarization process can be performed on the dielectric layer 140 or the passivation layer 150. The planarization method can include mechanical planarization or chemical mechanical polishing, etc.
[0074] Next, as shown in FIG. 1D, the second substrate 130 further includes a conductive plug 181 and a pad 182. The conductive plug 181 is formed in the dielectric layer 140 and the passivation layer 150, and is electrically connected to the conductive wire resistor 160. The pad 182 is formed in the dielectric layer 140 and the passivation layer 150, and is electrically connected to the conductive plug 181. Figure 4D
[0075] Specifically, a photoresist mask layer can be formed on the passivation layer 150, and the photoresist mask layer is patterned by exposure, development, etc., to form a photoresist layer defining the conductive plug 181. Then, the dielectric layer 140 and the passivation layer 150 are etched based on the photoresist layer to form a contact hole in the dielectric layer 140 and the passivation layer 150. Then, a metal material of the conductive plug 181 is deposited in the contact hole to form the conductive plug 181 electrically connected to the conductive wire resistor 160.
[0076] After the formation of the conductive plug 181, the pad 182 metal material can be deposited on the passivation layer 150 by various deposition methods commonly used in the art, for example, can be formed by chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or atomic layer deposition (ALD) method, etc. Then, the deposited pad 182 metal material is patterned, leaving the pad 182 metal material electrically connected with the conductive plug 181 as the pad 182.
[0077] It is worth mentioning that the order of the above steps is only an example, and the order of the above steps can also be changed or alternated, etc. without conflict.
[0078] So far, the key manufacturing method of the semiconductor device of the present application has been introduced. For the complete device manufacturing, other pre-step, intermediate step or post-step are required, which will not be described here.
[0079] In summary, the manufacturing method of the semiconductor device of the present application, by forming a patterned hard mask layer 120 on the first surface of the first substrate 110, the hard mask layer 120 has an empty area 121 and a protective layer 122 located in the empty area 121, so that in the subsequent etching process of the second substrate 130 to form the island film structure 132, the protective layer 122 can play a protective role for the island film structure 132, thereby ensuring that the island film structure 132 has a uniform thickness, its surface is a planar structure, effectively preventing the formation of silicon pillars on the island film structure 132, enhancing the effect of balancing the stress of the island film structure 132, and improving the stability and reliability of the device, and the thickness of the island film structure 132 can be adjusted according to the requirements.
[0080] Embodiment two
[0081] The present application also provides a semiconductor device, which can be manufactured by the method of the foregoing embodiment one.
[0082] Next, with reference to Figure 4F The semiconductor device of the present application is described in detail and explained. It is worth mentioning that, in order to avoid repetition, the same parts and structures as in the foregoing embodiment one are only briefly described, and the specific explanation and description can be referred to the description in embodiment one.
[0083] Specifically, as Figure 4F shown, the semiconductor device of the present application comprises: a first substrate 110 and a second substrate 130 stacked one above the other, the first surface of the first substrate 110 and the second surface of the second substrate 130 are joined; a back cavity 190 penetrating through the first substrate 110 and extending into the second substrate 130, wherein a downwardly protruding island film structure 132 is formed on the bottom surface center area of the back cavity 190; a protective layer 122 located on the lower surface of the island film structure 132.
[0084] Specifically, the protective layer 122 can protect the island film structure 132, so as to ensure that the island film structure 132 has a uniform thickness, the lower surface of the island film structure 132 has a planar structure, the formation of silicon pillars on the island film structure 132 is effectively prevented, the effect of enhancing the stress balance of the island film structure 132 is achieved, and the stability and reliability of the device are improved. In addition, the thickness of the island film structure 132 can be adjusted according to requirements.
[0085] In one example, the first substrate 110 and the second substrate 130 can be any suitable semiconductor substrate, such as a bulk silicon substrate, which can also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, etc., or silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked germanium-silicon-on-insulator (S-SiGeOI), germanium-silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or double-side polished wafers (DSP), ceramic substrates such as aluminum oxide, quartz or glass substrates, etc.
[0086] In one example, the protective layer 122 can be silicon oxide or any other suitable material, which is not limited.
[0087] In one example, as shown in Figure 4F Further comprising: a first dielectric layer 120 on the first surface of the first substrate 110, and the side of the first dielectric layer 120 away from the first substrate 110 is bonded to the second surface of the second substrate 130.
[0088] In one example, the first dielectric layer 120 can be formed by the hard mask layer in the manufacturing method described above. Specifically, the hard mask layer formed on the first surface of the first substrate 110 outside the empty area 121 can be referred to as the first dielectric layer 120.
[0089] In one example, the material of the first dielectric layer 120 can be silicon oxide or the like, which is not limited. Taking the example that the first dielectric layer 120 includes silicon oxide, the side of the first dielectric layer 120 away from the first substrate 110 can be bonded to the second surface of the second substrate 130 by silicon-oxygen bonding.
[0090] In one example, as shown in Figure 4F Further comprising: a stop layer 131 in the second substrate 130, the back cavity 190 exposes part of the stop layer 131, and the island film structure 132 is on the lower surface of the stop layer 131.
[0091] By providing a stop layer 131 in the second substrate 130, when the second substrate 130 is etched with an etchant to form an island membrane structure 132, the etchant can only remove a portion of the second substrate 130 on one side of the lower surface of the stop layer 131, leaving the portion of the second substrate 130 on one side of the lower surface of the stop layer 131 corresponding to the protective layer 122 as the island membrane structure 132.
[0092] For example, the stop layer 131 in the second substrate 130 may be silicon oxide or any other suitable material, without limitation.
[0093] In one example, the first dielectric layer 120 and the stop layer 131 can be the same material layer. For example, both can be silicon oxide.
[0094] In one example, such as Figure 4F As shown, it also includes: a second dielectric layer 140, located on the first surface of the second substrate 130.
[0095] Exemplarily, the second dielectric layer 140 can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the material of the second dielectric layer 140 can be silicon oxide or the like, and there is no limitation thereto. Exemplarily, after forming the second dielectric layer 140, the method further includes planarizing the second dielectric layer 140. Exemplarily, non-limiting examples of this planarization method include mechanical planarization or chemical mechanical polishing planarization.
[0096] In one example, such as Figure 4F As shown, it also includes a passivation layer 150, located on the second dielectric layer 140.
[0097] The passivation layer 150 can be formed using various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the material of the passivation layer 150 can be silicon nitride, etc., and there is no limitation thereto. Exemplarily, after forming the passivation layer 150, the method further includes planarizing the passivation layer 150. Exemplarily, non-limiting examples of this planarization method include mechanical planarization or chemical mechanical polishing planarization.
[0098] In one example, such as Figure 4FAs shown, the semiconductor device further comprises: a wire resistor 160 and a varistor 170, which are formed in the substrate on the first surface side of the second substrate 130 and are electrically connected to each other; a conductive plug 181 formed in the second dielectric layer 140 and the passivation layer 150 and electrically connected to the wire resistor 160; and a pad 182 electrically connected to the wire resistor 160 through the conductive plug 181.
[0099] In one example, the semiconductor device of the present embodiment is a MEMS pressure sensor.
[0100] In one example, the semiconductor device of the present embodiment is a MEMS pressure sensor.
[0101] In one example, the semiconductor device of the present embodiment is a MEMS pressure sensor.
[0102] In one example, the semiconductor device of the present embodiment is a MEMS pressure sensor.
[0103] In one example, the semiconductor device of the present embodiment is a MEMS pressure sensor.
[0104] According to the semiconductor device of the present application, the method in embodiment one is adopted to manufacture, the protective layer 122 is formed on the lower surface of the island film structure 132, the protective layer 122 can protect the island film structure 132, so as to ensure that the island film structure 132 has a uniform thickness, the surface is a plane structure, the silicon column is effectively prevented from being formed on the island film structure 132, the effect of balancing the stress of the island film structure 132 is enhanced, and the stability and reliability of the device are improved, and the thickness of the island film structure 132 can be adjusted according to requirements.
[0105] Embodiment three
[0106] The present application also provides an electronic device in another embodiment, which comprises the semiconductor device manufactured according to the method described above.
[0107] The electronic device of the present embodiment can be a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a digital photo frame, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, or any other electronic product or device, or any intermediate product including a circuit. The electronic device of the present embodiment has better performance due to the use of the semiconductor device described above.
[0108] In the above embodiment, the semiconductor device is used in a mobile phone. Figure 5 An example of a mobile phone handset is shown. The mobile phone handset 400 is provided with a display portion 402, operation buttons 403, an external connection port 404, a speaker 405, a microphone 406, and the like included in a housing 401.
[0109] In the above embodiment, the semiconductor device is used in a mobile phone.
[0110] The present application has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and illustration, and are not intended to limit the present application to the described embodiments. In addition, those skilled in the art can understand that the present application is not limited to the above embodiments, and more various modifications and changes can be made according to the teachings of the present application, which all fall within the scope of the present application. The scope of protection of the present application is defined by the attached claims and their equivalent scope.
Claims
1. A semiconductor device, characterized by, The semiconductor device includes: a first substrate and a second substrate disposed in a vertical stack, a first surface of the first substrate and a second surface of the second substrate being joined; a back cavity extending through the first substrate and into the second substrate, wherein a bottom surface central region of the back cavity has a downwardly protruding island film structure formed thereon; a protective layer on a lower surface of the island film structure.
2. The semiconductor device of claim 1, wherein, Further comprising: a stop layer in the second substrate, the back cavity exposing the stop layer, the island film structure being on a lower surface of the stop layer.
3. The semiconductor device of claim 1, wherein, The protective layer includes silicon oxide.
4. The semiconductor device of claim 2, wherein, Further comprising: a first dielectric layer on the first surface of the first substrate, a side of the first dielectric layer facing away from the first substrate being joined to the second substrate.
5. The semiconductor device of claim 4, wherein, The first dielectric layer and the stop layer are the same material layer.
6. The semiconductor device of claim 5, wherein, The first dielectric layer and the stop layer include silicon oxide.
7. The semiconductor device of claim 1, wherein, Further comprising: a second dielectric layer on the first surface of the second substrate; a passivation layer on the second dielectric layer.
8. The semiconductor device of claim 7, wherein, Further comprising: a wire resistance and a piezoresistance electrically connected to each other, in a substrate on a first surface side of the second substrate; a conductive plug in the second dielectric layer and the passivation layer and electrically connected to the wire resistance; a pad electrically connected to the wire resistance through the conductive plug.
9. The semiconductor device of claim 7, wherein, The passivation layer includes silicon nitride.
10. An electronic device, comprising: The electronic device includes the semiconductor device according to any one of claims 1 to 9.