IO circuit with logic memory function
By combining non-volatile memory units with I/O drive circuits in industrial control systems, the problem of inconsistent output after power failure is solved, achieving stability and flexibility of circuit output while reducing cost and size.
Patent Information
- Application Number
- CN202520065494.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-13
- Publication Date
- 2025-12-16
- Estimated Expiration
- 2035-01-13
AI Technical Summary
The lack of devices with memory retention function in existing industrial control systems leads to inconsistent outputs after power failure, resulting in losses. Traditional magnetic latching relays are expensive and bulky.
It combines non-volatile memory cells with I/O drive circuits, uses ferroelectric crystals or magnetic materials to maintain the logic state, and uses read/write control pins to control data readback and output, ensuring consistent output before and after power failure.
It achieves unchanged output before and after power failure, improves system stability, has a simple structure and small size, and is flexible in configuration.
Smart Images
Figure CN223679542U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to the industrial control field relates to a IO circuit with logic memory function. BACKGROUND
[0002] In the industrial control field, especially the system such as I / O control involving safety protection, all require that the equipment has the power-off protection function, and the power-off protection function refers to the output before power-off can be kept after the power-off restart of industrial control, to avoid the inconsistent output before and after power-off, causing irreparable loss.
[0003] There is no device-level transistor, logic gate or switching device with memory-keeping function on the market, and there is no device with logic state keeping after power-off, and the traditional scheme generally uses magnetic latching relay to realize, and the cost is heavy, and the volume is large. SUMMARY
[0004] The utility model discloses a kind of IO circuits, can realize the output keeping unchanged before and after power-off of circuit, improve system commissioning stability to solve the defects in prior art.
[0005] To achieve the above purpose, the technical scheme provided by the utility model is as follows:
[0006] A kind of IO circuit with logic memory function, including storage circuit and I / O drive circuit;Storage circuit is connected with IO drive circuit;Storage circuit includes storage unit, and read / write control pin for reading back data and sending data;Storage unit is connected with read / write control pin;Storage unit uses nonvolatile storage unit;I / O drive circuit includes I / O drive unit and output pin, I / O drive unit is connected with output pin.
[0007] The utility model controls I / O drive circuit output logic level by nonvolatile storage unit, to realize the output keeping unchanged before and after power-off of circuit.Meanwhile, read / write control pin is used to realize data reading back and output: the moment of power-off recovery, write pin is not enabled, only data can be read back, and circuit default output is stored in storage unit, when write pin is enabled, data is allowed to be sent.
[0008] Further, storage unit uses ferroelectric crystal or magnetic material, and data storage is carried out using ferroelectric effect or the characteristics of magnetic material.
[0009] Further, the I / O driving unit comprises a bit operation register, an output control register, a P-MOS and an N-MOS; when the I / O driving unit is configured in an open-drain output mode, when the value of the set output is high, the output control register is set to "1", the P-MOS and the N-MOS are both in a closed state, and the output pin of the corresponding I / O driving circuit is in a high-impedance state; when the I / O driving unit is configured in the open-drain output mode, when the value of the set output is low, the output control register is set to "0", the P-MOS is in a closed state, the N-MOS is in a conducting state, and the output pin of the corresponding I / O driving circuit is in a low-level state; when the I / O driving unit is configured in a push-pull output mode, when the value of the set output is high, the output control register is set to "1", the P-MOS is in a conducting state, the N-MOS is in a closed state, and the output pin of the corresponding I / O driving circuit outputs a high level; when the I / O driving unit is configured in the push-pull output mode, when the value of the set output is low, the output control register is set to "0", the P-MOS is in a closed state, the N-MOS is in a conducting state, and the output pin of the corresponding I / O driving circuit outputs a low level.
[0010] The logic output function of the I / O driving unit is realized by configuring the driving mode of the I / O output pin.
[0011] Compared with the prior art, the I / O circuit with the logic memory function has the following advantages:
[0012] The I / O circuit with the logic memory function has the following advantages:
[0013] The I / O circuit with the logic memory function has the following advantages:
[0014] The I / O circuit with the logic memory function has the following advantages: BRIEF DESCRIPTION OF DRAWINGS
[0015] Figure 1This is a structural block diagram of the I / O circuit with logic memory function of this utility model;
[0016] Figure 2 This is a flowchart illustrating the operation of the I / O circuit with logic memory function according to this utility model.
[0017] Figure 3 for Figure 1 A schematic diagram of the structure of the I / O drive unit. Detailed Implementation
[0018] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.
[0019] like Figure 1 As shown: This utility model includes a storage circuit and an I / O driver circuit. The storage circuit includes storage cells and read / write control pins. The storage cells are made of a non-volatile material and have power-off data retention capabilities. Each storage cell controls an I / O driver circuit to output a corresponding logic level. The write control pins include write enable and write data. The write enable pin is pulled high by default, supporting data readback. When the write enable pin is low, data transmission is allowed.
[0020] The circuit receives data from the processor, host computer, or other control modules, which can read back the data in the storage unit, parse the data to be sent bit by bit, pass it to the storage unit, and then control the I / O drive unit to output the corresponding logic level. The storage unit can then be modified bit by bit.
[0021] like Figure 2 As shown: When the circuit experiences a power outage and subsequent recovery, initially, the write control pin is disabled upon power-up, allowing only data to be read back. The circuit defaults to outputting the data stored in the memory unit. Once the write control pin is enabled, the circuit can choose to maintain the logic state before the power outage or re-output using a new logic level, depending on the actual needs. Because the data in the memory unit is preserved after power loss, the read-back data remains consistent with the data before the power outage upon power-up, and the logic level output by the control I / O drive unit also remains unchanged, thus achieving the function of maintaining the logic state after power loss. If a new logic level is used for re-output, new data can be written directly.
[0022] like Figure 3 As shown, each I / O drive unit contains a bit manipulation register, an output control register, a P-MOS, and an N-OMS.
[0023] More specifically, in the open drain output mode, when the value of the set output is high, both P-MOS and N-MOS are in the closed state, at this time, the high resistance, the level of the I / O port is not determined by the high and low level of the output, but by the pull-up or pull-down outside the I / O port; when the value of the set output is low, the P-MOS is closed, and the N-MOS is turned on, at this time, the level of the I / O port is low. In the push-pull mode, when the value of the set output is high, the P-MOS is turned on, and the N-MOS is closed, and the high level is outputted externally; when the value of the set output is low, the N-MOS is turned on, and the P-MOS is closed, and the low level is outputted externally.
[0024] Although the utility model has disclosed as above with preferable embodiments, it is not used to limit the utility model. Those skilled in the art to which the utility model belongs can make various changes and decorations without departing from the spirit and scope of the utility model. Therefore, the protection scope of the utility model shall be defined by the claims.
Claims
1. An IO circuit with a logic memory function, characterized by comprising: an IO circuit (1) having a logic memory function; and a logic memory (2) having a logic memory function. The application relates to a memory circuit and I / O drive circuit; the memory circuit is connected with the I / O drive circuit; the memory circuit comprises a memory unit and read / write control pins for reading and sending data; the memory unit is connected with the read / write control pins; the memory unit adopts a non-volatile memory unit; The I / O drive circuit comprises an I / O drive unit and output pins; the I / O drive unit is connected with the output pins.
2. The IO circuit of claim 1, wherein, The memory unit adopts a ferroelectric crystal or magnetic material.
3. The IO circuit of claim 1, wherein, The I / O drive unit comprises a bit operation register, an output control register, a P-MOS and an N-MOS; when the I / O drive unit is configured as an open-drain output mode and the set output value is high, the output control register is set as "1", the P-MOS and the N-MOS are both in the closed state, and the output pins of the corresponding I / O drive circuit are in the high resistance state; when the I / O drive unit is configured as the open-drain output mode and the set output value is low, the output control register is set as "0", the P-MOS is in the closed state, the N-MOS is in the conducting state, and the output pins of the corresponding I / O drive circuit are in the low voltage state; when the I / O drive unit is configured as a push-pull output mode and the set output value is high, the output control register is set as "1", the P-MOS is in the conducting state, the N-MOS is in the closed state, and the output pins of the corresponding I / O drive circuit output high voltage; when the I / O drive unit is configured as the push-pull output mode and the set output value is low, the output control register is set as "0", the P-MOS is in the closed state, the N-MOS is in the conducting state, and the output pins of the corresponding I / O drive circuit output low voltage.